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In this paper, the analysis of a current feedback compensation architecture compatible with pixels having the 2-transistors and 1-capacitor structure is evaluated. The aim of the circuit presented and analyzed, is to cleanly reach a programming pixel current level below 50 nA with an average 10% of error. Here, we also present the method to achieve robustness in the operation of the loop, observed through a series of measurements. All the peripheral blocks implementing the design are presented and analyzed through simulations as well as verified experimentally. Sources of noise are identified and eliminated, while the new techniques for better isolation from digital noise are described and tested on a newly fabricated driver. Multiple versions of the previously proposed circuit are outlined, simulated, fabricated, and measured to evaluate their performance.

This paper reports the characteristics of a-IGZO TFTs and circuits fabricated on conformable aluminum substrates. TFTs with field-effect mobility of up to 15.3 cm2/V s, average threshold voltage of 5.2 V, and off current less than 10−12 were demonstrated at zero strain; applying mechanical tensile strain up to 1.25% through bending was found to have a beneficial result to the device characteristics as mobility increased and threshold voltage decreased. These results highlight the potential of aluminum substrates for the use in future display and other large area electronics applications.

High performance thin film transistor (TFT) arrays and circuits on engineered aluminum substrates are reported. Aluminum substrates were engineered to have a smooth insulating surface suitable for device fabrication upon them. Amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors with an average field effect mobility of about 10 cm2/Vs, threshold voltage of 5 V, gate leakage current of 10−13 and on/off current ratio of 108 are demonstrated. Metal oxide transistors and circuits built on aluminum substrates open a route for future applications in large area flexible electronics.

A new feedback current programming architecture is described, which is compatible with active matrix organic light-emitting diode (AMOLED) displays having the 2T1C pixel structure. The new pixel programming approach is compatible with all TFT technologies and can compensate for non-uniformities in both threshold voltage and carrier mobility of the pixel OLED drive TFT. Based on circuit simulations, a pixel drive current of less than 10 nA can be programmed in less than 50 µ. This new approach can be implemented within an AMOLED external or integrated display data driver.

In this paper, we present fabrication and characterization of RF sputtered a-IGZO TFTs having a modified etch stopper structure with source/drain contact windows on glass wafers. The effect of annealing time and channel length on device performance in terms of mobility, on/off current ratio, average off current, threshold voltage, and sub threshold slope is reported.

A new feedback current programming architecture is described that is compatible with AMOLED displays having the 2T1C pixel structure. The new pixel programming approach is compatible with all TFT technologies and can compensate for non-uniformities in both threshold voltage and carrier mobility of the pixel OLED drive TFT. Based on circuit simulations a pixel drive current of less than 10nA can be programmed in less than 50μsec. This new approach can be implemented within an AMOLED external or integrated display data driver.

SUMMARY In this paper, the design and simulation of a tactile display that is based on a capacitive micromachined ultrasonic transducer (CMUT) array is presented. The array implements a ‘pixel’ of the display and is used to focus airborne ultrasound energy on the skin surface. The pressure field generated by the focused ultrasound waves excites the mechanoreceptors under the skin and transmits tactile information. The geometry of the individual transducer and the array are optimized so that the medium presents maximum impedance and the membrane oscillates with maximum deflection. Optimization is achieved using an electrical equivalent circuit model and the Berkeley Simulation Program with Integrated Circuit Emphasis (SPICE) code. Finite element analysis of the CMUT and the CMUT phased array is used to verify the SPICE results. The pressure at focal point is compared with the pressure threshold required for mechanoreceptor excitation in order to verify the feasibility of the design. Copyright © 2012 John Wiley & Sons, Ltd.

In this article, we present the design of a tactile display based on a CMUT-phased array. The array implements a ‘pixel’ of the display and is used to focus airborne ultrasound energy on the skin surface. The pressure field, generated by the focused ultrasound waves, is used to excite the mechanoreceptors under the skin and transmit tactile information. The results of Finite Element Analysis (FEA) of the Capacitive Micromachined Ultrasonic Transducer (CMUT) and the CMUT-phased array for ultrasound emission are presented. The 3D models of the device and the array were developed using a commercial FEA package. Modelling and simulations were performed using the parameters from the POLYMUMPS surface micromachining technology from MEMSCAP. During the analysis of the phased array, several parameters were studied in order to determine their importance in the design of the tactile display. The output of the array is compared with the acoustic intensity thresholds in order to prove the feasibility of the design. T...

In order to realize a high resolution and high throughput printing method for thin film transistor application, a modified offset roll printing was studied. This roll printing chiefly consists of a blanket with low surface energy and a printing plate (cliche) with high surface energy. In this study, a finite element analysis was done to predict the blanket deformation and to find the optimal angle of cliche's sidewall. Various etching methods were investigated to obtain a high resolution cliche and the surface energy of the blanket and cliche was analyzed for ink transfer. A high resolution cliche with the sidewall angle of 90^o and the intaglio depth of [email protected] was fabricated by the deep reactive ion etching method. Based on the surface energy analysis, we extracted the most favorable condition to transfer inks from a blanket to a cliche, and thus thin films were deposited on a Si-cliche to increase the surface energy. Through controlling roll speed and pressure, two inks, etch-resist and silver paste, were printed on a rigid substrate, and the fine patterns of [email protected] width and [email protected] line spacing were achieved. By using this printing process, the top gate amorphous indium-gallium-zinc-oxide TFTs with channel width/length of 12/[email protected] were successfully fabricated by printing etch-resists.

In order to use Al–2 at.%Nd as the source-drain electrode of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) without diffusion barrier, the diffusion characteristics of Al–2 at.%Nd into phosphorus-doped (n+) a-Si:H were studied, and diffusion between Al–2 at.%Nd and phosphorous-doped poly-Si (n + poly-Si) was also investigated for comparison. The electric resistance variation of Al–2 at.%Nd, n + a-Si:H, and n + poly-Si was measured by four-point probe method at every annealing step, and each surface was inspected by optical microscope. Auger Electron Spectroscopy and X-ray Photoelectron Spectroscopy were used to analyze atomic diffusion progress with the variation of annealing temperature. Through these analyses, we ascertain that the Nd element of Al–2 at.%Nd hinders the diffusion between Al and Si, and n + a-Si:H is stable up to 300 °C and n + poly-Si is stable up to 400 °C against the diffusion of Al–2 at.%Nd. Thus Al–2 at.%Nd can be utilized as the source-drain electrode of a-Si:H TFTs below 300 °C and poly-Si TFTs below 400 °C without diffusion barrier.

In this paper, voltage noise of lateral polysilicon p-i-n diodes, biased at constant current levels, is studied. The polysilicon film that forms the active material of the p-i-n diodes was prepared by the crystallization of amorphous silicon either by the solid phase crystallization (SPC) or the sequential lateral solidification (SLS) method; two different thicknesses of 100 and 50 nm were also investigated. Measurement results of the voltage noise at frequency bandwidth from 500 Hz to 1 MHz for polysilicon p-i-n diodes with different crystallization methods and active material thicknesses are presented. The effects of grain size, i-region geometry, and the biasing current on the voltage noise of p-i-n diodes are studied. Furthermore, different methods of improving the voltage noise of p-i-n diodes are also discussed, and experimental results are demonstrated.

In an effort to increase the integration level of large area digital and mixed-signal systems on flexible substrate, we designed and successfully fabricated and characterized a 3-bit flash analog to digital converter on stainless steel foil substrate. High quality laser crystallized polysilicon Thin Film Transistors (TFT) as well as carefully designed comparator circuit made it possible for a high performance flash ADC with maximum sampling rate of 3 Ms/s to be developed on stainless steel foil substrate. Both Integral and Differential Non-Linearity were extracted to be less than or equal to 0.25th of a Least Significant Bit (LSB), which makes it possible to increase the number of bits to 5-bits while keeping the same design structure and operating voltages. The same 3-bit design can also be used along with a 3-bit digital to analog converter in a two-step flash ADC structure to implement a 6-bit converter.

Electronic structures of the rare earth trifluorides CeF3 ( P 3 ¯ c 1 ) and TbF3 (Pnma) were examined by high-resolution valence-band X-ray photoelectron spectroscopy (VB-XPS) and all-electron periodic-crystal DFT theory including the spin-polarization (SP) combined with spin–orbit (SO) coupling using a second-variational treatment. Calculations using the Perdew–Burke–Ernzerhof (PBE) functional and the LDA+U method were carried out and compared. The results show that a complete analysis does require a full DFT–SP–SO treatment to obtain a quantitative account for the observed VB-XPS spectra, with an additional insight of the theory with regard to the nature of the topmost orbitals, and the bonding–antibonding character of orbitals within the VB and sub-VB levels. The band structure at the bottom of the conduction band (BCB) shows a strong dispersion in TbF3 but not in CeF3, predicting photoconductivity in TbF3.

The effects of uniaxial tensile strain on the performance of polycrystalline silicon thin-film transistors (poly-Si TFTs) is reported. Longitudinal strain increases the electron mobility and decreases the hole mobility, while transverse strain decreases the electron mobility and slightly decreases the hole mobility. Under longitudinal strain the off current decreases for both NMOS and PMOS TFTs and shifts in threshold voltage and substhreshold slope are observed for p-channel TFTs. A strong dependence on channel length for both electron and hole mobilities under longitudinal strain indicates the presence of a series resistance. For poly-Si TFTs, the mobility changes under strains are related to the strain effects on single crystalline silicon devices.

In this paper the influence of mechanical tensile strain on the performance of thin film transistors (TFTs), with various channel geometries, and of ring oscillators, with 3, 7, 11, 21, and 51 number of stages and device channel lengths of 1, 4, and 8 μm, fabricated on stainless steel foil substrate is investigated. TFT parameters such as field effect mobility, threshold voltage, subthreshold slope, leakage and gate current for both n-channel, and p-channel TFTs are studied at various longitudinal tensile strain levels. For strain levels from 0.0% to 0.5%, the field effect mobility of n-channel TFTs increases while that of p-channel ones decreases as the longitudinal tensile strain increases. The field effect mobility, of both n-channel and p-channel TFTs, becomes independent of longitudinal tensile strain at strain levels greater than 0.5%. Threshold voltage and subthreshold slope of p-channel TFTs increases while that of n-channel ones does not follow a specific trend. The leakage current of both type devices tends to decrease by increasing the longitudinal tensile strain. The propagation delay, per inverter stage of a ring oscillator, is investigated at different supply voltages and tensile strain levels. The propagation delay of inverters with longer device channel length (⩾4 μm) tends to decrease while that of shorter length tends to increase as the longitudinal tensile strain increases.

Polycrystalline silicon obtained by the crystallization of thin amorphous silicon films has been an important material for microelectronics technology during the last decades. Many properties are improved in crystallized amorphous silicon compared to the as-deposited polysilicon such as larger grain size, smoother surface, and higher-carrier mobility. In this work, the crystallization of amorphous silicon is investigated by combining transmission electron microscopy (TEM) observations and molecular dynamics calculations. TEM observations on a series of specimens have shown that the majority of the silicon grains are oriented with a $$ {\left\langle {110} \right\rangle} $$ zone axis normal to the surface. In order to understand the crystallization mechanism molecular dynamic simulations were performed. It is found that the $$ {\left\langle {110} \right\rangle} $$ c/amorphous interface exhibits the lowest reduced interfacial energy density while the $$ {\left\langle {111} \right\rangle} $$ c/amorphous has the lowest reduced energy differences per unit interfacial area. The most energetically unfavorable interface is $$ {\left\langle {001} \right\rangle} $$ c/amorphous.

An n-type multiple-gate laser-crystallized Poly-Silicon Thin Film Transistor (TFT) is introduced as a high voltage (Vg>30v, Vds>35v) moderate current (I=50mA) TFT structure for general purpose, matrix format actuator application on stainless steel substrate. The off-state performance of the device has been simulated and studied by the Silvaco software package and the performance of the structure has been compared with the commonly used High Voltage (HV) TFT structures.

Mesoporous silica materials derivatized with propyl-sulfonic groups (SBA-15) with a monovalent cation-exchange capacity of ∼1 meq/g were exchanged with Ce(III) ions to ∼0.5 meq/g to form Ce(III)SBA material displaying high-intensity purple photoluminescence. XPS and NIR-DRS analysis suggests the Ce(III) ion is bound to two proximal propyl-sulfonate groups and capped with a hydroxyl in a complex [≡Si−(CH2)3SO3]2Ce(III)OH·xH2O (x > 4), where the coordinated water can be almost completely removed by anoxic dehydration at 350 C to x < 0.2. The white hydrated (x ≥ 4) CeSBA and the brown-colored dehydrated (x < 0.2) CeSBA exhibit fluorescence with comparable integrated intensities at 368 and 394 nm, respectively. The Ce(III) 4f electron is located by XPS above the top of the Si 3p O 2p valence band, thus identifying the Ce(III) 4f orbital as the HOMO. Photoluminescence emission and excitation spectra of the 5d → 4f transition display Stokes shifts and structure sensitivity consistent with a direct transition pr...

A micro scale glass reactor was designed, fabricated and characterized with Water Gas Shift Reaction (WGSR). The fabrication procedure was quick, uncomplicated, template-free and inexpensive and did not require any special clean room facility, making it ideal for first generation prototyping. The fabricated unit was able to withstand pressure and temperature of 1.65 MPa and 260 °C respectively. An important reaction in micro scale fuel processing, namely WGSR, was carried out in this microreactor using a packed bed of 50–75 μm commercial catalyst particles at 185–250 °C. The design sizing was based on a CO flow of 0.06 mol/h. Experimental results were used to develop a kinetic model of the reaction.

This paper presents a 230 dpi Active Matrix Polymer Light Emitting Diode (AMPLED) display on flexible stainless steel substrates fabricated with laser annealed poly-silicon TFT technology. The high resolution display is based on the standard 2 TFT pixel circuitry to form a full VGA array. Polysilicon TFT based shift registers for integrated row driving are also demonstrated. Display fabrication is compatible with standard polysilicon TFT CMOS processing temperatures and conditions. This paper discusses backplane fabrication, PLED deposition and display encapsulation; all performed in-house.

The first successful integration of poly-Si thin-film- transistor (poly-Si TFT) backplane with polymer light-emitting diodes (PLEDs) onto a flexible stainless-steel foil is described, and a high-resolution (230 DPI) monochrome active- matrix polymer light-emitting diode (AM-PLED) display is demonstrated. The process technology required to implement this high-resolution AM-PLED display onto a flexible metal foil substrate is discussed. This technology primarily consists of the preparation of flexible metal foils, fabrication of the poly-Si TFT backplane, and integration with top-emitting PLEDs.

This paper presents a study on several polysilicon TFT circuits that may be used for highly integrated electronic systems on flexible metal foils. The circuit performance presented here validates the polysilicon TFT metal foil technology as a suitable platform for the incorporation of control, processing and communication circuits onto a flexible system. This research addresses digital, analog and mixed signal polysilicon thin film transistor (TFT) circuits exploiting metal foil device assets, while complying with design and fabrication parameters of flexible substrates. This paper reports some of the highest electron mobilities recorded to date on TFTs fabricated on metal foils (over 300 cm2/V s) and presents data on high performance circuits including: shift registers running at speeds over 10 MHz, ring oscillators with stage frequency response over 1 GHz and mixed signal circuits for row and column display driving. This is one of the most comprehensive reports to date on general purpose circuits on stainless steel foils.

This paper discusses in detail the design and fabrication process for the realization of high-performance polycrystalline silicon thin-film transistors and digital CMOS circuitry on thin flexible stainless steel foils. A comprehensive approach to substrate preparation is first presented. For transistor fabrication, distinct processing approaches are examined, such as solid-phase and excimer laser crystallization for the active semiconductor region, thermal growth and chemical vapor deposition for the gate insulator, and others. It is shown that process optimization has resulted in the fabrication of CMOS transistors with field-effect mobility values in the region of 200 cm/sup 2//V/spl middot/s and I/sub ON//I/sub OFF/ current ratios of at least seven orders of magnitude. The design and performance of high-speed digital CMOS is addressed, and the effects of the conductive foil through parasitic capacitive coupling are examined. CMOS inverter blocks in ring oscillator circuits operating with delay times as low as 1.12 ns are reported, as well as static and dynamic shift registers operating in the megahertz regime.

Flexible, large area electronics - macroelectronics - using amorphous silicon, low-temperature polysilicon, or various organic and inorganic nanocrystalline semiconductor materials is beginning to show great promise. While much of the activity in macroelectronics has been display-centric, a number of applications where macroelectronics is needed to enable solutions that are otherwise not feasible are beginning to attract technical and/or commercial interest. In this paper, we discuss the application drivers and the technology needs and device performance requirements to enable high performance applications to include RF systems.

Lateral polysilicon p+–p–n+ and p+–n–n+ diodes are fabricated and their electrical characteristics, such as ON-resistance, ideality factor and reverse current, are studied as a function of the polysilicon microstructure, the type and amount of doping in the lightly doped region and the length of the lightly doped region. Increasing the polysilicon grain size reduces the ON-resistance. The ON-resistance decreases while the reverse current increases with an increase in the amount of doping in their lightly doped region. The ON-resistance is higher and the reverse current is lower in diodes having p-type lightly doped regions. With an increase in the length of the lightly doped regions, the ON-resistance increases, while the reverse current does not change. The ideality factor does not depend upon the length of the lightly doped region, type of doping in this region and the grain size of polysilicon. The experimental observations are explained using a combination of field enhanced emission and a formulation that considers the effect of the grain-boundary segregation of dopants.

Lateral polysilicon P+–N–N+ and P+–P–N+ diodes were fabricated and their reverse current was measured at various temperatures in the range of 50°C to 150°C. The reverse current at a constant bias was characterized and used as a parameter to determine temperature by a method proposed in this work for possible application in a chemical microreaction system. Polysilicon diodes in a series combination of 2 or 3 were also fabricated and their electronic properties such as ON resistance, reverse current and ideality factor were studied. The ON resistance and the ideality factor increased linearly with the number of diodes in series, owing to the effect of the series combination of diodes. The multiple diodes also showed a lower reverse current than the individual single diodes in the series. Hence, it is beneficial to use these multiple diodes as temperature sensors, since they give the least error in temperature determination.

A novel palladium-based micromembrane is reported that can be used for hydrogen gas separation in a miniature fuel processor for micro fuel cells. The micromembrane structure is built in a silicon substrate, using standard MEMS microfabrication processes. Four layers, viz. copper, aluminum, spin-on-glass (SOG) and palladium form the composite membrane. Copper, aluminum and SOG layers provide structural support for the palladium film. Copper can act as catalyst in the water gas shift reaction that converts unwanted carbon monoxide gas into hydrogen. Palladium is used to separate hydrogen from other gases present. The micromembrane selectively separates hydrogen from a 20:80 hydrogen:argon gas mixture by weight even at room temperature. The diffusion of hydrogen through palladium is enhanced at higher temperatures and pressures, closely following the predictions from Sievert's law. Future applications of this micromembrane for simultaneous water gas shift reaction and hydrogen separation are discussed.

Bottom-gate metal-over-active (MOA) and active-over-metal (AOM) amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs), with channel lengths varying from 1 to 16 μm, are investigated with low-frequency noise (LFN) measurements in the linear region of operation. In the low drain-current range, LFN originates from carrier number fluctuations, whereas in the high drain-current range, the noise is affected by the series resistance. The extracted gate-insulator trap densities near the interface lead to the conclusion that the AOM a-IGZO TFTs are superior compared to the MOA devices.

We present a simple analytical model that accounts for the effects of temperature on the propagation delay of the CMOS inverter, implemented with polycrystalline silicon (polysilicon) thin film transistors. We have also fabricated polysilicon CMOS inverters with a variety of crystallization methods. We measure their switching speed as a function of temperature, and compare the results with the analytical model’s predictions. The experimental data are shown to be in excellent agreement with the developed model, which constitutes an effective tool for modeling the impact of temperature on polysilicon digital circuits.

We have fabricated thin film transistor operational amplifiers on a variety of polycrystalline silicon films. We have examined the open loop DC gain of these modules, and have observed that higher quality polycrystalline silicon films usually cause a negative impact on the DC gain of the amplifier. In this paper we have attempted to quantify this relationship, presenting the gain as a function of the transistor mobility, threshold voltage and channel length modulation parameter, which collectively can describe the quality of the active film. We have found that primarily the saturation characteristics of the transistor, as represented by the channel length modulation parameter, and the device threshold voltage have the biggest impact on amplifier gain.

International audience; The low-frequency noise of bottom-gate amorphous IGZO thin-film transistors is investigated in the low drain current range. The noise spectra show generation-recombination (g-r) noise at drain currents I d

We have successfully fabricated a full-bit shift register with low temperature amorphous indium gallium zinc oxide (a-IGZO) technology. Bottom-gate, staggered a-IGZO thin film transistors (TFTs) are fabricated with radio frequency-sputtered IGZO thin films with plasma-enhanced chemical vapor deposition deposited SiO2 as a gate dielectric and sputtered Mo as source, drain, and gate electrodes. The a-IGZO TFTs provide a good scalability and present field effect mobility in the range of 9–11 cm2/Vs. Integrated a-IGZO full-bit shift register consists of only 12 transistors per stage and operates at rail to rail voltage of about 18V. Stable full-bit shifting operation at a maximum operating frequency of about 25 kHz is confirmed.

A new simple unified analytical compact model for the amorphous InGaZnO Thin Film Transistors is proposed based on an analytical drain current model that uses a Gaussian distribution of subgap states, which is approximated by two exponential distributions. The model is continuous on all regions of operation, accurate also for the first derivatives of the transfer and output characteristics. A simple model is also proposed for the mobility to simulate the super-linear behavior of the drain current for low drain voltages. The model is verified for experimental data in all regions of operation and also for the transconductance and drain conductance of the transistors.

The integration of active matrix polysilicon TFT technology with organic light emitting diode (OLED) displays has been investigated with the goal of producing displays of uniform brightness. This work identifies and addresses several process integration issues unique to this type of display which are important in achieving bright and uniform displays. Rapid thermal processing has been incorporated to achieve uniform polysilicon microstructure, along with silicides to reduce parasitic source and drain series resistance. Using these processes, TFT drain current nonuniformity has been reduced below 5% for 90% of the devices. This work also introduces transition metals to produce low resistance contacts to ITO and to eliminate hillock formation in the aluminum metallization. These processes, along with spin on glasses for planarization, have been used to produce functional active matrix arrays for OLED displays. The final array pixel performance is also presented.

We have designed, fabricated, and successfully characterized a ten-stage half-bit shift register utilizing amorphous In-Ga-Zn-O (a-IGZO) thin-film-transistor (TFT) technology. High-performance bottom-gate staggered TFT structures with aluminum source, drain, and gate electrodes and RF-sputtered a-IGZO active material has been developed with a field-effect mobility of 16 cm2/V ·s. The half-bit shift register, which consists of only seven transistors per stage, has been successfully driven at a maximum clock frequency of 40 kHz (sufficient to drive a full VGA display at a frame rate of more than 80 kHz) and minimum rail-to-rail supply voltage of 20 V. This effort further demonstrates the potential of oxide-TFT technology to be employed for systems with higher integration level.

The effects of flash EEPROM floating gate (FG) morphology on the generation and density of fast programming bits in a 2Mbit flash EEPROM array has been characterized. These fast programming bits exhibit identical subthreshold characteristics similar to that of a normal bit after UV erase, thus establishing that the initial charge stored on the FG of both fast and normal bit is the same. Experimental results clearly indicates that the fast programming phenomena result from an interaction of the programming process with the FG polysilicon microstructure. An in-depth experimentation previously reported, reveals that the FG poly deposition and doping processes are crucial for controlling the desired Fowler–Nordheim tunneling. A correlation is established between the fast bit density observed in the memory arrays, the FG polysilicon grain size and tunneling field enhancement factor μ(Rc). A compact model of the fast programming bit memory threshold voltage as a function of the effective FG polysilicon grain area factor Geff, and tunneling field enhancement factor μ(Rc) has been developed for the first time.

This paper investigates the characteristics of high performance lateral polysilicon diodes. Low leakage currents and high ON currents were achieved using a gated PIN diode structure. An independent control gate terminal was placed over the intrinsic region of the diodes to improve the properties of the polysilicon diodes. The addition of the control gate was found to improve both the ON resistance and the leakage current by an order of magnitude. The gated PIN diodes had leakage currents less than 0.05 pA lm ˇ1 width at 5 V of reverse bias, and ON resistance less than 1 M Xl m ˇ1 width for an intrinsic region length of 2 lm. A gated PIN diode model is presented that models the diode as an ideal diode in series with a thin film transistor. This model is used to explain the impact of the control gate on the ON resistance and the leakage current of the gated PIN lateral polysilicon diodes. ” 2000 Elsevier Science Ltd. All rights reserved.

We have demonstrated the performance of circuits on stainless steel and compared them to those fabricated on quartz substrates. We have modeled the substrate dependence of the minimum and maximum operating frequency of a Shift Register, and found close agreement with our experimental measurements. This model can be used as a design guideline for future development of circuits on conducting substrates.

Silicides of cobalt and nickel are formed on thin (18–100 nm) polycrystalline silicon films by in situ vacuum annealing. The dependence of silicide sheet resistance on silicon film thickness and crystallinity, surface preparation, integrity of vacuum during metal deposition, and anneal temperature is shown. Cobalt and nickel silicides with sheet resistances as low as 30 and 20 Ω/□ were formed on 18-nm-thick polysilicon films. A surface preparation method to produce a passivated silicon surface compatible with large area glass substrates is demonstrated. The resistance of nickel and cobalt silicide to chemical reagents used in semiconductor processing is studied, as is the thermal stability of these films.

Reaction mechanisms within aluminum‐indium tin oxide (Al‐ITO) metallization schemes were investigated in this work using X‐ray photoelectron spectroscopy and X‐ray diffraction. Examination of Al‐ITO, aluminum‐nickel‐indium tin oxide (Al‐Ni‐ITO), and aluminum‐cobalt‐indium tin oxide (Al‐Co‐ITO) interfaces reveals that considerable atomic rearrangement at the ITO interface with Al or with barrier layer transition (CO or Ni) metals occurs due to reaction. Metal‐oxygen bonds in crystalline ITO are broken and the interface is rearranged. In Al‐Co‐ITO stacks, reduced intermetallic species were detected at the Co‐ITO interface. In Al‐Ni‐‐ITO stacks, such species were not detected at the Ni‐ITO interface, although formed at the Al‐Ni interface. These reactions within metallization stacks are important because they determine the electrical quality of ITO contacts with Al alloy data lines in polysilicon thin film transistor displays. © 1999 The Electrochemical Society. All rights reserved.

The effect of using bilayer Ni/Al-1%Cu or Co/Al-1%Cu metallization stacks with regard to hillock formation is investigated in this study and compared to hillock suppression capabilities of Al-1%Si and Al-1%Cu single layer films and Ti/Al-1%Cu bilayer metallization stacks. Various heat treatments during and immediately after depositions were used to study the resistances of different metallization stack specimens to hillock formation. The densities and sizes of hillocks were characterized using scanning electron microscopy and atomic force microscopy, while interfacial reactions between the transition metal layer and Al-1%Cu in the metallization stack were examined using glancing angle x-ray diffraction. Resistivities of the bilayer metallization stacks were characterized using conventional four-point probe measurements. Our studies indicate that metallization processes involving bilayer metallization stacks of nickel and cobalt with Al-1%Cu are more robust compared to those involving titanium with Al-1%Cu. The mechanism of hillock formation is analyzed in light of intermetallic compound formation and stress-strain considerations.

Interfacial reactions between ultra-thin Ni/Co bilayer films and single crystal Si (100) substrate were studied at 600°C using X-ray photoelectron spectroscopy (XPS). In very thin bilayer films (

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm2/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.

Polysilicon TFTs were fabricated in as-deposited polycrystalline silicon films as well as in crystallized films that were deposited in a mixed phase. The elimination or drastic reduction of the crystallization anneal resulted in greatly reduced thermal budgets for TFT fabrication. This makes polycrystalline silicon TFTs much more attractive for AMLCD applications. Devices in as-deposited polysilicon show lower mobilities than TFTs in polysilicon crystallized from the amorphous phase, but still much higher than those of amorphous silicon TFTs. Devices in polysilicon crystallized from films containing a mixed phase layer exhibit mobilities close to those for TFTs in polysilicon crystallized from the amorphous phase at a fraction of the required crystallization time. TFTs in as-deposited polycrystalline silicon exhibit much higher punchthrough voltages compared to devices in crystallized films.

A novel feedback current programming principle, compatible with 2T1C pixel structure AMOLED displays is described and a new driver circuit is proposed which can compensate for both the threshold voltage and mobility non- uniformities of the pixel drive TFT. Circuit simulations demonstrated that a pixel drive current of less than 100nA can be programmed with less than 10% of error even if the mobility varies by an order of magnitude.