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The authors present a comprehensive characterization method applied to the study of the state-of-the-art 18-[micro]m CMOS process. Statistical characterization of gate CD reveals a large spatial intrafield component, strongly dependent on the local layout patterns. The authors describe the statistical analysis of this data and demonstrate the need for such comprehensive characterization. They describe the experimental setup of the novel measurement-based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate circuit modeling and statistical design for increased performance and yield. Characterization is based upon an inexpensive electrically based measurement technique. A rigorous statistical analysis of the impact of intrafield variability on circuit performance is undertaken. They show that intrafield CD variation has a significant detrimental effect on the overall circuit performance that may be as high as 25%. Moreover, they demonstrate that the spatial component of gate CD variability, rather than the proximity-dependent component, is predominantly responsible for speed degradation. In order to reduce the degradation of circuit performance and yield, the authors propose a mask-level spatial gate CD correction algorithm to reduce the intrafield and overall variability and provide an analytical model to evaluate the effectiveness of correction for variance reduction. They believe that potentially significant benefits can be achieved through implementation of this compensation technique in the production environment. Index Terms--Characterization, correction, modeling, process variation, statistical design.

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material, and the underlying IC topography. An efficient defect macromodeling methodology based on the rigorous two-dimensional (2-D) topography simulator METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters (material, size, and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with the data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy for our method of developing contamination to defect propagation/growth macromodels. Index Terms - Defect particle, semiconductor fabrication, topography modeling.

Circuit designers need to be able to predict variations in circuit performance as a function of variations in process parameters. Often the relation between process parameters and circuit performances is highly nonlinear, and the process is described by a large number of independent variables. Traditional approaches to modeling, like polynomial regression, are not very accurate for such problems. In order to build accurate nonlinear models for high-dimensional problems, an algorithm has been implemented based on additive regression splines. The model building process is fully automated. The algorithm is used to build a model to predict the offset voltage of a parallel filter bank. This example demonstrates that very accurate nonlinear models can be constructed very efficiently.