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The indium phosphide (InP) 130 nm double-heterojunction bipolar transistor (DHBT) offers milliwatts of output power and high signal amplification in the lower end of the terahertz frequency band when the transistor is used in a common-base configuration. Instrumentation can directly benefit from this technology by enabling the development of novel broadband sources or synthesizers that rely on our ability to amplify the signal over enormous bandwidths. However, the design of high gain and stable amplifiers presents many obstacles and limitations as we increase the bandwidth and the carrier frequency. Here we show that adding a series resistor at the collector terminal of the common-base transistor prevents instabilities in the terahertz monolithic integrated circuit (TMIC) amplifier and increases its fractional bandwidth. Adopting this technique, we report a state-of-the-art broadband common-base amplifier that exhibits a minimum small-signal gain of 18.9 dB from 325 GHz to 477 GHz. This amplifier presents the highest fractional bandwidth and gain above 300 GHz. Our work demonstrates the feasibility of high-performance amplifiers that address the need of future terahertz electronic systems.

We report a three-gain-stage 88–104-GHz $W$ -band solid-state power amplifier (SSPA) monolithic microwave integrated circuit (MMIC) having modest 100–140-mW output power ( $P_{\mathrm {out}}$ ), high gain, and high power-added efficiency (PAE). The MMIC technology is 250-nm InP HBT. PA $S_{21}$ gain is 29.5 dB with ±0.5-dB variation. PA 3-dB $S_{21}$ gain roll-off is between 88 and 104.5 GHz with high $\vert S_{11}\vert $ and $\vert S_{22}\vert $ return losses. DC power ( $P_{\mathrm {dc}}$ ) is 0.41 W. Across 88 –104 GHz, the PA-saturated output power $P_{\mathrm {sat}}$ is 100–120 mW with greater than 20-dB power gain and 20% PAE. At 92 GHz, peak 120-mW $P_{\mathrm {out}}$ with 20-dB gain and 24.7% PAE is demonstrated. $P_{\mathrm {out}}$ at 1-dB gain compression OP $_{\mathrm {1-dB}}$ is estimated to be 15–17 dBm. At 94 GHz and an elevated output stage bias (0.50-W $P_{\mathrm {dc}}$ ), 140-mW $P_{\mathrm {out}}$ with 20-dB gain and 24.4% PAE is demonstrated. This work contributes to and improves the state of the art for $W$ -band PAs in the simultaneous performance areas of power, gain, and PAE.

We report a compact H-band power amplifier with high output power in 250nm InP HBT technology. Stacking and parallel power combining together provide the desired output power. Common-base stages with base capacitive degeneration act as stacked power cells. Four power cells are combined by a compact low-loss 4:1 transmission line network. At 270GHz, the four-stage amplifier has 16.8dBm saturated output power with 4% power-added efficiency (PAE). Over 266-285GHz, the amplifier's saturated output power is 14-16.7dBm with an associated 2.2-4%PAE. The 3-dB small-signal bandwidth extends from 233GHz to 281GHz with a peak gain of 20.5dB at 264GHz. The amplifier has a compact area of $\mathrm{1.08} \text{mm}\times \mathrm{0.77}\text{mm}$ and $P_{\text{sat}}$ /mm2 of 57.6mW/mm2. To the authors' knowledge, these results demonstrate a record output power and $P_{\text{sat}}/\text{mm}^{2}$ for H-band amplifiers working around 270GHz.

We report a high-efficiency G-band power amplifier in 250nm InP HBT technology. The amplifier has four capacitively linearized common base stages. Four power cells are combined by a low loss 4:1 corporate combiner. The drivers are scaled to sustain high power-added efficiency (PAE). At 202GHz operation, the amplifier has 18.3dBm saturated output power with 7.9% PAE. Over 190-210GHz, the amplifier's output power at 1dB gain compression (OP 1dB ) is 16-17.4dBm with an associated 4.7-6.4%PAE and 17.9-23.1dB gain. The peak small signal gain is 23.5dB at 204GHz with more than 20.5GHz 3dB bandwidth. The amplifier has a low DC power consumption of 814mW and a compact area of 1.2mm×0.95mm. To the authors' knowledge, this result demonstrates a record PAE at OP 1dB .

We present a record collector efficiency (54%) and PAE (46%) at 47 GHz for a 250-nm InP HBT power amplifier (PA). Reactively tuned transistor cells using a multi-section hybrid distributed-lumped matching network realize high PAE. The reported PA delivers up to 120 mW at 47 GHz while operating from a 2.75 V power supply. The measured PAE is the highest reported at 47 GHz.

Two high-gain, high power-added-efficiency (PAE) G-band solid-state power amplifier (SSPA) MMICs operating between 160–183 GHz are reported. Both utilize an identical five-stage gain-lane, and on-chip combining of these gain-lanes satisfies the output power (Pout) objectives. The first result is a 0.24-W PA using 4-way power combining. S21 mid-band gain is 21.0 dB and DC power dissipation (P DC ) is 3.05-W. The 3-dB S21 bandwidth (BW) is between 158.5-182.8 GHz. At 170-GHz, peak Pout is 244-mW (7.5% PAE). Pout is no less than 0.20-W between 160–180 GHz and is 177-mW at 183-GHz. The 170-GHz OP 1dB 1-dB gain compression is 120-mW (3.8% PAE). This PA result improves upon the prior state-of-the-art by 2.2-2.8× for peak SSPA power. The second result is a 0.14-W PA using 2-way combining. S21 mid-band gain is 23.6 dB and P DC is 1.35-W. The 3-dB S21 BW is between 161.0-184.8 GHz. At 170-GHz, peak Pout is 140-mW (9.50% PAE), and Pout is 116–140 mW (8.0-9.5% PAE) between 160–183 GHz. The 170-GHz OP 1dB is 70-mW (5.1% PAE). This PA result improves upon the prior state-of-the-art by 1.4-1.6× for peak SSPA power. This work establishes new SSPA RF power, gain, and PAE performance benchmarks at 160–183 GHz operation using a 250-nm InP HBT technology.

In this letter, we report on GaN-based field-effect transistors with laterally gated two-dimensional electron gas (2DEG). The drain current of the transistor is controlled solely by modulating the width of the 2DEG between buried gates. The lateral Schottky gate contact to the GaN channel layer enhances electron confinement by raising electrostatic potential below the 2DEG, improving isolation between the source and drain. Complete elimination of a top-contact gate reduces the density of trapped electrons near the surface and alleviates capacitive coupling between the trapped electrons and the 2DEG. Owing to the unique device structure and operation principle, the 150-nm-gate transistors with a channel width of 250 nm demonstrated: extremely small output conductance, drain-induced barrier lowering, knee voltage, and knee current collapse, greatly reduced ${g}_{m}$ derivatives near threshold, and nearly constant RF gain along the resistive load line. Furthermore, a preliminary accelerated life test indicated enhanced device reliability due to an absence of the inverse piezoelectric effect. The proposed transistors hold great promise for realizing reliable and efficient power amplifiers with improved transistor linearity.

Performances of high-speed switches operating as terahertz on–off-keying (OOK) modulators are reported. Two types of switches, a passive shunt switch and an amplifier switch, are fabricated using 0.25- $\mu \text{m}$ InP double heterojuction bipolar transistor (DHBT) technology. Small-signal tests show that the amplifier switch possesses superior on–off ratio, but the passive switch has broader bandwidth and smaller group delay ripples. A modulator test setup is built with 20-dB path loss between the transmitter and the receiver. The results indicate that carrier power levels of 14 dBm for the shunt switch and 8 dBm for the amplifier switch are required for 20-Gb/s OOK modulation with bit error rate (BER) of 10−2 at 290 GHz.

We report here a compact 140-GHz, 150-mW high-gain solid-state power amplifier (SSPA) monolithic microwave integrated circuit (MMIC) demonstrated in a 250-nm InP HBT technology. It utilizes five-gain stages and two-way on-chip power combining. The amplifier measures 29.5-dB mid-band $S_{21}$ gain and over 125-mW output power across 115–150-GHz operation. The peak 153-mW output power was measured at 140 GHz using only 2.7-mW RF input power—the associated large-signal gain is 17.5 dB with 9.8% power added efficiency (PAE). The 140-GHz OP1 dB 1-dB gain compression power is 106 mW with 7.0% PAE. The dc power dissipation is 1.54 W and its size is only 0.75 mm2. The 3-dB $S_{21}$ gain roll-off is between 112 and 147 GHz. The 115–150-GHz output power variation at 0-dBm input drive is only ±0.5 dB. The peak PAE varies between 8.2% and 10.5%. This D-band result improves upon by $2.3\times $ at 140 GHz the state-of-the-art peak RF power previously demonstrated by SSPA MMICs.

Highly scaled indium phosphide (InP) heterojunction bipolar transistor (HBT) technologies have been demonstrated with maximum frequencies of oscillation ( $f_{\max}$ ) of >1 THz and circuit operation has been extended into the lower end of the terahertz (THz) frequency band. InP HBTs offer high radio-frequency (RF) output power density, millivolt (mV) threshold uniformity, and high levels of integration. Integration with multilevel thin-film wiring permits the realization of compact and complex THz monolithic integrated circuits (TMICs). Circuit results reported from InP HBT technologies include: 200-mW power amplifiers at 210 GHz, 670-GHz amplifiers and fundamental oscillators, and fully integrated 600-GHz transmitter circuits. We review the state of the art in THz-capable InP HBT devices and integrated circuit (IC) technologies. Challenges in extending transistor bandwidth and in circuit design at THz frequencies will also be addressed.

A power detector integrated with a preamplifier is fabricated using a 250-nm InP double-heterojunction bipolar transistor technology for 280-GHz operation. The input RF signal to the detector is modulated at 20 kHz to decouple the output dc voltage from 1/f noise. The integrated receiver detector consists of a two-way balun, a differential preamplifier, a power detector. Breakout circuits of a standalone power detector and a test amplifier have been independently characterized. The test amplifier shows a gain of 18.1 dB and noise figure of 14 dB. The responsivity and noise equivalent power of the detector improve from 4.5 to 350 kV/W and from 10 to 0.13 pW/Hz0.5, respectively, at 280 GHz, with the addition of the preamplifier. The performance enhancements due to the preamplifier are in close agreement with the results predicted by advanced design system simulations.

In this paper we review the status of the state-of-the-art and our transition activities for mm-wave, D-, and G-band solid-state power amplifier (PA) MMICs developed into Teledyne Scientific’s 250-nm InP HBT technology. Key design decisions driven by the transistor gain at a given frequency and large-signal load-line are reviewed. Novel PA cell topologies are presented to show how they address the high current biasing required of the 250-nm InP HBT and permit 2× and 4× on-chip combining. PA wafer-mapping by auto-probing on a full thickness 100-mm wafer prior to finishing (thinning to 3-mil, chip singulation) permits the RF identification of known-good-die (KGD) and thus an inventory of parts can be generated. Five established 250-nm InP HBT power amplifiers are presented operating from 55-135 GHz (115-135 mW), 60-130 GHz (160-275 mW), 115-145 GHz (0.25-W @ 140-GHz), 115-185 GHz (75-115 mW), and 180-250 GHz (40-80 mW). Also, included is a novel 190-GHz low-power driver amplifier (high-gain, 100-mW P DC , 3-dBm OP 1dB , 11-dBm P sat with 9.6% PAE).

We report Monte Carlo simulation results of 300nm InP heterojunction bipolar transistors driven to exhibit distortion. IM3 distortion is typically explained by collector velocity modulation. Full-band ensemble Monte Carlo simulations implicate intervalley transfer as an additional source of distortion under conditions of high current, low voltage, and high doping. Simulations reveal that intervalley transfer promotes the formation of traveling accumulation domains which result in high frequency distortion more significant than that caused by velocity modulation. Special care must be taken when designing high current HBT power amplifiers in order to mitigate this effect.

We report here a 250-nm InP HBT based wideband power amplifier that operates between 110-190 GHz and fully covers D-band (110-170 GHz). It utilizes 5-gain stages and 2-way on-chip power combining. The amplifier demonstrates 25.2-dB S21 mid-band gain and 68-117 mW output power between 110190 GHz. The fractional bandwidth associated with 1-dB and 3- dB S21 gain roll-off are 35% (54-GHz) and 43% (66.5-GHz), respectively. The fractional large-signal power bandwidth associated with highest power between 110-190 GHz is 53%. Under small, medium, and large-signal operation, the PA is most efficient between 115-185 GHz – at 3-dBm input power, 73-104 mW output power (5.0-7.5% PAE) is demonstrated over this frequency span. This result represents a significant increase to the state-of-the-art for a mm-wave solid-state power amplifier operating across D-band and a significant fraction of G-band in the simultaneously demonstrated metrics of high output power (by 3-4× higher), bandwidth, gain, and gain flatness.

We report on GaN-based field effect transistors with laterally-gated multiple 2DEG channels, called BRIDGE FETs (buried dual gate FETs). Unique operation principle of the transistors demonstrated unprecedented device characteristics suitable for efficient and linear millimeter-wave power amplifier applications. Multiple 2DEG channels formed in AlGaN/GaN and AlN/GaN material systems are compatible with the BRIDE FET structure, adding design flexibility for an increased drain current density with higher frequency performance. The BRIDGE FET fabricated on a 4-channel epi structure with a net 2DEG density of 1.2×1013 cm-2 exhibited 1.7× higher saturation current density than those on a single-channel with the same 2DEG density. This is attributed to a higher saturation velocity of 2DEG with a lower density per channel. Finally, hexagonal micro-scale device cells consisting of segmented BRIDGE FETs construct a power amplifier (PA) unit cell, where distributing heat sources uniformly over an entire PA cell area maximizes its area power density while minimizing a rise of the peak junction temperature.

Velocity overshoot in heterojunction bipolar transistors has long been recognized to significantly reduce collector signal delay below that predicted under the assumption of a constant saturated electron velocity [1], [2]. This phenomenon has proven critical for high frequency operation of InP DHBTs which has resulted in cutoff frequencies above 1 THz [3]. In order to better understand the operation of these devices, we further explore the microscopic electron dynamics through simulation. We report modulated collector signal delay results from static and dynamic full band ensemble Monte Carlo simulation of a 300nm InGaAs/InP DHBT with a 300 nm collector.

Two high-gain, broadband power amplifier MMICs are reported. The first result is a 140-GHz 0.25-W PA. It utilizes 5-gain stages and 4-way power combining. S 21 gain is 29.4-dB. It demonstrates over 0.21-W P out across 110-150 GHz. 0.25-W P out at 140-GHz requires 4-dBm P in – the associated gain is 16-dB with 7.0% PAE. The 140-GHz OP 1dB 1-dB gain compression is 171-mW with 4.9% PAE. The 3-dB S 21 bandwidth (BW) is between 112-148 GHz. This result improves state-of-the-art by 65% at 140-GHz for peak SSPA power. The second PA result is a 55-135 GHz 115-135 mW PA. It utilizes 4-gain stages and 2-way power combining. Its operation fully covers WR15 (50-75 GHz) to WR08 (90-140 GHz) bands. S 21 gain is 27.3-dB. The S 21 fractional BW at 1-dB and 3-dB gain roll-off are 63% and 81%. Large-signal BW associated with high power and gain between 55-135 GHz is 84%. P out variation over this span at 3-dBm P in is only 11.2% (±13-mW). This result improves state-of-the-art for mm-wave PA’s where simultaneously high P out , fractional BW, gain, and gain flatness are required.

We report a high output power transmitter and a low DC power receiver front-end channels of a phased array transceiver, designed in heterogeneously integrated 250 nm InP HBT and 130 nm Si CMOS technologies. The transmitter channel consists of a variable gain amplifier, an IQ-vector-modulator-based phase shifter, and a power amplifier. External Analog control signals are used to adjust the phase shifter and VGA states. The transmitter has a saturated output power of 16dBm at 90GHz while consuming 885mW DC power. The receiver channel uses a low noise amplifier with a similar phase shifter, and a variable gain amplifier. 4-bit DACs are implemented in the CMOS to control the phase shifter and VGA. The overall the receiver channel has ~26dB small signal gain at 58.6 mW DC power dissipation. The areas of the transmitter and receiver channels are 2.7x0.81mm2 and 2.1x0.76mm2 respectively.

We verified a model for state-of-the-art 250-nm heterojunction bipolar transistors with large-signal measurements. We demonstrated the propagation of correlated measurement uncertainties through the model extraction and verification processes and used them to quantify the differences observed in the measurements and models and the accuracy of the model parameters we extracted.

Due to its remarkably high Johnson figure of merit, gallium nitride (GaN) has become the material of choice for applications requiring high output power at high frequencies. In this paper, we have reviewed high-speed switching work to date and we demonstrate a 28 V, 865-MHz switching speed step-down converter that can be applied to envelope tracking (ET). We report a GaN monolithic microwave integrated circuit technology utilized to fabricate a gate driver IC at a switching speed >1 GHz with 100 V breakdown GaN power switch. The on-chip integration of the power switch and gate driver allows in-circuit characterization of the power switch switching speed. Using the integrated gate driver and switch, we report a slew rate of the power switch of 152 V/ns at 50 V, which enables a down converter IC capable of ET with over 50-MHz tracking bandwidth. This paper shows the first demonstration of a GaN low-side gate driver capable of >1-GHz switching, monolithic integration with a 0.15- $\mu \text{m}$ T-gate suitable for up to Ka-band operation, and a >100 V breakdown voltage power switch on the same chip.

We examine potential 100–340 GHz wireless applications in communications and imaging, and examine the prospects of developing the mm-wave transistors needed to support these applications.

Compound semiconductor heterogeneous integration with silicon electronics offers new design opportunities for high performance microsystems. The indium phosphide (InP) material system is an attractive candidate for heterogeneous integration of both electronic and optoelectronic devices. For RF and mixed-signal integrated circuit (IC) applications, InP transistors offer the highest reported RF figures-of-merit, low transistor noise figure and high RF power density. We report on InP heterogeneous integration techniques performed at the wafer-scale using hybrid bonding and at the individual transistor level using micro-transfer printing. Both integration techniques maintain the native substrate transistor performance and have been used to demonstrate high performance millimeter-wave ICs (RF beamformers and power amplifiers).

We present two frequency doublers in 130 nm InP HBT technology. The doublers use digital logic and DC negative feedback to suppress unwanted harmonics. The single-ended output of the lower frequency doubler has -5 dBm output power over 32 GHz to 53 GHz output frequency range. First and third harmonic rejection is higher than 30 dBc. The delay control circuit with the feedback loop enables fourth harmonic rejection higher than 18 dBc. It consumes 0.94 W. The higher frequency doubler has -5 – -8 dBm single-ended output power over 50 to 106 GHz output frequency range with better than 25 dBc first harmonic rejection. It consumes 1.069 W.

InP double-heterojunction bipolar transistors (DHBTs) have demonstrated power gain cutoff frequencies $(f_{max})$ above 1THz under low collector voltage due to electron velocity overshoot in the InP drift collector [1] [2]. Under higher collector voltage, however, a quick onset of $\Gamma-\mathrm{L}$ scattering limits the average electron velocity to the saturation velocity (Fig. 1(a)-(c)), leading to a Johnson's figure-of-merit (JFOM) second to GaN HEMTs and a limited transistor power bandwidth for InP DHBTs [3]. Here we propose a velocity-engineered device structure called the segmented-collector DHBT (SC-DHBT) that incorporates p-type scattering layers within the drift collector to reduce the electron kinetic energy and force a greater electron distribution into the low effective mass $\Gamma-$ valley for extended velocity overshoot (Fig. 3(a)). Transport simulations show the collector transit time $\tau_{c}$ is reduced from 1.23ps in the reference design to 0.90ps in a double scatterer design at $V_{cb}=5\mathrm{V}, J_{c}{=}$ 1mA/um2. The proposed SC-DHBT design is suited for large power bandwidth power amplifiers.

Recent improvements in the fabrication technology of InGaAs/InP heterobipolar transistors have enabled highly scaled transistors with power gain bandwidths above 1 THz. Limitations of the conventional fabrication process that reduce RF bandwidth have been identified and mitigated, among which are high resistivity base ohmic contacts, resistive base electrodes, excessive emitter end undercut, and insufficient undercut of large-diameter base posts. A novel two-step deposition process for self-aligned metallization of sub-20-nm bases has been developed and demonstrated. In the first step, a metal stack is directly evaporated onto the base semiconductor without any lithographic processing so as to minimize contamination from resist/developer chemistry. The composite metal stack exploits an ultrathin layer of platinum that controllably reacts with base, yielding low contact resistance, as well as a thick refractory diffusion barrier, which permits stable operation at high current densities and elevated temperatures. Further reduction of overall base access resistance is achieved by passivating base and emitter semiconductor surfaces in a combined atomic layer deposition Al2O3 and plasma-enchanced chemical vapor depositon SiNx sidewall process. This technology enables the deposition of low-sheet-resistivity base electrodes, further improving overall base access resistance and $f_{\textrm {max}}$ bandwidth. Additional process enhancements include the significant reduction of device parasitics by scaling base posts and controlling emitter end and base postundercut.

In this paper, H-band (220–325 GHz) power amplifier (PA) integrated circuits (ICs) are presented using 250-nm InP HBT technology, where a cascode topology was adopted to achieve high gain and high output power. Three PAs were designed: PA1 was implemented with two-stage cascode HBTs, PA2 combined two PA1s, and PA3 combined four PA1s, by using Wilkinson couplers without isolation resistors. Electromagnetic simulations were carried out for the accurate design of passive circuits such as a microstrip line, a capacitor, and RF pads. The measured insertion loss of the RF pad and Wilkinson coupler was as low as 0.24 dB and 0.70 dB, respectively, at 300 GHz. The three PAs exhibited a measured gain higher than 15 dB with good return losses at 300 GHz. The output powers scaled well with total emitter area of the PAs. PA3 exhibited a maximum output power of 13.5 dBm at 301 GHz. To the best of the authors' knowledge, this corresponds to the highest output power among the previously reported solid-state PAs in this frequency range.

This paper presents a wideband vector-sum phase shifter (VSPS) that operates over the entire WR-3 band (220–320 GHz). Compared to conventional VSPSs with double Gilbert cells, the proposed phase shifter employs a single Gilbert-cell structure for vector modulation. This reduces the output current combining ratio from 8:2 to 4:2, and boosts the impedance at the combining node, thus facilitating wideband output matching at upper millimeter-wave and terahertz bands. The simplified structure leads to a reduction in dc power consumption and chip area without sacrificing the 360 $^{\circ}$ phase-shifting property. Lossy matching is applied at the Gilbert-cell output to further increase bandwidth and stability at the expense of relatively high loss. The phase shifter is implemented using a 250-nm InP DHBT technology that provides $f _{ T}$ and $f _{\max}$ exceeding 370 and 650 GHz, respectively. The measurements exhibit a wideband phase shift with continuous 360 $^{\circ}$ coverage and average insertion loss ranging from 11.8 to 15.6 dB for the entire WR-3 band. The root mean square amplitude and phase error among different phase states are less than 1.2 dB and 10.2 $^{\circ}$ , respectively. The input-referred 1-dB compression is measured at ${\hbox{0.7 dBm}}$ on average. The dc power consumption is 21.8–42.0 mW at different phase states.

We report an InP/InGaAs/InP double heterojunction bipolar transistor fabricated in a triple-mesa structure, exhibiting simultaneous 404 GHz fτ and 901 GHz fmax. The emitter and base contacts were defined by electron beam lithography with better than 10 nm resolution and smaller than 20 nm alignment error. The base-collector junction has been passivated by depositing a SiNx layer prior to benzocyclobutene planarization, improving the open-base breakdown voltage BVCEO from 3.7 to 4.3 V.

Highly-scaled Indium Phosphide (InP) transistor technologies have bandwidths extending into the terahertz (THz) frequency regime (0.3–3 THz). The high transistor bandwidth can be exploited to both extend circuit operation to THz frequencies and improve system performance at millimeter wave and sub-millimeter wave frequencies. InP heterojunction bipolar transistor (HBT) technologies offer wide bandwidths, high RF power handling and the capability to realize high levels of integration. We review integrated circuit (IC) results from Teledyne's InP HBT technologies that span frequencies from 60 GHz to >600 GHz focusing on performance benefits and applications.

X-band power performance of N-polar GaN HEMTs is reported, including 2-tone results at 10GHz that demonstrate an OIP3/P DC linearity figure of merit of 12dB at a drain voltage of 20V, utilizing tuning of fundamental, second and third harmonic terminations. Compared to available linearity results of GaN HEMTs at 10GHz, the device technology presented here demonstrates the best such ratio reported at 10GHz for any GaN HEMT to date. The N-polar HEMT device exhibits very low 3rd order intermodulation distortion as well as single-tone high power-added efficiency (PAE) of ∼65% with an associated power density of 3W/mm that scales favorably with a drain voltage of 15V. These results show the suitability of N-polar GaN HEMTs for high performance X-band transceiver systems.

In this paper, state-of-the-art terahertz (THz) integrated circuits in InP HBT technologies operating in the 500–600 GHz band are reviewed: the highest-frequency fundamental transistor oscillator, THz power amplifier in HBT with the highest saturated output power, the highest-frequency dynamic frequency divider, and the highest-frequency transmit/receive front-end integrated circuits, to the best of authors' knowledge.