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3. Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform

Author

Masselos, K., Blionas, S., Mignolet, J-Y., Foster, A., Soudris, D., Nikolaidis, S., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Macii, Enrico, editor, Paliouras, Vassilis, editor, and Koufopavlou, Odysseas, editor

Published
2004
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4. Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation

Author

Bartic, T. A., Desmet, D., Mignolet, J-Y., Marescaux, T., Verkest, D., Vernalde, S., Lauwereins, R., Miller, J., Robert, F., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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21. ADRES & DRESC: Architecture and Compiler for Coarse-Grain Reconfigurable Processors.

Author

Vassiliadis, Stamatis, Soudris, Dimitrios, Mei, B., Berekovic, M., and Mignolet, J-Y.

Abstract

Nowadays, a typical embedded system requires high performance to perform tasks such as video encoding/decoding at run-time. It should consume little energy to work hours or even days using a lightweight battery. It should be flexible enough to integrate multiple applications and standards in one single device. Coarse-grained reconfigurable architectures (CGRAs) are emerging as potential candidates to meet the above challenges. Many of them were proposed in recent years. However, existing CGRAs have yet been widely adopted mainly because of programming difficulty for such complex architecture In this chapter, a novel CGRA, ADRES (architecture for dynamically reconfigurable embedded systems), and a compiler framework, DRESC (dynamically reconfigurable embedded system compiler), are presented to address issues of existing CGRAs. Our approach possesses several unique features. First, the ADRES architecture tightly couples a very-long instruction word (VLIW) processor and a coarse-grained array by providing two functional views on the same physical resources. It brings advantages such as high performance, low communication overhead and easiness of programming. Second, the DRESC framework introduces software-like design experience. An application written in C can be quickly mapped onto an ADRES instance. The key technology behind the DRESC framework is a novel modulo scheduling algorithm, which can pipeline a loop onto the partially interconnected array to achieve high parallelism. Finally, ADRES is a template instead of a concrete architecture. With the retargetable compilation support from DRESC, architectural exploration becomes possible to discover better architectures or design domain-specific architectures A number of multimedia and telecommunication kernels are mapped. The instruction-per-cycle (IPC) up to 42.7 has been observed on an 8 × 8 ADRES instance. A multimedia application, MPEG-2 decoder, is mapped within one week starting from a software implementation. The speed-up over an 8-issue VLIW are about 12 times for kernels and 5 times for the entire application. [ABSTRACT FROM AUTHOR]

Published
2007
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27. Topology adaptive network-on-chip design and implementation.

Author

Bartic, T.A., Mignolet, J.-Y., Nollet, V., Marescaux, T., Verkest, D., Vernalde, S., and Lauwereins, R.

Subjects
*TOPOLOGY, *GEOMETRY, *DC-to-DC converters, *ELECTRIC current converters, *TRANSISTORS, *ELECTRONICS, *ENGINEERING
Abstract

Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. The authors believe that different types of networks will be required, depending on the application domain. Therefore, a very flexible network design is proposed that is highly scalable, and can be easily changed to accomodate various needs. A network-on-chip design, realised as part of the platform that the authors are developing for reconfigurable systems, is presented. This design is suitable for building networks with irregular topologies, and with low latency and high throughput. [ABSTRACT FROM AUTHOR]

Published
2005
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