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En aquest document, aprofundirem sobre com gestionen els serveis cada sistema operatiu i les diferències tècniques entre un MicroKernel i un Kernel monolític per tal de conèixer avantatges d’ús de cadascun. També intentarem observar com canvia el manteniment evolutiu entre tipus de nucli. Posteriorment, agafarem com a exemple un S.O amb nucli MicroKernel per destacar- ne algunes particularitats i veure en quines plataformes de desenvolupament funciona. L’objectiu d’això és compilar i assemblar-lo en una per veure les seves diferències amb Linux en el que respecta execució i accés a recursos hardware., In this document, we will go into more depth on how services are managed by each operating system and the technical differences between a MicroKernel and a monolithic Kernel in order to know each one’s usage advantages, we’ll also try to see how evolutionary maintenance changes between Kernel types. Afterwards, we’ll take as an example an O.P with MicroKernel nucleus to highlight some particularities and see on which development platforms it works. The aim of this is compiling and resembling it in one in order to see its differences with Linux in which it respects execution and access to hardware resources.

Aquest treball presenta la implentació d’un controlador en temps real utilitzant un microcontrolador programat en MATLAB Simulink per a gobernar un sistema bola-tub. El sistema controla la posició vertical de la bola de ping-pong dins d’un tub de metacrilat. La bola es manté en levitació pel corrent d’aire produït per un ventilador localitzat a la base del tub., Este trabajo presenta la implementación de un controlador en tiempo real utilizando un microcontrolador programado en MATLAB Simulink para gobernar un sistema bola-tubo. El sistema controla la posición vertical de una bola de ping-pong dentro de un tubo de metacrilato. La pelota se mantiene en levitación por la corriente de aire producida por un ventilador ubicado en la base del tubo., This work presents the implementation of a real-time controller using a microcontroller programmed in MATLAB Simulink to govern a ball-tube system. The system controls the vertical position of a ping-pong ball inside a methacrylate tube. The ball is kept in levitation by the air current produced by a fan placed at the base of the tube.

El present document recull el treball desenvolupat durant mesos per tal d'aconseguir implementar un sistema de control utilitzant la família de Microprocessadors C2000 aplicat a una planta de control del tipus biga-bola i tots els passos que s'han fet per aconseguir-ho. Per assolir tal objectiu s'ha hagut de fer una anàlisi prèvia de la planta on es treballarà i les seves propietats físiques per trobar un equivalent matemàtic del sistema. Un cop s'ha obtingut la primera simplificació s'ha comprovat paral·lelament si la simplificació del model es correspon amb la realitat i viceversa. Per adaptar la maqueta de la planta al microcontrolador s'ha hagut de dissenyar una petita interfície per condicionar el senyal rebut procedent del sensor i de pas simplificar el cablejat soldant una placa. Per altra banda, s'ha realitzat l'estudi d'un tipus de control PID aprofitant la resolució més gran que presenta el microcontrolador respecte als emprats a les pràctiques d'Implementació de sistemes de Control automàtic (ISCA). Per tal d'implementar el control PID ha calgut familiaritzar-se amb els nous blocs funcionals proporcionats per les llibreries de Texas Instruments, blocs que tenen molta més complexitat i possibilitats que els ja treballats a classe. Finalment, també ha calgut crear llibreries a partir de subsistemes de blocs de funcionament tant del servo com de condicionament de senyal, ja que aquestes no existeixen., El presente documento recoge el trabajo desarrollado durante meses a fin de conseguir implementar un sistema de control utilizando la familia de microprocesadores C2000 aplicado a una planta de control de tipo viga-bola y todo el camino recorrido para llegar a ello. Para llegar a tal meta se ha tenido que hacer un análisis previo de la planta donde se desarrollará el trabajo y sus propiedades físicas a fin de encontrar un equivalente matemático del sistema. Una vez se ha obtenido la primera simplificación se ha ido comprobando paralelamente si dicha simplificación del modelo tenía correlación con la realidad y viceversa. Para adaptar la maqueta de la planta al microcontrolador se ha diseñado una pequeña interfaz para acondicionar la señal recibida procedente del sensor y de paso simplificar el cableado soldando una placa. Por otro lado, se ha realizado el estudio de un tipo de control, el control PID, aprovechando la mayor resolución que presenta el microcontrolador respecto a los empleados en las prácticas de Implementación de sistemas de control automático (ISCA). Para implementar el control PID ha hecho falta familiarizarse con los nuevos bloques funcionales proporcionados por las librerías de Texas Instruments, estos bloques presentan más complejidad y posibilidades que los que se usaban en clase. Finalmente, también ha hecho falta crear librerías a partir de subsistemas de bloques de funcionamiento tanto del servo como del acondicionamiento de señal, puesto que estos no existían., This document summarizes the work developed over months in order to implement a control system using the C2000 family MCU’s applied to a beam and ball system and all the steps that have been taken along the way in order to make it possible. To achieve this goal, a prior analysis of the plant was done and a first mathematical model of the System was obtained. Once the first simplification has been done, it has been checked whether the simplification of the model corresponds to reality and vice versa. To adapt the model of the plant to the microcontroller, a small interface had to be designed to condition the signal received from the sensor and to simplify the wiring. On the other hand, the study of a type of PID control has been carried out, taking advantage of the greater resolution presented by the microcontroller compared to those used in ISCA labs. In order to implement the PID control, it was necessary to become familiar with the new functional blocks provided by the Texas Instruments libraries, blocks that have much more complexity and possibilities than those in the default libraries. Finally, it was also necessary to create libraries from subsystems of both the servo and signal conditioning operating blocks, since these do not exist.

The increase in working set sizes of contemporary applications outpaces the growth in cache sizes, resulting in frequent main memory accesses that deteriorate system per- formance due to the disparity between processor and memory speeds. Prefetching data blocks into the cache hierarchy ahead of demand accesses has proven successful at attenuating this bottleneck. However, spatial cache prefetchers operating in the physical address space leave significant performance on the table by limiting their pattern detection within 4KB physical page boundaries when modern systems use page sizes larger than 4KB to mitigate the address translation overheads. This paper exploits the high usage of large pages in modern systems to increase the effectiveness of spatial cache prefetch- ing. We design and propose the Page-size Propagation Module (PPM), a µarchitectural scheme that propagates the page size information to the lower-level cache prefetchers, enabling safe prefetching beyond 4KB physical page boundaries when the accessed blocks reside in large pages, at the cost of augmenting the first-level caches’ Miss Status Holding Register (MSHR) entries with one additional bit. PPM is compatible with any cache prefetcher without implying design modifications. We capitalize on PPM’s benefits by designing a module that consists of two page size aware prefetchers that inherently use different page sizes to drive prefetching. The composite module uses adaptive logic to dynamically enable the most appropriate page size aware prefetcher. Finally, we show that the proposed designs are transparent to which cache prefetcher is used. We apply the proposed page size exploitation techniques to four state-of-the-art spatial cache prefetchers. Our evalua- tion shows that our proposals improve single-core geomean performance by up to 8.1% (2.1% at minimum) over the original implementation of the considered prefetchers, across 80 memory-intensive workloads. In multi-core contexts, we report geomean, This work is supported by the Spanish Ministry of Science and Technology through the PID2019-107255GB project, the Generalitat de Catalunya (contract 2017-SGR-1414), the European Union Horizon 2020 research and innovation program under grant agreement No 955606 (DEEP-SEA EU project), the National Science Foundation through grants CNS-1938064 and CCF-1912617, and the Semiconductor Research Corporation project GRC 2936.001. Georgios Vavouliotis has been supported by the Spanish Ministry of Economy, Industry, and Competitiveness and the European Social Fund under the FPI fellowship No. PRE2018-087046. Marc Casas has been partially supported by the Grant RYC2017-23269 funded by MCIN/AEI/10.13039/501100011033 and ESF ‘Investing in your future’., Peer Reviewed, Postprint (author's final draft)

Aquest projecte s'emmarca en un vehicle de competició de Formula Student, Permanent magnet synchronous motors (IPMSM) are increasingly used in electric vehicles due to their power density and efficiency specifications. This type of engine involves applying a complex control, which can be implemented in programmable logic with an FPGA. In this project, a field oriented control (FOC) for IPMSM motors is implemented in FPGA and adapted for use in a Formula Student racing vehicle. The control incorporates an MTPA (Maximum Torque per Ampere) control strategy with field weakening (Field Weakening) and uses Space Vector Modulation as a PWM generating technique. Programming and validation of the control algorithm is performed directly on the Matlab/Simulink environment using Vitis Model Composer add-on. This report also addresses the choice of the FPGA board and the design of the software architecture for starting and stopping the engine and provide an extra layer of safety., Los motores síncronos de imanes permanentes (IPMSM) se emplean cada vez más en los vehículos eléctricos debido a su densidad de potencia y eficiencia. El uso de este tipo de motor lleva aparejado la implementación de un control complejo, que puede implementarse en lógica programable con una FPGA. En este proyecto se adapta y se implementa un control de campo orientado por motores IPMSM en FPGA para su uso en un vehículo de competición de Formula Student. El control incorpora una estrategia de control MTPA (Maximum Torque per Ampere) con debilitamiento de campo (Field Weakening) y emplea Space Vector Modulation como técnica generadora de PWM. La programación y validación por simulación del algoritmo de control se realiza con directamente sobre el entorno Matlab/Simulink, por medio de la extensión Vitis Model Composer. En esta memoria también se aborda la elección de la placa FPGA y el diseño de la arquitectura de software de una capa de arranque, parada y seguridad., Els motors síncrons d'imants permanents (IPMSM) s'empren cada vegada més en els vehicles elèctrics degut a seva densitat de potència i eficiència. L'ús d'aquest tipus de motor comporta aplicar un control complexe, el qual pot implementar-se en lògica programable amb una FPGA. En aquest projecte s'adapta i s'implementa un control de camp orientat per motors IPMSM en FPGA pel seu ús en un vehicle de competició de Formula Student. El control incorpora una estratègia de control MTPA (Maximum Torque per Ampere) amb debilitament de camp (Field Weakening) i empra l'Space Vector Modulation com tècnica generadora de PWM. La programació i la validació per simulació de l'algorisme de control es realitza amb directament sobre l'entorn Matlab/Simulink fent ús de l'extensió Vitis Model Composer. En aquesta memòria també s'aborda l'elecció de la placa FPGA i el disseny de l'arquitectura de programari d'una capa d'arrencada, parada i seguretat.

Apart from personal interest, this project arises with the idea of providing a new learning tool for the subject of Configurable Digital Systems. Specifically, this tool is an 8-bit microprocessor described in VHDL for the DE2-115 evaluation board. The microprocessor has the functionality of being able to run step-by-step, stopping at each clock cycle to be able to view the internal changes. In addition, it can be easily modified and is scalable. Moreover, a controller has been designed to allow the user to visualize various internal data on the LCD of the board, and a system based on R2-232 serial communication allows the user to rewrite the RAM without having to compile and synthesize the project again. A Python script has also been implemented to make it easier to write the programs that the user wants to load into RAM., Además de interés personal, este proyecto surge con la idea de proporcionar una nueva herramienta de aprendizaje en la asignatura de Sistemas Digitales Configurables. Concretamente, esta herramienta es un microprocesador de 8-bits descrita en VHDL para la placa de evaluación DE2-115. El microprocesador tiene la funcionalidad de poder ejecutarse paso a paso, parando en cada ciclo de reloj para poder visualizar los cambios internos. Además, puede modificarse fácilmente y es escalable. Asimismo, también se ha realizado un controlador para poder visualizar varios datos del microprocesador en la LCD de la placa, y un sistema basado en la comunicación serie R2-232 que permite reescribir la memoria RAM sin tener que compilar y sintetizar el proyecto de nuevo. También se ha implementado un código en Python para poder escribir más cómodamente los programas que el usuario desea cargar en la RAM., A part d'interès personal, aquest projecte sorgeix amb la idea de proporcionar una nova eina d'aprenentatge per a l’assignatura de Sistemes Digitals Configurables. Concretament, aquesta eina és un microprocessador de 8-bits descrita en VHDL per a la placa d'avaluació DE2-115. El microprocessador té la funcionalitat de poder-se executar pas per pas, parant a cada cicle de rellotge per a poder visualitzar els canvis interns. A més a més, es pot modificar fàcilment i és escalable. Així mateix, també s'ha dut a terme un controlador per a poder visualitzar diverses dades del microprocessador en la LCD de la placa, i un sistema bastat en la comunicació sèrie R2-232 que permet reescriure la memòria RAM sense haver de compilar i sintetitzar el projecte de nou. També s'ha implementat un codi en Python per a poder escriure més còmodament els programes que l'usuari vol carregar a la RAM.

Los altos costes que implica la ejecución de cualquier ensayo real relacionado con la investigación en nanosatélites, así como la gran cantidad que recursos tanto humanos como temporales que estos requieren imposibilitan que cualquier institución educativa pueda ofrecer a su alumnado de forma generalizada la posibilidad de formarse en este ámbito. Este hecho ha generado una tendencia por parte de estas instituciones educativas superiores a sustituir el enfoque de enseñanza práctica por uno más orientado a al estudio teórico o la práctica a través de simulaciones computacionales. En este proyecto se lleva a cabo el desarrollo, diseño y fabricación a nivel mecánico y electrónico de un prototipo de pruebas enfocado al estudio tanto de los sistemas de control de actitud de un U1 CubeSat como de nuevas tipologías de placas fotovoltaicas basadas en patrones de Origami. En este prototipo se incluye tanto el diseño de un mecanismo de despliegue de dichas tipologías de placas fotovoltaicas desplegables como el desarrollo e implementación del dispositivo de control de actitud en el cual se incorpora dicho mecanismo. El desarrollo de este dispositivo también engloba una notable mejora en los subsistemas de medición, así como en el algoritmo de control de posición. El diseño tanto del bastidor del prototipo del U1 CubeSat como de los sistemas de control de actitud y el mecanismo de despliegue de placas fotovoltaicas es modular. Esto implica que cada uno de estos subsistemas puede funcionar de forma independiente al resto, lo que facilita en gran medida el estudio independiente de cada uno ellos y encaja a la perfección con la ideología de los CubeSats modulares, los cuales pueden variar sus funcionalidades dependiendo de los elementos añadidos., The high costs involved in carrying out any real test related to nano-satellite research, as well as the large amount of human and temporary resources that these requires, make it impossible for any educational institution to offer its students the possibility to be formed in this area. This fact has generated a tendency for these educational institutions to replace the practical teaching on this field by a more theoretical approach only practiced through computational simulations. However, this project carries out the development, design, and manufacture, at both mechanical and electronic level, of a test prototype focused on the study of the attitude control systems of a U1 CubeSat, as well as the new typologies of photovoltaic panels based on Origami patterns. This prototype includes both the design of an unfolding mechanism for these types of deployable photovoltaic panels, and the development and implementation of the attitude control device in which the mechanism is incorporated. Moreover, this project also covers notable improvements of both the measurement subsystems and the position control algorithm. The proposed design of the U1 CubeSat prototype frame, the attitude control systems and the photovoltaic panel deployment mechanism is modular. This implies that each of these subsystems can be operated independently from the rest, which greatly eases the study of each one of them and fits perfectly with the ideology of modular CubeSats, which can improve their functionalities depending on the added elements. Considering so, this prototype incorporates an attitude control device with a single reaction wheel and its corresponding MPU position sensor, as well as a mechanism for deploying photovoltaic panels based on Origami patterns. It should be noted that each of these systems includes its corresponding power supply, all controlled by an STM32 BluePill microcontroller and communicated through an HC-06 Bluetooth module.

GPU architectures have become popular for executing general-purpose programs. Moreover, they are some of the most efficient architectures for machine learning applications which are among the most trendy and demanding applications these days. GPUs rely on having a large number of threads that run concurrently to hide the latency among dependent instructions. This work presents SOCGPU (Simple Out-of-order Core for GPU), a simple out-of-order execution mechanism that does not require register renaming nor scoreboards. It uses a small Instruction Buffer and a tiny Dependence matrix to keep track of dependencies among instructions and avoid data hazards. Evaluations for an Nvidia GTX1080TI-like GPU show that SOCGPU provides a speed-up up to 3.76 in some machine learning programs and 1.58 on average for a variety of benchmarks, while it reduces energy consumption by 17.6%, with only 3.48% area overhead when using the same number of warps as the baseline. Moreover, we show that SOCGPU can reduce the number of concurrently running warps without hardly affecting performance, which can provide significant reductions in area, especially in the register file and the instruction scheduler logic, as well as other hardware structures of the GPU cores.

En aquest projecte s'ha implementat un pedal per a guitarra fent servir el microprocessador ATMEL SAM3x8E corresponent a un ARM Cortex M3. Aquest microprocessador és present a les plaques de desenvolupament Arduino DUE. El pedal d'efectes desenvolupat permet aplicar diferents efectes d'àudio que prèviament s'han programat. La idea principal ha estat aconseguir un pedal de guitarra multiefectes amb una mida i format iguals als d'un pedal d'un sol efecte. Mitjançant un commutador de peu es pot seleccionar i activar els diferents efectes programats fent servir l'entorn IDE (“Integrated Development Environment”) d'Ardunio. A diferència d'altres projectes ja existents de pedals de guitarra multiefectes digitals, el pedal desenvolupat en aquest projecte permet treballar amb 16, 20 o 24 bits, en funció de com es configura. Per això, s'ha utilitzat un codi extern d'àudio que es comunica amb el microprocessador present a la placa d'Arduino DUE a través de la interfície I2S (“Inter-IC Sound”). Per poder connectar la guitarra al pedal, s'ha dissenyat una etapa d'entrada que permetrà ajustar l'amplitud de la senyal provinent de la guitarra al marge d'entrada del còdec extern d'àudio. També s'ha dissenyat una etapa de sortida que permetrà filtrar la senyal provinent del coòdec d'àudio per poder enviar-la a l'amplificador de guitarra. Un cop dissenyada l'etapa d'entrada i de sortida, s'ha implementat una placa d'expansió per a la connexió de tota la circuiteria electrònica necessària amb la placa d'Arduino Due., En este proyecto se ha implementado un pedal para guitarra usando el microprocesador ATMEL SAM3x8E correspondiente a un ARM Cortex M3. Dicho microprocesador está presente en las placas de desarrollo Arduino DUE. El pedal de efectos desarrollado permite aplicar diferentes efectos de audio que previamente se ha tenido que programar. La idea principal ha sido conseguir un pedal de guitarra multiefectos con un tamaño y formato iguales a los de un pedal de un solo efecto. Mediante un conmutador de pie se puede seleccionar y activar los diferentes efectos programados utilizando el entorno IDE (“Integrated Development Environment”) de Ardunio. A diferencia de otros proyectos ya existentes de pedales de guitarra multiefectos digitales, el pedal desarrollado en este proyecto permite trabajar con 16, 20 o 24 bits, en función de cómo se configure. Para ello, se ha utilizado un códec externo de audio que se comunica con el microprocesador presente en la placa de Arduino DUE a través de la interfaz I2S (“Inter-IC Sound”). Para poder conectar la guitarra al pedal, se ha diseñado una etapa de entrada que va a permitir ajustar la amplitud de la señal proveniente de la guitarra al margen de entrada del códec externo de audio. También se ha diseñado una etapa de salida que va a permitir filtrar la señal proveniente del códec de audio para poder enviarla al amplificador de guitarra. Una vez diseñada la etapa de entrada y de salida, se ha implementado una placa de expansión para la conexión de toda la circuitería electrónica necesaria con la placa de Arduino Due., In this project, a guitar pedal has been implemented using the ATMEL SAM3x8E microprocessor corresponding to an ARM Cortex M3. This microprocessor is present in the Arduino DUE development boards. The effect pedal developed allows you to apply different audio effects that have to be programmed. The main idea has been to achieve a multi-effects guitar pedal with the same size and format as a single-effect pedal. By means of a footswitch you can select and activate the different programmed effects using the IDE environment (“Integrated Development Environment ”) of Ardunio. Unlike other existing projects of digital multi-effects guitar pedals, the pedal developed in this project allows to work with 16, 20 or 24 bits, depending on how it is configured. For this purpose, an external audio codec has been used that communicates with the microprocessor present on the Arduino DUE board through the I2S interface (“Inter-IC Sound”). In order to connect the guitar to the pedal, an input stage has been designed and it will allow adjusting the amplitude of the signal coming from the guitar to the input range of the external audio codec. An output stage has also been designed too and it will allow the signal coming from the audio codec to be filtered in order to send it to the guitar amplifier. Once the input and output stage have been designed, an expansion board has been implemented to connect all the necessary electronic circuitry with the Arduino Due board.

Durante la pandemia que hemos estado viviendo se han realizado una gran cantidad de tests en los centros de salud, realizados por personal médico, para seguir de cerca la incidencia de la COVID-19 en la sociedad y poder actuar en consonancia. Todos los millones de test realizados comportan un problema: Se está destinando personal médico a realizar esa función, dejando huecos en la atención primaria. En este trabajo de fin de grado se propone un sistema hardware para una máquina de autoservicio que pueda utilizar la población para realizar tests de saliva que puedan ser analizados posteriormente en laboratorios. La máquina sería válida tanto en la actual pandemia, ya que la COVID es detectable por vía salival, como en otras infecciones como hepatitis, VIH, bacterias diversas, marcadores tumorales, etc. El sistema que este documento describe es capaz de identificar a un usuario y dispensar un kit para que pueda realizar una prueba de saliva. Cuando el usuario haya realizado la prueba, podrá introducir su muestra de saliva en la propia máquina. La máquina, aparte de realizar las acciones ya comentadas, se encarga de asociar, en una base de datos, al paciente en cuestión con su muestra entregada. Así, posteriormente, en el laboratorio, será una tarea rápida la asociación de un ciudadano con una cierta muestra analizada. El sistema está compuesto por un microprocesador gobernando el módulo central y dos microcontroladores, conectados al central, gobernando los módulos de recolectar y dispensar. Al módulo central también va conectada una pantalla sobre la que se muestra la aplicación y puede interactuar el usuario, así como una impresora de etiquetas y un lector de código de barras, y a los módulos laterales van conectados un relé, un motor y unos sensores de temperatura e infrarojos, con las funciones de monitorear y comprobar el correcto funcionamiento del sistema, así como para cerrar lazos de control., During the pandemic that we have been experiencing, a large number of tests have been carried out in health centers, carried out by medical personnel, to monitor the incidence of COVID-19 in society and to be able to act accordingly. All the millions of tests carried out entail a problem: medical personnel are being assigned to perform this function, leaving gaps in primary care. In this final degree thesis, a hardware system is proposed for a self-service machine that the population can use to carry out saliva tests that can be later analyzed in laboratories. The machine would be valid both in the current pandemic, since COVID is detectable through the saliva, and in other infections such as hepatitis, AIDS, various bacteria, tumor markers, etc. The system that this document describes is capable of identifying a user and dispensing a kit so that users can perform a saliva test. When the user has carried out the test, he will be able to introduce his saliva sample into the machine itself. The machine, apart from carrying out the actions already mentioned, is in charge of associating, in a database, the patient in question with his delivered sample. Thus, later, in the laboratory, it will be a quick task to associate a citizen with his saliva sample. The system is made up of a microprocessor governing the central module and two microcontrollers, connected to the central CPU, governing the collecting and dispensing modules. A screen is also connected to the central module, on which the application is displayed, and the user can interact with it, as well as a label printer and a barcode reader. Also, a relay, a motor and some temperature and IR sensors are connected to the side modules. These sensors have the functions of monitoring and checking the correct operation of the system, as well as to close control loops.

En aquest projecte, es dissenya un microprocessador neuronal per ser implementat en FPGAs. Aquesta tecnologia consisteix en un processador softcore basat en RISC-V descrit amb SystemVerilog que s'utilitza per controlar un coprocessador encarregat d'executar una xarxa neuronal spiking amb propagació directa descrita amb VHDL. El control es fa amb senyals que es generen a partir d'instruccions SIMD personalitzades definides en una extensió del conjunt d’instruccions RSIC-V. Per fer-ho, es modifica el processador de manera que pugui detectar i descodificar les noves instruccions emmagatzemades a la seva memòria de programa. Per facilitar la tasca de definir el contingut de la memòria del programa, s'utilitza un codi escrit en C i es desenvolupa un conjunt d'instruccions C personalitzades. Aquestes instruccions es basen en l'ús de macros i inline assembly, i la seva finalitat és facilitar i permetre l'ús de les instruccions personalitzades RISC-V en el codi d'alt nivell. Per demostrar el correcte funcionament del projecte, se simula el microprocessador neuronal i després es prova a l'FPGA d'una placa de desenvolupament Nexys 4, amb el coprocessador implementat per resoldre el problema XOR. La implementació del coprocessador es replica amb C i s'executa a l'FPGA utilitzant només el processador predeterminat sense modificar. Finalment, els resultats s'analitzen i es comparen per determinar les compensacions entre els dos enfocaments en termes de temps d'execució, consum d'energia i espai utilitzat., En este proyecto, se diseña un microprocesador neuronal para su implementación en FPGAs. Esta tecnología consiste en un procesador softcore basado en RISC-V descrito con SystemVerilog que se utiliza para controlar a un coprocesador encargado de ejecutar una red neuronal spiking con propagación directa descrita con VHDL. El control se realiza con señales que se generan a partir de instrucciones SIMD personalizadas definidas en una extensión del conjunto de instrucciones RSIC-V. Para ello, se modifica el procesador de forma que pueda detectar y descodificar las nuevas instrucciones almacenadas en su memoria de programa. Para facilitar la tarea de definir el contenido de la memoria del programa, se utiliza un código escrito en C y se desarrolla un conjunto de instrucciones C personalizadas. Estas instrucciones se basan en el uso de macros e inline assembly, y su finalidad es facilitar y permitir el uso de las instrucciones personalizadas RISC-V en el código de alto nivel. Para demostrar el correcto funcionamiento del proyecto, se simula el microprocesador neuronal y después se prueba en la FPGA de una placa de desarrollo Nexys 4, con el coprocesador implementado para resolver el problema XOR. La implementación del coprocesador se replica con C y se ejecuta en la FPGA utilizando sólo el procesador predeterminado sin modifcar. Por último, los resultados se analizan y se comparan para determinar las compensaciones entre ambos enfoques en términos de tiempo de ejecución, consumo de energía y espacio utilizado., In this project, a neural microprocessor is designed to be implemented in FPGAs. This technology consists of a RISC-V-based soft processor described in SystemVerilog that is used to control a coprocessor in charge of executing a feedforward spiking neural network described in VHDL. The control is done with signals that are generated from custom-designed SIMD instructions defined in a RISC-V ISA extension. To do it, the processor is modified such that it can detect and decode the new instructions stored in its program memory. To facilitate the task of defining the program memory contents, a code written in C is used and a set of custom C instructions is developed. These instructions are based on the use of macros and inline assembly, and their purpose is to facilitate and allow the use of the RISC-V custom instructions in the high-level code. To demonstrate the correct operation of the project, the neural microprocessor is simulated and then tested on the FPGA of a Nexys 4 development board, with the coprocessor implemented for solving the XOR problem. The coprocessor implementation is replicated with C and executed in the FPGA using only the default processor without being modified. Finally, the results are analyzed and compared to determine the trade-offs between the two approaches in terms of execution time, power consumption, and utilized space.

An important drawback of cycle-accurate microarchitectural simulators is that they are several orders of magnitude slower than the system they model. This becomes an important issue when simulations have to be repeated multiple times sweeping over the desired design space. In the specific context of graphics workloads, performing cycle-accurate simulations are even more demanding due to the high number of triangles that have to be shaded, lighted and textured to compose a single frame. As a result, simulating a few minutes of a video game sequence is extremely time-consuming.In this paper, we make the observation that collecting information about the vertices and primitives that are processed, along with the times that shader programs are invoked, allows us to characterize the activity performed on a given frame. Based on that, we propose a novel methodology for the efficient simulation of graphics workloads called MEGsim, an approach that is capable of accurately characterizing entire video sequences by using a small subset of selected frames which substantially drops the simulation time. For a set of popular Android games, we show that MEGsim achieves an average simulation speedup of 126×, achieving remarkably accurate results for the estimated final statistics, e.g., with average relative errors of just 0.84% for the total number of cycles, 0.99% for the number of DRAM accesses, 1.2% for the number of L2 cache accesses, and 0.86% for the number of L1 (tile cache) accesses., This work has been supported by the CoCoUnit ERC Advanced Grant of the EU’s Horizon 2020 program (grant No 833057), the Spanish State Research Agency (MCIN/AEI) under grant PID2020-113172RB-I00, and the ICREA Academia program., Peer Reviewed, Postprint (author's final draft)

Cache Replacement Policies are known to have an important impact on hit rates. The OPT replacement policy [27] has been formally proven as optimal for minimizing misses. Due to its need to look far ahead for future memory accesses, it is often reduced to a yardstick for measuring the efficacy of other practical caches. In this paper, we bring the OPT to life, in architectures for mobile GPUs, for which energy efficiency is of great consequence. We also mold other factors in the memory hierarchy to enhance its impact. The end results are a 13.8% decrease in the memory hierarchy energy consumption and an increased throughput in the Tiling Engine. We also observe a 5.5% decrease in the total GPU energy and a 3.7% increase in frames per second (FPS)., This work has been supported by the CoCoUnit ERC Advanced Grant of the EU’s Horizon 2020 program (grant No 833057), the Spanish State Research Agency (MCIN/AEI) under grant PID2020-113172RB-I00, the ICREA Academia program and the AGAUR grant 2020-FISDU-00287. We would also like to thank the anonymous reviewers for their valuable comments., Peer Reviewed, Postprint (author's final draft)

El moviment de codi obert promet revolucionar el món del maquinari igual que el programari ha revolucionat. Gràcies a l'arquitectura de conjunt d'instruccions o ISA (de l'anglès Instruction Set Architecture) RISC-V de codi obert, molts projectes s'estan obrint camí per oferir una alternativa a l'hermètic i privatiu món de l'arquitectura de computadors. En aquest context neix el projecte DRAC, les sigles del qual fan referència, de l'anglès, a Designing RISC-V-based Accelerators for next-generation Computers. Aquest projecte, liderat pel Barcelona Supercomputing Center (BSC), desenvolupa processadors i acceleradors basats en la tecnologia RISC-V, amb l'objectiu d'accelerar tasques de seguretat, medicina personalitzada i navegació autònoma. Aquesta tesi té com a propòsit dissenyar, implementar i verificar una bootrom pel SoC (de l'anglès System on Chip) de 64 bits DRAC 22 nm. Aquest SoC integra un processador RISC-V de 7 etapes anomenat Sargantana. El disseny del SoC, basat en l'anterior \textit{tape-out} anomenat PreDRAC, es divideix en dues parts. Una part conté tots els components orientats a l'ASIC; l'altra conté els elements orientats a la FPGA. Una de les raons principals d'aquesta divisió és que no existia una bootrom orientada a ASIC i, per tant, calia utilitzar la FPGA per arrencar el xip. Amb la integració de la bootrom desenvolupada en aquesta tesi, el SoC serà capaç d'arrencar per ell mateix, eliminant la part orientada a la FPGA del disseny del SoC., The open-source movement promises to revolutionize the hardware world just as it has revolutionized software. Thanks to the open-source RISC-V instruction set architecture (ISA), many projects are making their way to offer an alternative in the hermetic and proprietary world of computer architecture. The DRAC project, whose acronym refers to Designing RISC-V-based Accelerators for next-generation Computers, was created in this context. This project, led by the Barcelona Supercomputing Center (BSC), develops processors and accelerators based on RISC-V technology, and their purpose is to accelerate security tasks, personalized medicine and autonomous navigation. This thesis aims to design, implement and verify a bootrom for the 64-bit DRAC 22 nm System on Chip (SoC). This SoC integrates an in-order 7-stage RISC-V core called Sargantana. The SoC design, based on the previous tape-out PreDRAC, is divided into two parts. One part contains all the ASIC-oriented components; the other contains the FPGA-oriented components. One of the main reasons for this division is that there was no ASIC-oriented bootrom, and therefore, it was necessary to use the FPGA to boot the chip. With the integration of the bootrom developed in this thesis, the SoC will be able to boot by itself, eliminating the FPGA-oriented part of the SoC design.

Aquest document pretén raonar i justificar la actualització del kit de laboratori de la informàtica industrial que s’utilitza en el campus de l’Escola d’Enginyeria de Barcelona Est (EEBE) de la Universitat Politècnica de Catalunya (UPC). Per a aquesta finalitat es proposa canviar el processador que s’utilitza actualment, l’Intel 8051 de 8 bits, per l’STM32 de 32 bits i arquitectura ARM, la més utilitzada actualment per fabricants de dispositius mòbils. Inicialment, es fa una breu descripció del kit de laboratori actual i es fa un estudi de l’arquitectura ARM i del microprocessador escollit, l’STM32F401RE. Per a simplificar el projecte i adaptar-lo a la extensió d’un TFG realitzat per un sol alumne, s’utilitza una placa de desenvolupament, la NUCLEO-F401RE, que inclou el microcontrolador i diferents components, connectors i característiques que es detallen en aquest document. Un cop definit el component clau del kit, el microcontrolador, es fa la selecció de perifèrics que formaran part de la PCB, en forma de shield, per a la placa de desenvolupament, creant així un kit de laboratori actualitzat. Els components escollits pretenen poder donar continuïtat al kit anterior i a les pràctiques de laboratori i metodologia utilitzades fins ara per a tenir una transició d’un a l’altre el més suau possible. En aquest document també es detalla i justifica el software utilitzat per a les diverses fases del projecte i es fa un repàs a la programació, proporcionant codis d’exemple. També es defineixen les fases del prototipat físic i es mostra el resultat final obtingut. Al final del document es fa un estudi econòmic del preu associat al prototip ja realitzat i del cost de una possible producció en sèrie per finalitzar donant les conclusions del projecte, justificant la necessitat d’aquesta actualització.

A aquest treball de fi de grau es dissenya i implementa, fent ús del llenguatge VHDL, el nucli d’un microcontrolador amb el conjunt d’instruccions RISC-V, concretament el conjunt base RV32I. L’objectiu es crear un microprocessador capacitat per al món laboral, doncs el conjunt d’instruccions es comercial i d’ús lliure i gratuït i la placa utilitzada per a la implementació del disseny té unes característiques decents, i amb un nivell de complexitat apte per a poder treballar-ho en universitats i altres estudis relacionats amb la electrònica digital. Per a això, s’ha dut a terme una recerca d’informació necessària sobre el llenguatge, conjunt d’instruccions i la teoria que es treballa, s’estudia el llistat d’instruccions que s’han d’executar, es dissenya el datapath, que es l’esquema principal del disseny i, per últim, la unitat de control la qual s’implementa juntament al datapath per a completar el funcionament del processador. Una vegada el disseny es complert, es verifica que el seu funcionament sigui correcte i posteriorment es sintetitza i s’implementa, de manera que es pugui assegurar que es físicament viable i apte per a la placa seleccionada., En este trabajo de final de grado se diseña e implementa, usando el lenguaje VHDL, el núcleo de un microcontrolador con el conjunto de instrucciones RISC-V, concretamente el conjunto base RV32I. El objetivo es crear un microprocesador capacitado para el mundo laboral, pues el conjunto de instrucciones es comercial y de uso libre y gratuito y la placa usada para la implementación del diseño tiene unas características decentes, y con un nivel de complejidad apto para poder trabajarlo en universidades u otros estudios relacionados con la electrónica digital. Para ello, se ha llevado a cabo una búsqueda de información necesario sobre el lenguaje, conjunto de instrucciones y la teoría que se trabaja, se estudia el listado de instrucciones que se deben ejecutar, se diseña el datapath, que es el esquema principal del diseño y, por último, la unidad de control la cual se implementa junto al datapath para completar el funcionamiento del procesador. Una vez el diseño esta completado, se verifica que su funcionamiento sea correcto y posteriormente se sintetiza y se implementa, de manera que se puede asegurar que es físicamente viable y apto para la placa seleccionada., In this bachelor’s thesis the core of a microcontroller is designed and implemented, using the language VHDL, with the instruction set RISC-V, specifically the base set RV32I. The objective is to create a microprocessor capable for working with it, since the instruction set is commercial and of open and free use and the board used for the implementation of the design have a decent characteristic, and with a suitable complexity level for working it in university or another digital electronic related studies. In order to achieve it, it’s been conducted a necessary information research about the language, the instruction set and the theory that it’s being working with, it’s studied the list of instructions that are going to be executed, the datapath is designed, that is the principal scheme of the design, and, lastly, the control unit is implemented next to the datapath for completing the processor operating. Once the design is completed, the correct operation is verified and afterwards is synthetized and implemented, to secure that is physically feasible and suitable for the selected board.

This document is an introduction to Machine Learning and the Artificial Neural Networks. The implementation of an automatic learning model is carried out and it is deployed on a microprocessor, in order to demonstrate that it is possible to implement an automatic learning model locally on a device with a very limited memory. The model has been implemented on the Arduino Nano 33 BLE Sense board using the Edge Impulse platform, a useful tool for developing models for microprocessors and limited memory devices. The aim is to obtain a model that can be executed locally without requiring an Internet connection and with minimum latency, while maintaining the privacy of the data analysed and keeping energy and memory consumption to a minimum., En este documento se hace una introducción al Machine Learning y a las Redes Neuronales Artificiales. Se realiza la implementación de un modelo de aprendizaje automático que se despliega sobre un microprocesador, para demostrar que es posible implementar un modelo de aprendizaje automático de forma local sobre un dispositivo de memoria muy limitada. El modelo se ha implementado sobre la placa Arduino Nano 33 BLE Sense haciendo uso de la plataforma Edge Impulse, una herramienta muy útil para desarrollar modelos para microprocesadores y dispositivos de memoria limitada. Los objetivos que se quieren lograr es obtener un modelo que se ejecute de forma local sin requerir de una conexión a Internet en el que se obtenga una latencia mínima, donde se mantenga la privacidad de los datos analizados y que el consumo de energía y memoria sea el mínimo posible., En aquest document es fa una introducció al Machine Learning i a les Xarxes Neuronals Artificials. Es realitza la implementació d?un model d?aprenentatge automàtic que es deplega sobre un microprocessador, per tal demostrar que és possible implementar un model d?aprenentatge automàtic de forma local sobre un dispositiu de memòria molt limitada. El model s?ha implementat sobre la placa Arduino Nano 33 BLE Sense fent ús de la plataforma Edge Impulse, una eina molt útil per desenvolupar models per a microprocessadors i dispositius de memòria limitada. Els objectius que és volen assolir és obtenir un model que s?executi de forma local sense requerir d?una connexió a Internet en el que s?obtingui una latència mínima, on es mantingui la privadesa de les dades analitzades i que el consum d?energia i memòria sigui el mínim possible.

Currently, human needs and healthcare are usually related with signal detection and interpretation, beginning from favorite music and ending with heart rate. Until last decade, signals were only related with physical, telecommunication and electronic fields but now biotechnology is one of the most promising study fields. The idea of using biological signals to detect human health problems, like measuring in real time the glucose in blood, is giving spectacular results to diabetic people. Besides, this technology has a huge range of applications. Society uses a huge range of technology and it takes a lot of data about people social life. These devices are in contact with human organs such as skin, ears or eyes, the interest is on taking data from them, reading biological information of these organs to give us further more information about mood and health. Mobile phones, smart watches, ear-pods, etc. known as IoT systems, connected to human biology will create revolutionary idea of biotechnology sensing procedures at real time. This idea consists on apply the IoT technologies on biosensor appliance. This engineering telecommunication bachelor thesis is based on designing and developing a wireless, flexible and passive device for biosensor applications which in the future is going to read information about biological facts applying a RFID structure to achieve the previous characteristics. After lots of experimental trials and simulations, the results shown the possibility of using the RFID structure to create useful biosensors to satisfy human common life needs. This technology will have lots of applications in most used social devices.

Power consumption is one of the main aspects in the overall performance of en electronic circuit. Design for low power can be applied from algorithm through the physical implementation of the integrated circuit. In this work, different low power implementation techniques will be applied to an existing System on Chip (SoC) design of a RISC-V processor. Low power approaches like multi-voltage supply, power gating and internal power optimization will be explored., El consumo de potencia es uno de los aspectos más importantes en diseño de circuitos. Opciones de diseño para bajar consumo pueden ser implentadas dentro de los algoritmos de la implementación física. En este trabajo, varias técnicas serán aplicadas a un procesador RISC-V. Varias técnicas como multi supply voltage, power gating y power optmization van a ser analizados.

Current microprocessors include several knobs to modify the hardware behavior in order to improve performance, power, and energy under different workload demands. An impractical and time consuming offline profiling is needed to evaluate the design space to find the optimal knob configuration. Different knobs are typically configured in a decoupled manner to avoid the time-consuming offline profiling process. This can often lead to underperforming configurations and conflicting decisions that jeopardize system power-performance efficiency. Thus, a dynamic management of the different hardware knobs is necessary to find the knob configuration that maximizes system power-performance efficiency without the burden of offline profiling. In this paper, we propose libPRISM, an infrastructure that enables the transparent management of multiple hardware knobs in order to adapt the system to the evolving demands of hardware resources in different workloads. libPRISM can minimize execution time, energy-delay product or power consumption by dynamically managing the SMT level, the data prefetcher, and the DVFS hardware knobs. Overall, the proposed solutions increase performance up to 130% (16.9% on average), reduce energy-delay product up to 80%, and reduce power consumption up to 33% depending on the target metric compared to the default knob configuration of the system., This work has been supported by the RoMoL ERC Advanced Grant (GA 321253), by the European HiPEAC Network of Excellence, by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P), by Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272) and by IBM/BSC Deep Learning Center initiative.This research was developed in part with funding from the Defense Advanced Research Projects Agency (DARPA)., Peer Reviewed, Postprint (author's final draft)

This project is the implementation of an error detection and recovery system on top of the Inkel Pentiun processor, a RISC-V-like processor developed in earlier stages of this Master. The error detection system will detect execution errors caused by transient faults (Single-Event Upsets, or SEUs for short), and is then able to recover the execution to a previous stable point without breaking the intended behaviour of the code being executed. The code for the project is attached as a zip file, but it is also available on my public Git repository, at https://github.com/adriaaap/TFM-Inkel-error-recovery

The decrease in the size of transistors and technology nodes has made manufacturing processes increasingly difficult and unreliable, Design for Test techniques provide measures to thoroughly test the manufactured device for quality and coverage. The main objective of this work is to apply those techniques to a processor, specifically the PreDRAC design, which is a RISC-V based SoC developed in collaboration with the BSC, CIC-IPN, IMB-CNM (CSIC) and UPC. To achieve this, DFT implementation steps through different phases of the elaboration of the preDRAC are performed, with the objective of maintaining a low impact on the area, timing and power values concerning the original design. During synthesis step the DFT configuration is defined, scan structures are added to improve the testability and compression structures are inserted to control scan chains. Then, the test patterns needed to detect defects are generated and simulated, studying two different types of analysis (static and dynamic). Finally, a Place&Route has been performed to elaborate a final layout. The final results show that DFT can successfully be integrated with the preDRAC SoC, with some overhead in the area and not degrading the timing constraints. The reports of the test pattern generation detailed that with the implemented design, high test coverage values are achieved. From the simulations carried out, we extract that all these test vectors have been successfully verified.

En aquest treball s’ha realitzat el disseny i les proves de funcionament per simulació d’un microcontrolador, capaç d’executar totes les instruccions del set d’instruccions AVR1 del fabricant de microcontroladors Atmel. Aquest disseny s’ha creat amb objectius didàctics, per tal de que estudiants puguin aprendre el funcionament intern d’un microcontrolador i el puguin provar fent servir instruccions d’un set d’instruccions comercial. El fet de que sigui un set d’instruccions comercial fa, que els estudiants, puguin posteriorment aplicar els coneixements adquirits en aquest entorn didàctic en la vida laboral. També, al tenir tota la documentació del disseny, les universitats el poden modificar, adaptant-lo a les seves necessitats. En el document, s’explica primerament que és un microprocessador, element principal d’un microcontrolador. Seguidament, s’explica que és un microcontrolador i alguns microcontroladors i microprocessadors disponibles al mercat i les seves característiques. Després d’això, es fa èmfasi en el disseny realitzat, explicant primerament les accions realitzades per cada una de les instruccions del set d’instruccions AVR1, explicant després el disseny del Datapath, (conjunt d’elements del microcontrolador capaços de realitzar les accions necessàries per poder executar totes les instruccions) i la unitat de control (element que gestiona quines accions fa en cada moment el Datapath, per tal de que l’execució de la instrucció es produeixi correctament). Explicant per últim, les proves realitzades per comprovar que el microcontrolador executa totes les instruccions del set AVR1 satisfactòriament., En este trabajo se ha realizado el diseño y las pruebas por simulación de un microcontrolador, capaz de ejecutar todas las instrucciones del set de instrucciones AVR1 del fabricante de microcontroladores Atmel. Este diseño se ha creado con objetivos didácticos, para que los estudiantes puedan aprender el funcionamiento interno de un microcontrolador y lo puedan probar usando instrucciones de un set de instrucciones comercial. El hecho de que sea un set de instrucciones comercial hace, que los estudiantes, puedan posteriormente aplicar los conocimientos adquiridos en este entorno didáctico en la vida laboral. También, al tener toda la documentación del diseño, las universidades lo pueden modificar, adaptándolo a sus necesidades. En el documento, se explica primeramente que es un microprocesador, elemento principal de un microcontrolador. Seguidamente, se explica que es un microcontrolador y algunos microcontroladores y microprocesadores disponibles en el mercado y sus características. Después de esto, se hace énfasis en el diseño realizado, explicando primeramente las acciones realizadas por cada una de las instrucciones del set de instrucciones AVR1, explicando después el diseño del Datapath, (conjunto de elementos del microcontrolador capaces de realizar las acciones necesarias para poder ejecutar todas las instrucciones) i la unidad de control (elemento que gestiona que acciones hace en cada momento el Datapath, para que la ejecución de la instrucción se produzca correctamente). Explicando por último las pruebas realizadas para comprobar que el microcontrolador ejecuta todas las instrucciones del set AVR1 satisfactoriamente., This project contains the design and operation tests via simulation of a microcontroller, capable of executing all of the instructions of the AVR1 instruction set by the microcontroller manufacturer Atmel. This design has been created with educational use in mind, so that students may learn the internal workings of a microcontroller and test it using instructions form a commercial instruction set. The fact that the instructions are from a commercial instruction set, means that the knowledge gained by the students while working with this microcontroller can be later applied to the workplace. Also, the fact that all the documentation regarding the design is available means that the universities can modify it to suit their needs. First on the document, there is the definition of a microprocessor, the main element in a microcontroller. Followed by the definition of microcontroller and finally some microcontrollers and microprocessors available on the market. Then, we focus on the design made, explaining first what each of the instructions of the AVR1 instruction set does, followed by an explanation of the Datapath, (set of elements capable of doing the necessary actions to be able to execute all the instructions) and the control unit (the element in charge of controlling which actions the Datapath does on each instance, to ensure that the execution of the instruction is completed correctly). Explaining lastly the tests made to check that the microcontroller executes correctly all the instructions form the AVR1 instruction set.

Autonomous driving (AD) imposes the need for safe computations in high-performance computing (HPC) components such as GPUs, thus with capabilities to detect and recover from errors since a safe state may not exist anymore. This can be achieved with Triple Modular Redundancy (TMR) for computation components. Furthermore, error detection capabilities need to provide some form of diversity to avoid the case where a single fault leads all redundant executions lead to the same error, which would go undetected. In our past work, we assessed GPUs against dual modular redundancy (DMR) with diversity, showing their potential and limitations to provide diverse redundancy building on reset and restart for recovery. However, such recovery scheme may be too slow for some applications. This paper proposes a software-only solution to deliver diverse TMR on commercial off-the-shelf (COTS) GPUs. Our work details how staggered execution can be achieved and assesses the performance of TMR on COTS GPUs. Moreover, we identify those elements where diversity cannot be guaranteed and provide some discussion comparing the case of DMR and TMR for those elements., This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 871467 (SELENE). Leonidas Kosmidis has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under a Juan de la Cierva Formacion postdoctoral fellowship with number FJCI-2017-34095., Peer Reviewed, Postprint (author's final draft)