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The performance of complex and advanced applications of industrial reports requires large computational power. The control system presented in this paper is designed as a multi-microcomputer system. The main purpose of this system is to create a pleasant environment for present and further studies in robotic research. The Advanced Robot Control System (ARC) uses multiple microcomputers based on iAPX 8086 processors. A local bus of each processor allows additional memory and Input/output expansions for increased throughput. Nevertheless, the rising calculation effort for the kinematic and dynamic relations shows the insufficient computing power of standard microprocessors. Therefore a fast floating-point processor has been developed. This Robot Arithmetic Processor (RAP) is built up with bipolar bit-slice components, special arithmetic modules and hardware control mechanisms for on- and off-line diagnostic functions.

Hyperdimensional computing (HDC) is a brain-inspired computing paradigm-based on high-dimensional holistic representations of vectors. It recently gained attention for embedded smart sensing due to its inherent error-resiliency and suitability to highly parallel hardware implementations. In this work, we propose a programmable all-digital CMOS implementation of a fully autonomous HDC accelerator for always-on classification in energy-constrained sensor nodes. By using energy-efficient standard cell memory (SCM), the design is easily cross-technology mappable. It achieves extremely low power, 5 $\mu \text{W}$ in typical applications, and an energy efficiency improvement over the state-of-the-art (SoA) digital architectures of up to $3\times $ in post-layout simulations for always-on wearable tasks such as Electromyography (EMG) hand gesture recognition. As part of the accelerator’s architecture, we introduce novel hardware-friendly embodiments of common HDC-algorithmic primitives, which results in $3.3\times $ technology scaled area reduction over the SoA, achieving the same accuracy levels in all examined targets. The proposed architecture also has a fully configurable datapath using microcode optimized for HDC stored on an integrated SCM-based configuration memory, making the design “general-purpose” in terms of HDC algorithm flexibility. This flexibility allows usage of the accelerator across novel HDC tasks, for instance, a newly designed HDC-algorithm for the task of ball bearing fault detection.

The Advanced GAmma Tracking Array (AGATA) multidetector spectrometer will provide precise information for the study of the properties of the exotic nuclear matter (very unbalanced proton (Z) and neutron (N) numbers) along proton- and neutron-drip lines and of super-heavy nuclei. This is done using the latest technology of particle accelerators. The AGATA spectrometer consists of 180 high-purity germanium detectors. Each detector is segmented into 38 segments. The very harsh project requirements are to measure gamma-ray energies with very high resolution ( $ ) at a high detector counting rate (50 K events/s/crystal). This results in a very high data transfer rate per crystal (5–8 Gb/s). The 38 segments are sampled at 100 MHz with 14 bits of resolution. The samples are continuously transferred to the control and processing (CAP) module, which reduces the data rate from 64 to 5 Gb/s. The CAP module also adds continuous monitoring data, which results in total outgoing data rate of 10 Gb/s. The serial transfer acquisition and readout over Ethernet (STARE) module is designed to fit between the CAP module and the computer farm. It will package the data from the CAP module and transmit it to the server farm using a 10-Gb/s user datagram protocol (UDP) connection with a delivery insurance mechanism implemented to ensure that all data are transferred.

Exploiting instruction level parallelism (ILP) is a widely used method for increasing performance of processors. While traditional very long instruction word (VLIW) processors can exploit ILP energy-efficiently thanks to static instruction scheduling, they suffer from bad code density with serial parts that cannot utilize the multi-issue capabilities. Transport triggered architecture (TTA) is a variation of the VLIW paradigm with an exposed datapath that improves scaling of VLIW processors with the cost of even wider instructions by exposing the datapath interconnection network to the programmer. To this end, we propose Dual-IS, an architecture that implements a TTA multi-issue and RISC-V compatible single-issue instruction-set modes by means of a microcoded control path. By utilizing the instruction set modality, the TTA mode can be used in codes that benefit from ILP, while a single-issue RISC-V ISA mode reduces instruction stream energy and code size for sequential programs. Thanks to the TTA programming model, the static multi-issue mode can be implemented without additional register file ports. The processor was synthesized on a 28 nm ASIC technology. For this design point, when instruction-set mode was selected based on energy-delay product at the program granularity, with CHStone benchmarks, Dual-IS had on average 14% lower energy-delay product compared to a single-mode TTA processor with a similar datapath, while only adding a 3% overhead in the core area. Dual-IS achieved on average 15% and in the best case 33% smaller run times than a single-issue RISC-V implementation by running programs in the TTA mode only when it was beneficial in terms of performance. A pre-print accepted to ARCS 2022 https://arcs-conference.org

IoT devices are becoming increasingly ubiquitous because they have greatly simplified many aspects of our daily life and our work. However, most firmware in these embedded devices carry various security vulnerabilities, such as hard-cod-ed passwords, cryptographic keys, insecure configurations and backdoors. Recent large-scale attacks have demonstrated that the security vulnerabilities in IoT firmware have posed a severe threat to the Internet infrastructure. In this work, we design a hybrid platform to detect vulnerabilities in IoT firmware, which integrates both offline static detection and online dynamic detection. Our evaluation on real IoT devices shows that the proposed platform can effectively identify various security weaknesses and risks in firmware, such as dangerous processes, exploitable vulnerabilities, and other attack surfaces.

Firmware vulnerabilities raise serious security concerns with the rapid growth in connected embedded devices. Fuzzing is an effective dynamic testing technique to find those vulnerabilities; however, firmware fuzzing is very limited by hardware dependence, such as on-chip and off-chip peripherals. The latest elegant approaches are making substantial progress in hardware-independent firmware fuzzing, but there is room for further improvement. We observe that hardware-independent peripheral modeling is scalable but slow at the register level; in contrast, at the abstract function level, it is fast but has limited scalability. Firmware fuzzing is still challenging in terms of achieving both scalability and efficiency. To address this problem, we present a dual-level approach that leverages register level modeling and selective function level modeling in a hybrid manner. Our method starts firmware fuzzing at the register level and connects peripheral handlers while executing hardware abstraction layer functions. We evaluate our method in terms of efficiency, scalability, and effectiveness with four real-world firmware and demonstrate the possibility of relatively fast and scalable firmware fuzzing that combines the benefits of the two levels.

Programa doutoral em Engenharia Eletrónica e de Computadores (PDEEC) (especialidade de Informática Industrial e Sistemas Embebidos), O ecossistema de sistemas embebidos de hoje tornou-se enorme, cobrindo vários e diferentes sistemas, exigindo desempenho e mobilidade completa enquanto atingem autonomias de bateria cada vez maiores. Mas a crescente frequência de relógio que resultou em dispositivos cada vez mais rápidos começou a estagnar antes dos transístores pararem de encolher. Plataformas Field Programmable Gate Array (FPGA) são uma solução alternativa para a implementação de sistemas completos e reconfiguráveis. Fornecem desempenho e eficiência computacional para satisfazer requisitos da aplicação e do sistema embebido. Vários Sistemas Operativos (SO) assistidos por FPGA foram propostos, mas ao estreitar seu foco na síntese do datapath do acelerador de hardware, a grande maioria ignora a integração semântica destes no SO. Ambientes de síntese de alto nível (HLS) elevaram a abstração além da linguagem de transferência de registo (RTL), seguindo uma abordagem específica de domínio enquanto misturam software e abstrações de hardware ad hoc, que dificultam as otimizações. Além disso, os modelos de programação para software e hardware reconfigurável carecem de semelhanças, o que com o tempo dificultará a Exploração do Ambiente de Design (DSE) e diminuirá o potencial de reutilização de código. Para responder a estas necessidades, propomos HAL-ASOS, uma ferramenta para implementar sistemas embebidos baseados em Linux que fornece (1) elasticidade no design em conformidade com a natureza evolutiva deste SO, (2) integração semântica profunda de tarefas de hardware nos modelos de programação do Linux, (3) facilidade na gestão de complexidade através de metodologia e ferramentas para apoiar o design, verificação e implementação, (4) orientada por princípios de design híbridos e eficiência no sistema. Para avaliar as funcionalidades da ferramenta, foi implementado um aplicativo criptográfico que demonstra alcance de desempenho enquanto se emprega a metodologia de design. Novos níveis de desempenho são atingidos numa aplicação de Visão por Computador que explora recursos de programação assíncrona-síncrona. Os resultados demonstram uma abordagem flexível na reconfiguração entre hardware e software, e desempenho que aumenta consistentemente com acréscimo de recursos ou frequência de relógio., Today’s embedded systems ecosystem became huge while covering several and different computer-based systems, demanding for performance and complete mobility while experiencing longer battery lives. But the rampant frequency that resulted in faster devices began hitting a wall even before transistors stopped shrinking. Field Programmable Gate Array (FPGA) platforms are an alternative solution towards implementing complete reconfigurable systems. They provide computational power, efficiency, in a lightweight solution to serve the application requirements and increase performance in the overall system. Several FPGA-assisted Operating Systems (OS) have been proposed, but by narrowing their focus on datapath synthesis of the hardware accelerator, they completely ignore the deep semantic integration of these accelerators into the OS. State-of-the-art High-Level Synthesis (HLS) environments have raised the level of abstraction beyond Register Transfer Language (RTL) by following a domain-specific approach while mixing ad hoc software and hardware abstractions, making harder for performance optimizations. Furthermore, the programming models for software and reconfigurable hardware lack commonalities, which in time will hinder the Design Space Exploration (DSE) and lower the potential for code reuse. To overcome these issues, we propose HAL-ASOS, a framework to implement Linux-based Embedded systems which provides (1) elasticity by design to comply with the evolutive nature of Linux, (2) deep semantic integration of the hardware tasks in the Linux programming models, (3) easy complexity management using methodology and tools to fully support design, verification and deployment, (4) hybrid and efficiency-oriented design principles. To evaluate the framework functionalities, a cryptographic application was implemented and demonstrates performance achievements while using the promoted application-driven design methodology. To demonstrate new levels of performance that can be achieved, a Computer Vision application explores several mixed asynchronous-synchronous programming features. Experiments demonstrate a flexible design approach in terms of hardware and software reconfiguration, and significant performance that increases consistently with the rising in processing resources or clock frequencies., Financial support received from Portuguese Foundation for Science and Technology (FCT) with the PhD grant SFRH/BD/82732/2011.

A multitude of privacy-enhancing technologies (PETs) has been presented recently to solve the privacy problems of contemporary services utilizing cloud computing. Many of them are based on additively homomorphic encryption (AHE) that allows the computation of additions on encrypted data. The main technical obstacles for adaptation of PETs in practical systems are related to performance overheads compared with current privacy-violating alternatives. In this article, we present a hardware/software (HW/SW) codesign for programmable systems-on-chip (SoCs) that is designed for accelerating applications based on the Paillier encryption. Our implementation is a microcode-based multicore architecture that is suitable for accelerating various PETs using AHE with large integer modular arithmetic. We instantiate the implementation in a Xilinx Zynq-7000 programmable SoC and provide performance evaluations in real hardware. We also investigate its efficiency in a high-end Xilinx UltraScale+ programmable SoC. We evaluate the implementation with two target use cases that have relevance in PETs: privacy-preserving computation of squared Euclidean distances over encrypted data and multi-input functional encryption (FE) for inner products. Both of them represent the first hardware acceleration results for such operations, and in particular, the latter one is among the very first published implementation results of FE on any platform.

Computer hardware is usually perceived as more secure than software. However, recent trends lead us to reexamine this belief. We draw attention to the "firmwarization" of hardware and argue for revisiting the role of hardware and software in systems security.

Firmware functional validation suffers from a series of performance limitations in practice, which in turn heavily relies on manual effort and becomes a major bottleneck of product time cycle. The requirement of repetitive run-time firmware execution for the validation environment demands novel techniques to accelerate the validation process. We propose an online firmware functional validation scheme utilizing the colored Petri net (CPN) model which can be generated automatically from the firmware source code. With simulation runs on the generated CPN models at run-time, the firmware execution path is presented and, if an error occurs, the location of error can be identified. An integrated validation tool has been designed and implemented to show the proposed validation methodology’s potential and effectiveness. This tool is used in the validation of the universal serial bus (USB) initialization in unified extensible firmware interface (UEFI).

This paper discusses the methods of optimal IIR filter FPGA implementation. The methods are focused on the reduction of occupied resources and increasing data throughput. Higher demands on an internal controller complexity are successfully solved by utilizing programmable microcode controller. The novelty of SOS core and its capabilities are presented and different variants of SOS core are assessed. The workflow of IIR filter design using MATLAB considering rounded coefficient method is demonstrated.

Code generation for VLIW processors includes several optimization problems like code optimization, instruction scheduling, and register allocation. The high complexity of these problems usually does not allow the computation of the optimal solution. Instead, optimization techniques, e.g., based on heuristics, are used to find acceptable solutions in a reasonable time. List scheduling is a well known heuristic-based microcode compaction method, that bases its scheduling decisions on weights derived from dependency analysis of the input program. Additional information and methods have to be used in order to reach better code compaction. Also, more sophisticated code optimization and register allocation support better code compaction. In this paper, evolutionary algorithms are used as dynamic heuristics in code generation, which allows dynamic adaption to the given input program and target processor configuration. Three evolutionary algorithms for operation merging, instruction scheduling, and register allocation are presented and evaluated on an exemplary image processing application, which shows different processing characteristics in the subroutines. They outperform code generation based on static heuristics and allow compilation for restricted target architectures that cannot be handled by the static heuristics.

Microcode update mechanism have been widely used in modern processors. Due to the implementation details are not public, researchers are prevented from gaining any sort of further understanding currently. The microcode update binary which uploaded into Central Processing Unit (CPU) is the only accessible node in this update chain by researchers, but previous manual reverse analysis for a small amount of microcode updates has the disadvantages of incomplete coverage, slow speed, and low accuracy. Therefore, we first build a Sample Repository containing 504 Intel official microcode updates, then propose a semiautomatic analytical method named SJNW-MA to analyze samples. This work has the following merits: (1) automatic methods of similarity analysis and candidate feature mining improve the speed; (2) manual-assisted analysis based on expert knowledge can filter important features, to avoid redundant features or valuable common data blocks missing; (3) analysis for 504 microcode updates make the results of reverse engineering are more complete. Finally, we extract eleven structures of Intel microcode updates and group them into four categories. In addition, we also identify and describe some new metadata in microcode updates of the third and the fourth category, including a new 3072-bit RSA Modulus as well as corresponding RSA Exponent which indicates upgrade of security technology inside update mechanism.

Firmware refers to device read-only resident code which includes microcode and macro-instruction-level routines. For Internet-of-Things (IoT) devices without an operating system, firmware includes all the necessary instructions on how such embedded systems operate and communicate. Thus, firmware updates are essential parts of device functionality. They provide the ability to patch vulnerabilities, address operational issues, and improve device reliability and performance during the lifetime of the system. This process, however, is often exploited by attackers in order to inject malicious firmware code into the embedded device. In this article, we present a framework for secure firmware updates on embedded systems. This approach is based on hardware primitives and cryptographic modules, and it can be deployed in environments where communication channels might be insecure. The implementation of the framework is flexible, as it can be adapted in regards to the IoT device’s available hardware resources and constraints. Our security analysis shows that our framework is resilient to a variety of attack vectors. The experimental setup demonstrates the feasibility of the approach. By implementing a variety of test cases on FPGA, we demonstrate the adaptability and performance of the framework. Experiments indicate that the update procedure for a 1183-kB firmware image could be achieved, in a secure manner, under 1.73 seconds.

To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class computing unit. This paper focuses on the Hardware Kernel and mainly its microcode control unit, which will leverage the elasticity to naturally evolve with Linux OS through key differentiating capabilities of field programmable gate arrays (FPGAs) when compared to the state of the art. To comply with the evolutive nature of Linux OS, or any Hardware Task incremental features, the proposed model generates page-faults signaling runtime errors that are handled at the kernel level as part of the virtual file system runtime. To evaluate the accelerator model’s programmability and its performance, a client-side application based on the AES 128-bit algorithm was implemented. Experiments demonstrate a flexible design approach in terms of hardware and software reconfiguration and significant performance increases consistent with rising processing demands or clock design frequencies., This work has been supported by FCT-Fundação para a Ciência e Tecnologia within the R&D Units Project Scope: UIDB/00319/2020.

Embedded memory is the most common circuitry in all System on Chip (SoC). It is also a critical circuit that is difficult to be tested effectively and efficiently by using external testing equipment, therefore the testing cost is expensive. Memory Built-in Self Test (MBIST) which is a self-test circuit added to the memory under test is the solution for effective and efficient embedded memory testing. Area overhead and test time are the concern in the memory testing with MBIST. There are many MBIST architectures available such as microcode-based, FSM-Based and Counter-based. Each of the architectures has its own pros and cons. The microcode-based MBIST requires a longer test time and consumes a large area. Above all, FSM-Based MBIST has better area overhead as compare with Microcode-based but it is less flexible. Counter-based MBIST has low area overhead with trade off of less flexibility. The MBIST is exercising based on the testing algorithms such as March algorithms. However, existing March algorithms are of the minimal length on the respective fault. In this paper, a new March-based testing algorithm is proposed, called March (5n) which is using the address for generating data pattern provide an alternative form of March based algorithm and it is implemented with an FSM-Based MBIST that consists of a March (5n) controller, an address generator, a data generator, and a memory interface. It is found that the proposed March (5n) testing algorithm can provide higher fault coverage than conventional MATS+ and test time 1.2 times faster than conventional MATS++ testing algorithms.

We describe an efficient system for ensuring code integrity of an operating system (OS), both its own code and application code. The proposed system can protect from an attacker who has full control over the OS kernel. An evaluation of the system's performance suggests the induced overhead is negligible. peerReviewed

Infrared scene projectors based on superlattice light emitting diodes (SLEDs) have evolved rapidly over the past decade. Much of this development has been enabled by the design of a flexible support system for driving the SLEDs. This paper describes the system and its benefits.

Modern instruction set decoders feature translation of native instructions into internal micro-ops to simplify the CPU design and improve instruction-level parallelism. However, this translation is static in most known instances. This paper proposes context-sensitive decoding, a technique that enables customization of the micro-op translation based on the current execution context and/or preset hardware events. Further, it can transition between different translation modes rapidly. While there are many potential applications, this paper demonstrates its effectiveness with two use cases: 1) as a novel security defense to thwart instruction/data cache-based side-channel attacks; and 2) as a power management technique that performs selective devectorization to enable efficient unit-level power gating.

Microcontrollers constitute a popular technology of our age. While a few decades ago, it seemed extremely difficult to teach non-electronic engineers how to program a single-chip computer system, nowadays, inexperienced designers share microcontroller-based prototypes over the Internet. The emergence of today’s do-it-yourself (DIY) culture has introduced pervasiveness of this technology and rendered the development of embedded computing systems easier than ever before. This communication identifies two fundamental eras in the advancement of microcontroller programming and application development, and distinguishes the ‘back then’ with ‘nowadays’ trends and consequent risks in education. Then, attention is paid to the classification and progress in educational research over a span of twenty years, along with a prediction of the prospective direction in microcontroller education in the upcoming decade. In this paper, in the recognition of the growing interdisciplinary nature of microcontroller technology, the information summarized could serve as a reference guide for further research study in diverse disciplines.

The Internet of Things (IoT) and the Internet of Everything (IoE) have driven processors into nearly every powered device, from thermostats to refrigerators to light bulbs. From a security perspective, the IoT and IoE create a new layer of signals and systems that can provide insight into the internal operations of a device via analog side channels. Our research focuses on leveraging these analog side channels in IoT/IoE processors to detect intrusions. Our goal is to defend against cyberattacks that insert malware into IoT devices by detecting deviations in the code running on their processors from known firmware. Our approach applies signal processing and machine-learning techniques to collected radio-frequency (RF) emissions of code running on the processor.

Configure communication equipment is a critical task that typically requires handling advanced concepts aimed at managing and troubleshooting networking issues, thus demanding high analytical and problem-solving skills to ICT technicians. To reduce this gap, this paper presents a portable hardware and software solution devoted to unify the administration of operating systems, configuration files and network services in communication devices. This includes the automatic recovery of firmware under failure conditions concerning the loss of boot image, corruption of Flash memory and forgotten passwords, among others. The prototype, mainly tested on routers and switches from Cisco and MikroTik, can be also applied to other equipment such as APs, firewalls or embedded devices since it looks for universality and independence from devices and manufacturers. As advantage, this facilitates the easy maintenance and quick deployment of network infrastructures, thus saving cost and time to engineers. So the xperimentation carried out shows the significant advantage concerning the time taken to perform some automated functions rather than running manually. This stands for a powerful tool that, as a result, has been successfully patented and extended through an international cooperation treaty (PCT)

Multiple cell upsets (MCU) is an issue that has to be dealt with when designing electronics for working in a radiated environment. Furthermore, the constant evolution of ICs integration density causes an increment in the MCUs span. These issues are typical in aviation applications, where, additionally, fault-tolerant (FT) performance is required. FT systems are typically based on a redundancy concept for storing and retrieving healthy information, for example, with a triple modular redundancy (TMR) scheme. The main issue with redundancy is design oversizing. On the other hand, reconfiguration-based techniques allow error scrubbing with a limited overhead. The main drawback here is overhead vulnerability to radiation, which is invalid for FT requirements. This paper proposes a new hybrid architecture that takes advantage of the optimized performance of reconfiguration-based techniques supported on extremely compressed redundant information nonvulnerable to radiation, referred to in this paper as hardwired seed bits (HSB). It also includes different known techniques, such as interleaving, error detection and correction (EDAC) algorithms, etc., for optimizing the final architecture as much as possible. As a result, the proposed approach meets FT requirements thanks to nonvulnerable tiny redundant information combined with an optimized performance through EDAC-based implementation.

Control firmware in unmanned aircraft systems (UAS) manage the subsystems for in-flight dynamics, navigation and aircraft sensors. Computer systems on-board the aircraft and on gateway machines can now support rich features in the control firmware, such as GPS-driven waypoint missions and autonomy. However, the source code behind control firmware can harbor software bugs whose symptoms are detectable only during flight. Often, software bugs in UAS have serious symptoms that lead to dangerous situations. We studied previously reported bugs in the open-source repositories of ArduPilot and PX4, two widely used control firmware for UAS, and characterized their root causes, severity and position in the firmware architecture. Even though both platforms have employed rigorous software engineering practices, bugs were common and often had severe symptoms (e.g., crashes.) In particular, bugs associated with mishandling aircraft sensor readings were the leading cause for bug-induced crashes. Finally, we used simulation to study the symptoms of sensor bugs and found that source code repositories under reported their frequency and impact. Our study motivates multiple research directions on software reliability in UAS firmware.

This paper presents the development and implementation of a variant of the manual flight mode, the Cartesian mode, which consists of the directional control of a multi-rotor UAV w.r.t. its heading and pilot's heading. The main objective of the presented flight mode is to ease the manual displacement control while the pilot has a ground Point of View (POV). The flight mode's concept is implemented in the PX4 firmware under Software-in-the-Loop (SITL) simulations and real flights to assess its performance applied to a real quad-rotor. The results obtained during simulations and real experiments show that the flight mode performs correctly.

We are accustomed to thinking of computers as fail-stop, especially the cores that execute instructions, and most system software implicitly relies on that assumption. During most of the VLSI era, processors that passed manufacturing tests and were operated within specifications have insulated us from this fiction. As fabrication pushes towards smaller feature sizes and more elaborate computational structures, and as increasingly specialized instruction-silicon pairings are introduced to improve performance, we have observed ephemeral computational errors that were not detected during manufacturing tests. These defects cannot always be mitigated by techniques such as microcode updates, and may be correlated to specific components within the processor, allowing small code changes to effect large shifts in reliability. Worse, these failures are often "silent" - the only symptom is an erroneous computation. We refer to a core that develops such behavior as "mercurial." Mercurial cores are extremely rare, but in a large fleet of servers we can observe the disruption they cause, often enough to see them as a distinct problem - one that will require collaboration between hardware designers, processor vendors, and systems software architects. This paper is a call-to-action for a new focus in systems research; we speculate about several software-based approaches to mercurial cores, ranging from better detection and isolating mechanisms, to methods for tolerating the silent data corruption they cause.

Incremental reprogramming is one of the key features for managing resource-constrained IoT devices. Nevertheless, existing approaches fall flat in RAM and flask usage due to the increasing firmware size of contemporary IoT applications. In this paper, we advocate S2, a differencing algorithm for reprogramming resource-constrained IoT devices. S2 achieves small memory and flash footprints by leveraging a topological sort based in-place reconstruction mechanism and stream reconstruction technique, as well as smaller delta size by a prediction-based encoding. Evaluation shows that S2 uses 33.3% less RAM while reducing at most 42.5% delta size than state-of-the-arts.

Creating an application-specific processor is an effective and popular way to solve many problems in embedded hardware design using FPGAs, ASICs, or custom silicon. Programming these processors is complicated by the lack of toolchain support for creating the necessary binary code as part of hardware design, implementation, and evaluation. Hardware developers who cannot create their own ad-hoc assembler are left to hand-assemble their code into binary instructions which is both painful and error prone. We present a tool that supports the rapid creation of assemblers for application-specific processors. A single language is used to specify both instruction formats as collections of bit fields and the instantiation of those formats into sequences of binary instructions as a single, homogeneous activity that is designed to be as familiar and accessible to hardware designers as possible. The output from the tool can be used directly by hardware synthesis tools to initialise the program memory of an application-specific processor.

Through the Internet of Things (IoT) increasingly growing, questions concerning the security of IoT gadgets have become evident. A couple of sellers build IP-associated gadgets for residence and little office arrangements that frequently experience the ill effects of inadequate security plans and executions. They additionally tend to need instruments for firmware informs or fixes that be able to help security of dispose the vulnerabilities. Making sure about systems where the proximity of these helpless gadgets is known requires a brown field advance: applying fundamental security measures inside the system with the intention of potentially powerlessness. Gadgets should live together in the same device without jeopardizing the protection of the various gadgets. Now, IOT SENTINEL is a platform able of separating the category of gadgets associated with an IoT. To allow laws to force the correspondence of helpless gadgets in order to minimize the harm caused by their off trade. It is appear that IOT SENTINEL is feasible in recognize gadget forms and has marginal transparency execution.

Channel state information (CSI)-based fingerprint approach for WiFi-based indoor localization has attracted a lot of attention recently. The fine-grained CSI represents the location-dependent channel characteristics more effectively than the coarse-grained received signal strength indicator (RSSI). However, the CSI fingerprints can deviate drastically with environmental variations. Consequently, the CSI-based fingerprint positioning models need to be adapted for different environments and/or updated over time, which is time-consuming and labor-intensive in practice. In this paper, an environment-adaptive positioning system is proposed to transfer the fingerprint features that significantly reduce reconstructing the fingerprint database. A CSI extraction platform is developed based on the modified OpenWrt firmware, enabling access to CSI measurements on commodity WiFi devices. To transfer the fingerprint features, a domain adaptation approach is proposed to reconstruct the CSI fingerprint database from the existing fingerprints with a limited number of new measurements. Experiments are conducted in several real-world test sites, including the laboratory and the lounge, with environmental change. The results show that the performance of the proposed system is promising in terms of localization accuracy and adaptation efficiency.

This article is about the process of creating a custom corporate android ROM which can be safely used in the company and placed near the main phone’s ROM. It focuses on the custom ROMs and ways to protect information on the smartphone. The existing security methods were studied. This paper also discusses android’s boot process and ways of changing it. During the research, several shell scripts were made and third-party open-source implementations were used to achieve the research goal. The result of the research is a fully working ROM based on AOSP which provides solutions for protecting data in the device’s memory from being read by third parties. The ways of installing it into the device are considered as well. Also, this article includes a comparison of some stock and corporate ROM’s characteristics such as average operating time, average boot time, and average temperature.

In recent years, Internet of things security incidents occur frequently, which has threatened the stability of the country, society and personal privacy. As the core of Internet of things equipment system, the security of firmware is very important. In order to design a more reasonable and effective firmware security detection method, the firmware needs to be analyzed in detail. This paper describes the security objectives of firmware from three aspects of confidentiality, integrity and availability, summarizes and analyzes the firmware attack surface, and carries out relevant verification experiments for each attack surface. In order to solve the tedious steps of firmware format identification, unpacking and key information extraction in the process of large-scale firmware security analysis, a firmware security analysis tool is designed and implemented, and large-scale experimental analysis of firmware is carried out from the perspectives of open-source components, weak passwords and hard coding.

An ATMEL AVR ICSP programmer is considered an important device for who uses ATMEL AVR microcontrollers. Legacy programmer devices require wired connection to a PC via USB cable. This technique forces a user to place the target microcontroller close enough to a PC. Modernized systems and applications require wireless communications via many technologies, such as Wi-Fi and ZigBee. Systems that are inaccessible or installed in dangerous zones require a remote communication technique for firmware upgrading. Unfortunately, the current devices do not support remote firmware upgrading. Therefore, it resembles a critical problem for many factories. In this research paper, we will introduce a new device for programming all ATMEL AVR microcontrollers remotely via Wi-Fi and ZigBee. Also, we will provide two experimental works to prove our device's new architecture concept alongside with deploying it in real life use cases, such as Massive Deployment.

Recent researches have implemented a lot of IoT. The problem that is often faced is IoT end devices are still not user friendly in its configuration. There are still many device configurations are located at firmware level and only developers have access to firmware level and configure it. The user is still confused in configuring IoT end device. This researches proposes to apply pairing to IoT end devices. Pairing has been used by several IoT end device that are already on the market but can still be developed. Therefore, researches have been directed to designing a system that makes pairing IoT end devices easier. So that the configuration is not done at firmware level but at the application level. Users can pair an Android smartphone with an IoT end device and configure such as choosing Access Point in application. Application use proximity authentication, where pairing authentication is obtained by analyzing movements that affect RSSI variation. In addition, the system also implements dynamic device pairing to make pairing easier by viewing connection history. For determining the connection between an Android smartphone and an IoT end device, a Decision Tree is used. By using these systems and methods, the accuracy obtained is 92.19%.

Spin Torque Transfer Magneto-resistive Random-Access Memory (STT-MRAM) is a type of non-volatile memory that stores data in magnetic domains. It is a very interesting market space that STT-MRAM will support, trying to take the best of both worlds, the ever fast paced DRAM with scaling challenges and the non-volatile world of Flash with latency challenges. Initial setup, bring-up and endurance characterization of the STT-MRAM device are summarized. An overview of the tester-board design, along with the endurance characterization methodology and test results are discussed. Learning shared to introduce and educate about STT-MRAM bring-up and help future system designs using STT-MRAM. STT-MRAM is not as scalable as DRAM or Flash but has high potential based on its performance and persistence characteristics.

As medical devices become more digitalised, failures in those systems can no longer go uninvestigated. Current medical device failure are typically diagnosed through procedures relating to specific problems related to the physical operation of the device. Technologies such as trusted computing offer an additional layer of hardware and software resiliance and security and come with a potential vast array of diagnostic and forensic information in case of failure. The traditional methods of fault diagnosis will never catch firmware and software based attacks and even leave said devices in a vulnerable state even after repair. Utilising trusted computing forensics offers an opportunity to add security related diagnosis and protect the functionality of these devices.

BOOTROM is the piece of code that is hardcoded into the ROM mask of the device during manufacturing. This code is responsible for the booting of the device and to download final customer applications. This downloading and booting can be possible through multiple ways, i.e. serial download through LIN [1], UART [2], ENET interface, flash booting, SD card booting etc. As BOOT ROM code is the critical piece of firmware, so its validation becomes imp erative. As this code goes on ROM mask, so any failure detected on silicon will result in re-spin of the device, so it is must to have a robust testing of this firmware in the pre-silicon environment. In this paper, we will touch upon, one of the booting modes (Serial boot) testing in a pre-silicon environment (or framework). We will discuss the challenges and techniques to overcome them.

With the increasing popularity of the Internet of Things (IoT), security issues in this domain have become a major concern in recent years. In favor of a fast time to market and low cost, security is often neglected during IoT development and little effort has been spent to enhance security tools to support the most common IoT architectures. Therefore, this work investigates fuzzing, an emerging security analysis technique, on the popular ESP32 IoT architecture. Instead of performing fuzzing directly on the target IoT system, we propose a full-system emulator that runs ESP32 firmware images and is able to perform fuzzing several orders of magnitude faster than the actual system. Using this emulator, we were able to fuzz a commercial IoT device with more than 300 requests per second and identify a bug in it within a few minutes. The developed framework can not only be used for discovering security issues in released products, but also for automated fuzzing tests during development.

LoRa WAn is one of the LPWAN technologies that has become popular in both industries and research. LoRaWAN aims to provide long-range communication and empowers low-powered devices to last for years in the field. LoRaWAN relies on the symmetric cryptography to provide end-to-end encryption. Even though LoRaWAN relies on symmetric cryptography, there are recent works that try to enhance security of LoRaWAN by incorporating technologies like Blockchain. Blockchain is a decentralized peer-to-peer network that provides tamperproof and immutability of data. This paper proposes a Blockchain-based firmware update mechanism to enhance firmware update in LoRaWAN as well as managing the update process. This mechanism aims to provide updates by ensuring authenticity, and integrity of the firmware. The mechanism focuses more on devices that are too constrained in resources, hence for that purpose we evaluated the cost involved in some cryptographic operations taken to ensure security during firmware updates. We conclude that the approach is feasible for constrained devices in LoRaWAN network by evaluating the memory usage of the cryptographic operation used by the end device.

This article presents the design and development of a relay switch (RS) to handle electrical loads up to 20A using WiFi technology. The hardware design and the implementation methodology are explained, both for the power supply and for the wireless communication that are embedded in the same small printed circuit board. In the same way, the design of the implemented firmware to operate the developed RS is shown. An ESP-12E module is used to achieve wireless communication of the RS, which can be manipulated through a web page using an MQTT protocol or via and iOS or Arduino app. The developed RS presents at least three differentiators in relation to other similar devices on the market: it can handle a higher electrical load, has a design in accordance with national and international security standards and can use different cybersecurity strategies for wireless communication with the purpose of safe and reliable use. Experimental results using a lamp and a single-phase motor as electrical loads demonstrate an excellent performance and reliability of the developed relay switch.

Safety, security and virtualization is getting important to enable multiple use cases in automotive and industrial market for efficient use of hardware resources. The high performance computer vision, imaging, deep learning functions are accelerated using dedicated hardware accelerators for power and performance reasons. The typical single threaded design of these HW accelerators poses challenges in sharing in mixed safety critical, secure and virtualized environments. This paper presents a flexible and efficient sharing scheme for these environments without modifying the underlying HW accelerators. The proposed solution consists of a programmable MCU and additional HW wrappers to enable isolation for safety, security and virtualization. The solution uses novel techniques namely, trusted and sand-boxed message exchange, dynamic master ID generator, and intelligent firmware to shared multiple HW accelerators using a single MCU. The proposed solution is realized in TI Jaincto 7 SoC. The prototype shows < 1% degradation on HW accelerator performance. Further, the scheme is flexible enough to support multiple HW accelerators like multimedia, imaging, video and deep learning.

Information level protection standard 2.0 requires trusted verification of system bootstrappers, system programs, etc. of server equipment based on trusted root. According to the requirements of information level protection standard, this paper puts forward a network trusted start-up scheme based on the trusted platform control module to guarantee the security and trust of the server's BIOS firmware, PXE boot file and Linux system file. When publishing BIOS firmware, PXE startup file, Linux system file, the state-secret algorithm SM3 is used to calculate the summary value as the benchmark value, and stored in the trusted platform control module, BIOS firmware, Linux boot file. When the server starts up with PXE, the BIOS firmware is measured by the Trusted Platform Control Module, the BIOS Start Environment Measures PXE Boot File, and the PXE Boot File measures the Linux system file. The trusted platform control module is the trust root level measurement level, the first level of trust level, the trust chain, the implementation of a trusted server operating environment. The method proposed in this paper is tested on the domestic autonomous controllable Sunway server, and the experimental results show that the method proposed in this paper is feasible.

Compromised power electronics, due to firmware attacks and hardware Trojans, in a flight computer can jeopardize the safety and security of an Unmanned Aerial Vehicle (UAV). They can maliciously alter sensor measurements or control commands to make a UAV to take disastrous moves. Unfortunately, most of these attacks are difficult to detect before deploying components in the system. Therefore, detecting compromised behavior run-time is important, while it is challenging at the same time. In this work, we propose to build machine learning-based intrusion detection systems (IDSs) to be deployed at the power electronics/microcontorller level such that it can deal with malicious data/control commands initiated due to hardware attacks.

In this paper, a concept for building equipment of unmanned aerial vehicles (UAV) mission control is proposed from a point of safety to provide coordination with regulatory authorities regarding law restrictions. The concept involves the use of flight maps containing information about the flight and restrictions on the cargo carried and flight modes. The flight map is recorded in the memory of the microcontroller or SIM-card and is encrypted by the security algorithm. The flight map embedded on microcontroller or card is installed in the UAV without the possibility of manual control. The read-only flight map provides UAV flight on a given route with given flight mode and cargo. In case of emergency, the flight map provides safe landing points. The concept is implemented using a DJI Phantom 2 Vision+ and a PIC32 microcontroller on the UART port. Simulation modeling of the proposed concept showed that one can be used since the speed and capabilities of the equipment are sufficient for the safe flight of the UAV.