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Since large array devices of MOSFETs are huge for driving capabilities, ESD self protections are also required. Then, the large drain-contact-to-poly-gate-spacing layout rule is usually adopted with large layout areas. In this paper, a new control circuit is implemented for adopting the minimum device layout rule in the LAD. Hence, it results in a very small layout area and ESD self-protection capabilities can be established.

CMOS-technology scaling has moved to a power-constrained condition regardless of the application segments. Power management in advanced CMOS technology drives the need to conciliate scaling-driven fundamental material limitations with product and application evolution requirements. Flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip. This paper reviews issues associated with transistor scaling and co-optimization for power-management circuit-design schemes for active-and leakage-power control. This paper also addresses the derived trends and implications on I/O and analog-transistor scaling.

A new high voltage tolerant (HVT) electro-static discharge (ESD) design adopts one forward biased P+/N-well diode in series of one stacked NMOS, called the diode-stacked NMOS, is proposed to reduce the total capacitance and maintain the high ESD performance. The device has been implemented in 0.18 μm CMOS logic technologies and finds the measured human body model and machine-model ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.

Several physical phenomena in highly scaled CMOS technology have now become first-order elements affecting the electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others can have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.

The scanning capacitance microscope (SCM) is a carrier-sensitive imaging tool based upon the well-known scanning-probe microscope (SPM). As reported in Edwards et al. [Appl. Phys. Lett. 72, 698 (1998)], scanning capacitance spectroscopy (SCS) is a new data-taking method employing an SCM. SCS produces a two-dimensional map of the electrical pn junctions in a Si device and also provides an estimate of the depletion width. In this article, we report a series of microelectronics applications of SCS in which we image submicron transistors, Si bipolar transistors, and shallow-trench isolation structures. We describe two failure-analysis applications involving submicron transistors and shallow-trench isolation. We show a process-development application in which SCS provides microscopic evidence of the physical origins of the narrow-emitter effect in Si bipolar transistors. We image the depletion width in a Si bipolar transistor to explain an electric field-induced hot-carrier reliability failure. We show two sample geometries that can be used to examine different device properties.

We examine two assumptions commonly used in analytical studies of inverter transient performances, that the transcapacitive current during a transient and the distributive gate resistance are negligible. We derive the additional delay time expressions which need to be added to the delay times calculated with such assumptions. In addition, we propose an equivalent lumped transistor which accurately models the transient behavior of the transistor with a distributive gate resistance.

The design and optimization of ESD protection circuits is greatly enhanced by the ability to perform circuit-level simulations of the protection circuits and the I/O buffers. Most available simulators do not cover the high current region of the circuit operation, but still enable an approximate analysis to be made of the behaviour under ESD conditions. In this article, a description of the behaviour of the MOS device in the high current regime is presented together with the model equations governing that behaviour. The equations have been implemented into a SPICE circuit simulator, and the experimental and simulation results are given. A simple parameter extraction methodology is presented that uses the terminal currents from a single MOS DC I-V curve to obtain all the MOS and bipolar parameters required for the model.

Investigates the effects of self-heating on the high current I-V characteristics of semiconductor structures using a fully coupled electrothermal device simulator. It is shown that the breakdown in both resistors and diodes is caused by conductivity modulation due to minority carrier generation. In isothermal simulations with T=300 K, avalanche generation is the source of minority carriers. In simulations with self-heating, both avalanche and thermal generation of minority carriers can contribute to the breakdown mechanism. The voltage and current at breakdown are dependent on the structure of the device and the doping concentration in the region with lower doping. For all structures, except highly doped resistors with poor heating sinking at the contacts, the temperature at thermal breakdown ranged from 1.25T/sub i/ to 3T/sub i/, where T/sub i/ is the temperature at which the semiconductor goes intrinsic. Hence, it is found that T=T/sub i/ is not a general condition for thermal (or second) breakdown. From these studies, an improved condition for thermal breakdown is proposed. >

A novel low-leakage diode string design using separate diode objects in 0.18 m CMOS processes is proposed in this paper. Diode strings can be divided into two (or three) groups with only a large shallow trench isolation (STI) used as spacing. With STI used to separate the groups, the diode string successfully prevents excessive current leakage. The turn-on voltage of the diode string can be derived from the equations concluded from the experiments.

To conciliate scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization including dynamic body/well bias, gate dielectric scaling, mobility enhancement by strained-Si, SRAM process and design interactions, digital and analog device tradeoffs, and HV I/O considerations in advanced CMOS technologies.

Transmission line pulse (TLP) measurements have been shown to correlate well with ESD performance in most cases. However, some recent researches suggested in some cases miscorrelation can happen. A test chip was designed and fabricated in TSMC 0.13 /spl mu/m technology to test this correlation. We found that in some conditions, TLP measurements (IT2) do not correlate well with ESD testing in both human body and machine models.

We present a design methodology for I/O cell library design automation. It's different from the conventional cell library compilers or generators, which generate the cells for standard cells or regular structures (e.g., SRAM). The proposed compiler generates I/O cells based on a set of parameterized unit-cells with the features of scalable geometry dependence. The compilation results of the I/O cells have been proved in a 0.13 /spl mu/m LOGIC IP8M process. Through this compiler, the number of unit-cells needed to be maintained is dramatically reduced, thereby reducing library development costs and time to market.

In this paper, the weak erase failure mechanism of a source side injected split gate flash memory after endurance (ENDU) cycling test has been identified through a 2T cell structure. In general, charge trapping in the inter poly oxide (IPO) after Fowler Nordheim tunneling erase is considered to dominate the weak erase failure. However from this study, it is found that cell current reduction after erase is not due to erase-induced tunneling oxide degradation. On the contrary, program-induced electron trapping in the coupling oxide dominates the cell current reduction after long term endurance cycling stress.

To reconcile scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize Systems on a Chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization, gate dielectric scaling, strain-Si enhancement and I/O support.

A new high voltage tolerant (HVT) ESD design adopts one forward biased P+/N-well diode in series of one stacked NMOS to reduce the total capacitance and maintain the high ESD performance is proposed and implemented by 0.18 /spl mu/m CMOS technologies. The measured HBM and MM ESD levels of the HVT pin exceed 6 kV and 550 V, respectively, while the measured input capacitance is only 250 fF.

A parallel circuit simulator, iPRIDE, which uses a direct solution method and runs on a shared-memory multiprocessor is described. The simulator is based on a multilevel node tearing approach which produces a nested bordered-block-diagonal (BBD) form of the circuit equation matrix. The parallel solution of the nested BBD matrix is described. Its efficiency is shown to depend on how the circuit is partitioned as well as the sequence in which the concurrent tasks (scheduling) are solved. A partitioning heuristic is proposed, assuming that an arbitrary number of processors is available. Scheduling methods are studied when the number of processors is fixed. A method for determining the optimal level of partitioning, which depends on the number of processors as well as the scheduling methods, is described. The program is implemented on an ALLIANT FX/8 multiprocessor with shared memory. The performance of the program is reported. >

The problems of prematured snapback and false multiple breakdown are found in simulating semiconductor devices in the high temperature region. The only way to achieve accurate and efficient electrothermal simulation under these conditions is by adaptive regridding. An adaptive regridding algorithm that approaches the optimal efficiency by applying the equidistribution of local truncation error is developed. With this algorithm both problems are overcome. In addition, both simulation accuracy and efficiency are improved by at least a factor of two. >

We propose a novel non-quasi-static model for long-channel MOSFETs which removes the known problems with existing models, such as zero base current and bump features. In a fast switching case, this model reduces the r.m.s. error of I/sub s/, I/sub d/, I/sub g/, I/sub b/ from 22%, 136%, 85%, 100% for BSIM3 and 24%, 77%, 32%, 34% for the Turchetti model down to only 2.1%, 12%, 3.6% and 7.8%, respectively.

Low temperature aluminum plug fill schemes such as CVD Al and high pressure ForceFill/sup TM/ Al offer significant advantages in terms of lower via resistance and compatibility with low-k polymer dielectrics. The low processing temperature is desirable for advanced high performance sub-half micron interconnects with polymeric dielectrics. While the CVD Al process enables sub-300/spl deg/C plug processing, the ForceFill/sup TM/ process has also been shown to of relatively low temperature (400/spl deg/C). An embedded dielectric scheme is particularly attractive for integrating polymeric materials as this structure offers improved structural stability and alleviates many of the difficulties associated with via process integration. In this paper we present a comparison of CVD Al and ForceFill/sup TM/ Al for double level metal structures using embedded low-k dielectrics such as Parylene (N) (k=2.7) and Hydrogen Silsesquioxane (HSQ). Integration of Al and Parylene is shown to provide significant performance advantage for metal RC delay.

The new embedded polymer structure combines the advantages of SiO/sub 2/ and low dielectric constant of polymeric materials. The interconnect performance is improved through line-to-line capacitance reduction by utilizing polymer only between tightly spaced lines. Double-level-metal interconnect structures have been successfully fabricated using a variety of low-dielectric-constant insulators. The new multilevel interconnect scheme alleviates many of the integration and reliability problems associated with polymers, and can be easily adopted to standard production process. >

A r.f. MOSFET model generated for use in LIBRA simulation typically applies to only one bias point. The model and its parameters can be unphysical. It is desirable to establish a physical, scalable model capable of simulating both d.c. and r.f. characteristics and applicable to all the bias ranges. BSIM3 is a potential candidate, having demonstrated accuracy and scalability in the devices' d.c. characteristics. When it is applied to simulate the s-parameters at r.f., we find BSIM3 to be somewhat problematic and two modifications are necessary to obtain a good fit. The first modification involves the addition of a bulk resistive network, achievable with a simple circuit extension to the existing BSIM3 model. The second improvement accounts for the finite channel resistance, whose origin lies in a nonquasi-static analysis. Since BSIM3 employs a quasi-static assumption, this improvement, while important, involves some changes in the BSIM3 source code.

We have developed a new unified substrate current model for weak and strong impact-ionization. The model which is semi-empirical is able to capture non-local field effects. The importance of this model is its simplicity requiring three parameters which can be extracted easily from a single wafer-level measurement. The implementation of this model in a circuit simulator provides the capability to include hot-carrier and ESD effects into circuit design optimization, which is essential for achieving design-in-reliability targets.

As device geometries and operating voltage continue to decrease while functional density increases, it is imperative to reduce the RC time delay. The new embedded polymer structures improves the interconnect performance through line-to-line capacitance reduction by using polymer only between tightly spaced lines. The gapfill polymeric materials do not degrade the electromigration performance of standard multilayered TiN-Al-TiN interconnects. This scheme alleviates many of the integration and reliability problems associated with polymers, and can be easily adopted into a standard production process.

Hydrogen silsesquioxane (HSQ) is a low density material for intra-metal gapfill, that offers low permittivity for interconnect capacitance reduction. Films with k as low as /spl sim/2.2 preferentially form between tightly-spaced metal leads when cured at low temperature (

The evaluation of 'future' SRAM designs often involves aggressive patterning techniques. This is especially true for the prototyping stage of a product because the target 'production' tools are either unavailable or suffer from immature processes. This paper describes an OPC implementation method for 0.18 micrometers technology production of small SRAM cells of logic gate levels. A model based proximity correction has been applied to compensate the pattern distortions encountered in DUV lithography patterning. The first step is to generate a process specific empirical model for OPC simulation. To judge the accuracy of the OPC model, a set of linewidth measurements including linewidth versus pitches and linewidth versus linearity could be used to do a model prediction verification. However, linewidth confirmation is only in 1D. A 2D confirmation is important to ensure the success of OPC because there are lots of irregularly shaped layouts in a random logic device. The validity of OPC model prediction also needs to be verified for low contrast areas in patterning using focus exposure matrices by comparing the printed result to the model simulation. This procedure is very important in pushing chip density. Some experimental result from our approaches are discussed in this paper.

Most two-dimensional (2D) dopant characterization techniques deal with near surface carrier concentration or surface potential measurements using a device cross-section. Thus, a reproducible and well-characterized surface condition is essential for accurate measurements. We report on an X-ray photoelectron spectroscopy study of surface preparation techniques commonly used in 2D dopant characterization: (i) hydrogen termination, (ii) colloidal silica polishing, (iii) low temperature silicon oxidation. Although the presented results may be applied to any other technique, in this report we concentrate on scanning capacitance microscopy (SCM). For high quality SCM a thin, uniform, and charge-free insulating film has to be formed on top of the silicon sample. Two phenomena may have a critical impact on accuracy of SCM: (i) leakage through the insulating layer and (ii) surface charging which may cause unpredictable variations in flat-band voltage. We found that samples polished by colloidal silica have about on...

The lack of a two-dimensional (2D) dopant standard and hence a priori knowledge of dopant distribution makes it impossible to unambiguously judge accuracy of any experimental or theoretical effort to characterize silicon doping in two-dimensions. Recently a strong progress has been made in quantitative scanning capacitance microscopy (SCM), scanning spreading resistance microscopy (SSRM), secondary electron (SE) and transmission electron microscopy (TEM) doping profiling. Several research groups have claimed an ability of quantitative 2D dopant characterization. A round-robin study involving various analytical techniques and comprehensive numerical simulations should help to evaluate an accuracy of available quantitative techniques and set some helpful standard for further development. We report on a world-wide round-robin study performed on CMOS 2D test structures fabricated at Texas Instruments (TI). Seven research groups, which represent an advanced SCM, SSRM and TEM dopant profiling, participated in the study. Related process information and 1D dopant profiles measured by secondary ion mass-spectroscopy (SIMS) were released to the sites. Process simulator TSUPREM4 tuned using SIMS and inverse electrical modeling was employed to simulate 2D dopant distributions for both PMOS and NMOS test structures. Method-to-method variations in pn-junction position are noticeably higher than 10 nm, the spatial resolution requested by TCAD. The statistical scatter in pn-junction position varies from 10 to 30%. Although interpretation of the data is still a challenging problem, controlled and reproducible surface preparation is an important step, which may help to reduce the observed diversity of dopant characterization results. A round-robin study on test structure capable of electrical characterization should link round-robin results to device performance and hence is necessary.

A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

As device geometries and operating voltage continue to scale while functional density increases, it is imperative to reduce the RC time delay. The replacement of Si0 2 as an intermetal dielectric with an insulator of lower dielectric constant is a particularly attractive solution since it provides immediate performance improvement through reduction in capacitance. An embedded polymer integration scheme improves the interconnect performance through line-to-line capacitance reduction by using polymer only between tightly spaced lines. The gapfill polymeric materials do not degrade the electromigration performance of standard multilayered TiN/Al/TiN interconnects. Embedded polymers alleviate many of the integration and reliability problems associated with polymer integration, and can be easily adopted into a standard production process.

Interconnect delay is shown to be a performance-limiting factor for ULSI circuits when feature size is scaled into the deep submicron region, due to a rapid increase in interconnect resistivity and capacitance. Dielectric materials with lower values of permittivity are needed to reduce the line-to-line capacitance as metal spacing decreases. However, the challenge is to successfully integrate these materials into on-chip interconnects. A new multilevel interconnect scheme has been developed that gives improved performance through insertion of a low-dielectric-constant material between metal leads. A novel polymer/Si02 composite dielectric structure provides lower line-to-line capacitance while alleviating many of the integration and reliability problems associated with polymers in standard interconnect processing.

The use of 2D device simulations in predicting the ESD robustness of MOS devices is discussed. The merits of using the peak power density, JE, and the second breakdown trigger current, I/sub t2/, as a measure of the relative robustness of MOS devices with varying drain/source profiles, contact to gate spacing, and gate bias conditions, is studied. It is shown that the peak JE correlates with the peak temperature in the device, but it is strongly influenced by variations in the grid. Hence, its applicability is limited to comparing the relative robustness of devices with simulations where the grid does not change drastically. I/sub t2/ is less sensitive to grid variations and is more widely applicable for analyzing the effect of technology variations on ESD robustness. >