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ISBN: 9780889860650; International audience

The design of complex real-time distributed hardware/software systems commonly involves evaluating the performance of several design alternatives. Early in the design process, it is therefore desirable that design methods support constructing abstract models for the purpose of analysis. Recent extensions to the Unified Modeling Language (UML) that enable specifying schedulability, performance and time provide a means to start developing such models directly after defining the concepts and requirements of a system. However, UML hampers the evaluation of performance properties because this requires constructing executable models with a modeling language that supports application of mathematical analysis techniques. In this paper, we present how the Software/Hardware Engineering (SHE) method can be used for the performance modeling of real-time distributed hardware/software systems. Starting from a UML specification, SHE enables constructing formal executable models based on the expressive modeling language POOSL (Parallel Object-Oriented Specification Language).

Integration of increasingly complex systems on a chip augments the need of system-level methods for specification and design. In the earliest phases of the design process important design decisions can be taken on the basis of a fast exploration of the design space. This paper describes an abstract modeling approach towards system-level design-space exploration, which is formal and flexible. It uses a uniform system model that contains both functional and architectural information. Disjunct, parameterizable resources represent the real-time behavior of the target architecture. Due to the expressiveness of the modeling language (POOSL), control as well as data oriented behavior can be specified in the functional part of the system model. Well-founded design decisions can be taken as a result of performance estimations that are based on Markov theory.

International audience; This article focuses on the behavioral abstraction methods of VHDL models for the improvement of event-driven simulation performance. The model abstraction takes into account the specific simulation requirements in a particular simulation execution: the observability of the internal and external signals as well as the testbench vectors of the input signals. According to those requirements the initial model is abstracted in order to decrease its complexity in terms of the number of VHDL objects used, but also in terms of the elaborated model memory usage. The practical results of the simulation performance improvement comparing to the conventional simulation are presented.

International audience; A growing complexity of the electronic systems stimulated by the progress in the fabrication technology of integrated circuits requires a corresponding growth of the productivity of the design and verification methods. The low simulation performance is one of the obstacles preventing a delivery of high quality of products in a short time and at a low cost. This article presents four methods developed for improving the simulation performance of VHDL models: the model optimisation, the model transformation, the model reduction and the model abstraction. These methods convert an initial VHDL model into another VHDL model, functionally equivalent, which renders a better simulation performance. The results of simulation time improvement of each method are presented.

International audience; System-Level Synthesis deals with the concurrent design of electronic applications, including both hardware and software. The issue has become the bottleneck in the design of electronic systems, including both hardware and software, in several major industrial fields, including telecommunications, automotive and aerospace engineering. The major difficulty with the subject is that it demands contributions from several research fields, including system specification, system architecture, hardware design, and software design. Most existing book cover well only a few aspects of system-level synthesis. The present volume presents a comprehensive discussion of all the aspects of system-level synthesis. Each topic is covered by a contribution written by an international authority on

International audience; We are at the confluence of two powerful technology phenomena, which are opening unexpected domains of application but also incredible new challenges. The first is the nearly overwhelming complexity of Integrated Circuits. The other is networking, promising a worldwide generalized interconnection of intellects, their work and creations.

The paper binds together a collection of short presentations on hardware description languages (HDLs) developed in Europe and provides a view of the history of HDLs during the last three decades (1968-98). This historical review presents the ideas conceived in these previous languages, which are now implemented in the standard languages. Furthermore, the paper highlights those early concepts which still need to be implemented in the evolving standards or could provide a way to unify them (like VHDL, Verilog or SDL) within a formally defined multi-language environment. Among a large number of European works over 3 decades, we have selected a sample from different countries: France, Germany, UK, Italy, which have been implemented and used reliably in various segments of the industry. The selected HDLs are: CASSANDRE (1967), MIMOLA (1977), DACAPO (1977), ELLA (1979), ART (1980), and CASCADE (1981). We have tried to compare the main features of the chosen languages according to a list of criteria and briefly identify those which are still missing in the recognized worldwide standards.

International audience; This article gives a survey on formal hardware verification tools developed in Europe. It describes the main objectives and domains of application of the formal methods for the verification of electronic systems. Further, it gives an overview of the formal methods used in the most significant European research in this domain. It attempts to introduce some classification scheme for the existing commercial or prototype tools, which is based on the different verification aspects: type of the circuit to verify, abstraction level, verification objective, mathematical model, formal proof technique, input formalism, diagnostic method incorporated and the others. The most significant features of the methods and tools are summarized, and some advantages and drawbacks are discussed. Finally, some conclusions concerning the possible future trends in development are drawn.

International audience; Decreasing power dissipation per logic function has become a primary concern in virtually all CMOS system chips designed today as a result of the relentless progress in processing technology that has led us into the deep-submicron age. Evolution from 1 micron to 0.1 micron lithography in the next decade will not be possible without a change in the way we design CMOS systems. But power reduction requires an overall optimisation, ranging from software compilation over instruction set design down to the introduction of much more parallelism in the architecture, the optimal use of memory hierarchy, new clocking strategies, use of asynchronous techniques, new CMOS circuit techniques and management of leakage currents in new low power technologies. Moreover, performance and power dissipation will come to be dominated by interconnect and thus completely new floor planning and place and route strategies are emerging.The chapters in this book present a systematic coverage of deep submicron CMOS digital system design for low power, from process technology all the way up to software design and embedded software systems.Audience: An excellent guide for the practising engineer, researcher and student interested in this crucial aspect of actual CMOS design.