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There are large individual differences in how people evaluate their own memory. Although most of us tend to be quite optimistic about the power of our memory, some people believe [...], The relationship between subjective memory beliefs and suggestibility, compliance, false memories, and objective memory performance was studied in a community sample of young and middle-aged people (N = 142). We hypothesized that people with subjective memory problems would exhibit higher suggestibility and compliance levels and would be more susceptible to false recollections than those who are optimistic about their memory. In addition, we expected a discrepancy between subjective memory judgments and objective memory performance. We found that subjective memory judgments correlated significantly with compliance, with more negative memory judgments accompanying higher levels of compliance. Contrary to our expectation, subjective memory problems did not correlate with suggestibility or false recollections. Furthermore, participants were accurate in estimating their objective memory performance.

We present a unified mathematical framework for analyzing the tradeoffs between parallelism and storage allocation within a parallelizing compiler. Using this framework, we show how to find a good storage mapping for a given schedule, a good schedule for a given storage mapping, and a good storage mapping that is valid for all legal (one-dimensional affine) schedules. We consider storage mappings that collapse one dimension of a multidimensional array, and programs that are in a single assignment form and accept a one-dimensional affine schedule. Our method combines affine scheduling techniques with occupancy vector analysis and incorporates general affine dependences across statements and loop nests. We formulate the constraints imposed by the data dependences and storage mappings as a set of linear inequalities, and apply numerical programming techniques to solve for the shortest occupancy vector. We consider our method to be a first step towards automating a procedure that finds the optimal tradeoff between parallelism and storage space. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors--compilation; optimization; memory management General Terms: Languages Additional Key Words and Phrases: Automatic parallelization, affine scheduling, storage optimization, occupancy vectors, polyhedral model, affine recurrence equations ACM Reference Format: DOI = 10.1145/1286821.1286825 http://doi.acm.org/10.1145/1286821.1286825

With the diverging improvements in CPU speeds and memory access latencies, detecting and removing memory access bottlenecks becomes increasingly important. In this work we present METRIC, a software framework for isolating and understanding such bottlenecks using partial access traces. METRIC extracts access traces from executing programs without special compiler or linker support. We make four primary contributions. First, we present a framework for extracting partial access traces based on dynamic binary rewriting of the executing application. Second, we introduce a novel algorithm for compressing these traces. The algorithm generates constant space representations for regular accesses occurring in nested loop structures. Third, we use these traces for offline incremental memory hierarchy simulation. We extract symbolic information from the application executable and use this to generate detailed source-code correlated statistics including per-reference metrics, cache evictor information, and stream metrics. Finally, we demonstrate how this information can be used to isolate and understand memory access inefficiencies. This illustrates a potential advantage of METRIC over compile-time analysis for sample codes, particularly when interprocedural analysis is required. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors---Compilers; optimization; B.3.2 [Memory Structures]: Design Styles--Cache memories General Terms: Algorithms, Languages, Performance Additional Key Words and Phrases: Dynamic binary rewriting, program instrumentation, data trace generation, data trace compression, cache analysis

Pretenuring can reduce copying costs in garbage collectors by allocating long-lived objects into regions that the garbage collector will rarely, if ever, collect. We extend previous work on pretenuring as follows: (1) We produce pretenuring advice that is neutral with respect to the garbage collector algorithm and configuration. We thus can and do combine advice from different applications. We find for our benchmarks that predictions using object lifetimes at each allocation site in Java programs are accurate, which simplifies the pretenuring implementation. (2) We gather and apply advice to both applications and Jikes RVM, a compiler and runtime system for Java written in Java. Our results demonstrate that building combined advice into Jikes RVM from different application executions improves performance, regardless of the application Jikes RVM is compiling and executing. This build-time advice thus gives user applications some benefits of pretenuring, without any application profiling. No previous work uses profile feedback to pretenure in the runtime system. (3) We find that application-only advice also consistently improves performance, but that the combination of build-time and application-specific advice is almost always noticeably better. (4) Our same advice improves the performance of generational, Older First, and Beltway collectors, illustrating that it is collector neutral. (5) We include an immortal allocation space in addition to a nursery and older generation, and show that pretenuring to immortal space has substantial benefit. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors--Memory management (garbage collection) General Terms: Algorithms, Languages, Performance Additional Key Words and Phrases: Garbage collection, pretenuring, lifetime prediction, profiling ACM Reference Format: Blackburn, S. M., Hertz, M., McKinley, K. S., Moss, J. E. B., and Yang, T., 2007. Profile-based pretenuring. ACM Trans. Program. Lang. Syst. 29, 1, Article 2 (January 2007), 57 pages. DOI = 10.1145/1180475.1180477 http://doi.acm.org/10.1145/1180475.1180477.

This research was an investigation of children's performance on a task that requires memory binding. In Experiments 1 and 2, 4-year-olds, 6-year-olds, and adults viewed complex pictures and were tested on memory for isolated parts in the pictures and on the part combinations (combination condition). The results suggested improvement in memory for the combinations between the ages of 4 and 6 years but not in memory for the isolated parts. In Experiments 2 and 3, the authors also examined the developmental relationship between performance in the combination condition and free recall of a naturalistic event, finding preliminary evidence that performance on a memory task that requires binding is positively related to performance in episodic memory. Keywords: episodic memory, binding, memory development, free recall

Six experiments investigated conjunction memory errors (e.g., falsely remembering blackbird after studying parent words blackmail and jailbird) in a continuous recognition procedure with a parent-conjunction lag manipulation. In 4 experiments (1A, 1B, 2A, and 2B) 'recollect' judgments, which indexed recall of parent words, showed that participants can use recollection to prevent conjunction errors. 'Recollect' judgments, as well as overt recall of parent words (in Experiments 2A and 2B), dropped sharply from a lag of 0 to 1 word, then stabilized from a lag of 1 to 20 words. Thus, the 'recollect' responses and overt recall demonstrate a step function of forgetting over short intervals. These data generalized to cued recall in Experiments 3A and 3B with the first morpheme (e.g., black) as the cue, though recall conjunction errors occurred infrequently relative to recognition conjunction errors. Overall, the results support the idea that automatic and controlled processes contribute to memory performance. Keywords: memory, conjunction errors, familiarity, recollection

Reference-counting is traditionally considered unsuitable for multiprocessor systems. According to conventional wisdom, the update of reference slots and reference-counts requires atomic or synchronized operations. In this work we demonstrate this is not the case by presenting a novel reference-counting algorithm suitable for a multiprocessor system that does not require any synchronized operation in its write barrier (not even a compare-and-swap type of synchronization). A second novelty of this algorithm is that it allows eliminating a large fraction of the reference-count updates, thus, drastically reducing the reference-counting traditional overhead. This article includes a full proof of the algorithm showing that it is safe (does not reclaim live objects) and live (eventually reclaims all unreachable objects). We have implemented our algorithm on Sun Microsystems' Java Virtual Machine (JVM) 1.2.2 and ran it on a four-way IBM Netfinity 8500R server with 550-MHz Intel Pentium III Xeon and 2 GB of physical memory. Our results show that the algorithm has an extremely low latency and throughput that is comparable to the stop-the-world mark and sweep algorithm used in the original JVM. Categories and Subject Descriptors: D.1.5 [Programming Techniques]: Object-oriented Programming; D.3.3 [Programming Languages]: Language Constructs and Features--Dynamic storage management; D.3.4 [Programming Languages]: Processors Memory management (garbage collection); D.4.2 [Operating Systems]: Storage Management--Garbage collection General Terms: Languages, Algorithms Additional Key Words and Phrases: Programming languages, memory management, garbage collection, reference-counting

ABSTRACT As new information technologies are available to the design and implementation of organizational memory and as organizations continue to automate their business processes and collect explosive amounts of data, […]

I examined 2 different views on organization of lineal order information in memory: the linear schema view and the hierarchical structure view. The linear schema view holds that there is a strong tendency in memory to organize an array of transitively related elements into a unidimensional order. The hierarchical structure view maintains that the transitively related elements are organized in memory in a hierarchy of items. I proposed an input structure and retrieval compatibility hypothesis as a coherent explanation for file contradictory views on the memory organization of serial elements. I argue that the organization of linear order information in memory is determined by the nature of the memory retrieval task used. For example, a comparative judgment task is more compatible with a unidimensional structure, whereas a sequential recall or serial position identification task is more compatible with a hierarchical organization. The input structure and retrieval compatibility concept can also explain why dichotomous categories imposed on a linear order play very little role in comparative judgments.

The problem of survival memory management of a Viterbi decoder (VD) was solved by introducing a novel pointer implementation for the register exchange method, where a pointer is assigned to each row of memory in the survivor memory unit (SMU). The content of the pointer which points to one row of memory is altered to point to another row of memory, instead of copying the contents of the first row to the second. In this paper, the one-pointer VD is proposed; if the initial state of the convolutional encoder is known, the entire SMU is reduced to only one row. Because the decoded data bits are generated in the required order, even this row of memory is dispensable. Thus, the one-pointer architecture, referred to as memoryless VD (MLVD), reduces the power consumption of a traditional traceback VD by approximately 50%, but has some performance degradation. A prototype of the MLVD with a one third convolutional code rate and a constraint length of nine is mapped into a Xilinx 2V6000 chip, operating at 25 MHz with a decoding throughput of more than 3 Mbps and a latency of two data bits. Index Terms--Low power, memoryless, register exchange (RE), Viterbi decoder (VD), wireless.

The Java RMI collector is arguably the most widely used distributed garbage collector. Its distributed reference listing algorithm was introduced by Birrell et al. in the context of Network Objects, where the description was informal and heavily biased toward implementation. In this article, we formalize this algorithm in an implementation-independent manner, which allows us to clarify weaknesses of the initial presentation. In particular, we discover cases critical to the correctness of the algorithm that were not accounted for by Birrell. We use our formalization to derive an invariant-based proof of correctness of the algorithm that avoids notoriously difficult temporal reasoning. Furthermore, we offer a novel graphical representation of the state transition diagram, which we use to provide intuitive explanations of the algorithm and to investigate its tolerance to faults in a systematic manner. Finally, we examine how the algorithm may be optimized, either by placing constraints on message channels or by tightening the coupling between the application program and distributed garbage collector. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors--Memory management (garbage collection) General Terms: Algorithms, Verification Additional Key Words and Phrases: Distributed garbage collection, distributed reference counting/listing, proof of correctness

Multithreaded applications with multigigabyte heaps running on modern servers provide new challenges for garbage collection (GC). The challenges for "server-oriented" GC include: ensuring short pause times on a multigigabyte heap while minimizing throughput penalty, good scaling on multiprocessor hardware, and keeping the number of expensive multicycle fence instructions required by weak ordering to a minimum. We designed and implemented a collector facing these demands building on the mostly concurrent garbage collector proposed by Boehm et al. [1991]. Our collector incorporates new ideas into the original collector. We make it parallel and incremental; we employ concurrent low-priority background GC threads to take advantage of processor idle time; we propose novel algorithmic improvements to the basic mostly concurrent algorithm improving its efficiency and shortening its pause times; and finally, we use advanced techniques, such as a low-overhead work packet mechanism to enable full parallelism among the incremental and concurrent collecting threads and ensure load balancing. We compared the new collector to the mature, well-optimized, parallel, stop-the-world marksweep collector already in the IBM JVM. When allowed to run aggressively, using 72% of the CPU utilization during a short concurrent phase, our collector prototype reduces the maximum pause time from 161 ms to 46 ms while only losing 11.5% throughput when running the SPECjbb2000 benchmark on a 600-MB heap on an 8-way PowerPC 1.1-GHz processors. When the collector is limited to a nonintrusive operation using only 29% of the CPU utilization, the maximum pause time obtained is 79 ms and the loss in throughput is 15.4%. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors Memory management (garbage collection) General Terms: Languages, Performance, Algorithms Additional Key Words and Phrases: Garbage collection, JVM, concurrent garbage collection

The performance benefits of speculation in a release consistently software distributed shared memory system are examined. Speculative Home-based Release Consistency (SHRC) protocol is implemented for speculatively updating data at remote nodes for reducing the latency of remote memory accesses.

The problem of testing shared memories for memory coherence and consistency is studied where first it is proved that detecting violations of coherence in an execution is NP-Complete and it remains NP-Complete for a number of restricted instances. The results indicate that the complexity of verifying consistency models is not a mere consequence of coherence and verifying sequential consistency remains NP-Complete even after coherence is verified.

The five options for virtual address translation in the context of Distributed Shared Memory multiprocessors including Cache-Coherent Non-Uniform Memory Access Architectures and Cache Only Memory Access Architectures are described and compared. The Translation Lookaside Buffer is very effective when it is merged with the shared memory, because of the sharing and prefetching effects and there is no need to maintain its consistency is also observed.

The development of best-fit allocators and comparisons with Doug Lea allocator is described and the effects of allocation policies on performance and memory usage are examined. Results show that programs respond differently to different allocation policies.

In many applications, users specify target values for certain attributes, without requiring exact matches to these values in return. Instead, the result to such queries is typically a rank of the "top k" tuples that best match the given attribute values. In this paper, we study the advantages and limitations of processing a top-k query by translating it into a single range query that a traditional relational database management system (RDBMS) can process efficiently. In particular, we study how to determine a range query to evaluate a top-k query by exploiting the statistics available to an RDBMS, and the impact of the quality of these statistics on the retrieval efficiency of the resulting scheme. We also report the first experimental evaluation of the mapping strategies over a real RDBMS, namely over Microsoft's SQL Server 7.0. The experiments show that our new techniques are robust and significantly more efficient than previously known strategies requiring at least one sequential scan of the data sets. Categories and Subject Descriptors: H.2.4 [Database Management]: Systems--query processing; relational databases; H.3.3 [Information Storage and Retrieval]: Information Search and Retrieval--retrieval models; search process; H.3.4 [Information Storage and Retrieval]: Systems and Software--performance evaluation General Terms: Algorithms, Measurement, Performance Additional Key Words and Phrases: Multidimensional histograms, top-k query processing

The pattern of factor effects on response time (RT) performance in multi-factor experiments provides a powerful technique for inferring the structure of underlying mental processes. The results of the present lexical decision experiment show that additive effects of stimulus quality and word frequency are observed in mean RTs, variances, and the exGaussian parameters of the RT distribution. These findings are consistent with the conclusion that word frequency and stimulus quality affect separate stages of processing. This is consistent with the conclusion that word frequency effects reflect mapping operations between stages, but, when taken in conjunction with other reports in the literature, is inconsistent with the received view in many activation models that word frequency exerts its effect within the word detector level of representation.

Global register allocation through graph coloring uses program structure knowledge for the guidance of global register allocation. Restrictions on the live ranges of loops and conditionals cause the respective portions of the register conflict graph to become interval graphs. The location of clique separators in register conflict graphs is found by the use of this knowledge. Sequential register allocation and parallelized global register allocation are improved by the use of clique separators.

An analytical approach and numerical simulation of rate equations yielded a memory diagram, and also demonstrated that pattern effects present at the output of the laser can be prevented by reducing the bias current to a level slightly below the threshold. An increase in the bias current induces an elevated bias of the laser above the threshold. The memory region comprises small no memory zones termed 'no-memory islands.'

In this paper, the algorithm and architecture of a variable-length-code (VLC) codec system using a new group-based approach and achieving full table programmability are presented. According to the proposed codeword grouping and symbol memory mapping, both group searching and encoding/decoding procedures are completed by applying numerical properties and arithmetic operations to codewords and symbol addresses. By a novel symbol conversion, the memory requirement of the encoding process is reduced and the programmability of codewords and symbols is achieved. For MPEG applications, a 0.6-/[micro]m CMOS design that performs concurrent VLC codec processes is shown. This VLSI implementation occupies an area of 5.0 x 4.5 [mm.sup.2] with 110 k transistors and satisfies a coding table up to 256-entry 12-bit symbols and 16-bit codewords. In addition, both encoding and decoding throughputs of this design achieve 100 Msymbols/s at a 100-MHz clock rate. Therefore, the proposed VLC codec system is suitable for applications which require high operation throughput, such as HDTV, and simultaneous compression and decompression, such as videoconferencing. Index Terms--Group-based, HDTV, Huffman coding, VLC codec, VLC/VLD.

The older you become, the more often you may face moments of forgetfulness, such as losing track of where you left today's newspaper or misplacing your wallet. While some forgetfulness [...]