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A Proportional-Integral-Derivative (PID) controller make its appearance in various control mechanism due to its adaptively, applicability and simple structure. The tuning for parameters K P , K D and K I selection for PID is a tedious task. A Particle-Swarm-Optimization (PSO) algorithm is an evolutionary method that simulates the particles to provide best solutions in a given search-space based on fitness value. It provides another design of optimization for PID controller that provides better gain parameters, fast convergence and quick computation, in this paper, an efficient designed PSO based PID controller is then synthesized with the help of Xilinx SYSGEN. To evaluate the effectiveness and usefulness of PSO the DC motor based system response is figured and compared it with conventional method.

It is the right time to embark upon wireless sensor networks to overcome problems of the structures safety by analyzing them precisely using structural health monitoring techniques. This research lays emphasis on the development of an IOT based smart instrumentation for analyzing the health structure based on simple accelerometer (ADXL320) and MCU node. The accelerometer sensing paves way in determining the health structure by observing the non-linear vibrations in the structure. The real-time data acquired from the sensor is transmitted to a cloud platform (Thingspeak) using a secure API communication that helps client to observe the frequency response of the entire structure remotely. The developed instrumentation is a power efficient, low cost solution having a latency of 15 s, and remarkably efficient.

The core part of any study of rolling stock behavior is the wheel-track interaction patch because the forces produced at the wheel-track interface govern the dynamic behavior of the whole railway vehicle. It is significant to know the nature of the contact force to design more effective vehicle dynamics control systems and condition monitoring systems. However, it is hard to find the status of this adhesion force due to its complexity, highly non-linear nature, and also affected with an unpredictable operation environment. The purpose of this paper is to develop a model-based estimation technique using the Extended Kalman Filter (EKF) with inertial sensors to estimate non-linear wheelset dynamics in variable adhesion conditions. The proposed model results show the robust performance of the EKF algorithm in dry, wet/rain, greasy, and fully contaminated track conditions in traction and braking modes of a railway vehicle. The proposed model is related to the other works in the area of wheel-rail systems and a tradeoff exists in all conditions. This model is very useful in condition monitoring systems for railway asset management to avoid accidents and derailment of a train.

Usually, railway accidents are caused by train derailment, the mechanical failure of tracks, such as broken rails often caused by lack of railway condition monitoring. Such monitoring could identify track surface faults, such as squats, that act as a catalyst for the track to crack and ultimately break. The research presented in this paper enables real-time identification of railway track faults using image processing techniques such as Canny edge detection and 2D discrete wavelet transformation. The Canny edge detection outperforms traditional track damage detection techniques including Axle Based Acceleration using Inertial Measurement Units and is as reliable as Fiber Bragg Grating. The Canny edge detection employed can identify squats in real-time owing to its specific threshold amplitude using a camera module mounted on a specially designed handheld Track Recording Vehicle (TRV). The 2D discrete wavelet transformation validates the insinuation of the Canny edge detector regarding track damage and furthermore determines damage severity, by applying high sub band frequency filter. The entire algorithm works on a Raspberry Pi 3 B+ utilizing an OpenCV API. When tested using an actual rail track, the algorithm proved reliable at determining track surface damage in real-time. Although wavelet transformation performs better than Canny edge detection in terms of determining the severity of track surface damage, it has processing overheads that become a bottleneck in real-time. To overcome this deficiency a very effective two-stage process has been developed.

Induction motors (IMs) are the workhorse of the industry and are subjected to a harsh environment. Due to their operating conditions, they are exposed to different kinds of unavoidable faults that lead to unscheduled downtimes and losses. These faults may be detected early through predictive maintenance (i.e., deployment of condition monitoring systems). Motor current signature analysis (MCSA) is the most widely used technique to detect various faults in industrial motors. The stator winding faults (SWF) are one of the major faults. In this paper, we present an induction motor fault detection and identification system using signal processing techniques such as fast Fourier transform (FFT), short-time Fourier transform (STFT), and continuous wavelet transform (CWT). A three-phase motor model is developed in MATLAB Simulink and simulated under various fault conditions. The current signature is observed using FFT, spectrogram, and scalogram to detect the faults. It is observed that under some fault conditions, the current signature analysis remains indistinguishable from the non-fault case. Therefore, deep learning (DL) methods are adopted here to identify these faults. The time-series data of healthy and unhealthy conditions are obtained from the simulation results. The comparative investigation among DL models confirmed the superiority of the long short-term memory (LSTM) model, which achieved 97.87% accuracy in identifying the individual faults.

Digital filters are the most significant part of signal processing that are used in enormous applications such as speech recognition, acoustic, adaptive equalization, and noise and interference reduction. It would be of great benefit to implement adaptive FIR filter because of self-optimization property, linearity and frequency stability. Designing FIR filter involves multi-modal optimization problems whereas conservative gradient optimization technique is not useful to design the filter. Hence, Particle Swarm Optimization (PSO) algorithm is more flexible and optimization technique based on population of particles in search space and alternative approach for linear phase FIR filter design. PSO improves the solution characteristic by giving a novel method for updating swarm's position and velocity vector. Set of optimized filter coefficients will be generated by PSO algorithm. In this paper, PSO based FIR Low pass filter is efficiently designed in MATLAB and further Xilinx System Generator tool is used to efficiently design, synthesize and implement FIR filter in FPGA using SPARTEN 3E kit. For an example specifications, output of PSO algorithm is obtained that is set of optimized coefficients whose response is approximating to the ideal response. Hence, functional verification of the proposed algorithm has been performed and the error between obtained filter and ideal filter is minimized successfully. This work demonstrates the effectiveness of the PSO algorithms in parallel processing environment as compared to the Remez Exchange algorithm.

Preventive maintenance is one of the main concerns in modern industry, in which early failure detection increases the lifecycle of machines. In this paper, electrical signature analysis is employed to indicate the development or existence of faults within the proposed system and this is achieved by embedding a real-time frequency analysis of the motor current. The term in the title electrical signature analysis basically refers to the motor current or voltage attributes are being used as a transducers to detect the changes in their spectrum in both the conditions; healthy and unhealthy. The algorithm used for analyzing the signals in frequency domain is done using Fast Fourier transform. In this work, we have focused on failure of bearing part of single phase induction motor and developed hardware for monitoring conditions (i.e. health of the motor) in run time. Because of the simplicity of this technique the mechanism of fault diagnosis is employed using an FPGA approach that offers re-configurability. This work can be very useful in industrial setup where there are 100 motors working together for some production lines. The findings show promising results which could lead to better reliability performance of the induction motor and lower maintenance costs.

Recenlty, short word length DSP systems are proposed and reported that they outperform compared to their counterpart multi-bit systems in the sense of area-performance-power analysis. In this continuation, this paper presents the application of sigma-delta modulation (SDM) in the design of adaptive channel equalizer using the Wiener filter for wireless and underwater acoustic communication (UWA). To validate the application, various aspects of design are taken into consideration and comparison is carried out with contemporary (i.e., multi-bit) approach. Besides, FPGA based implementation of SDM based design and conventional approach is also carried out to endorse the proposed algorithm to be used in hardware based implementation. The results given in terms of area -perfromance analysis show that proposed algorithm works as desired and it opens the way of using the sigma-delta modulation in adaptive signal processing domain for UWA that has remained a quite challenging task ever before.

FPGA’s block memory may be programmed as a single or dual-port RAM/ROM module that leads to an area-efficient implementation of memory-based systems. In this contest, various works of carrying out an optimized implementation of simple to complex DSP systems on embedded building blocks may be seen. The multiplier is a core element of the DSP systems, and in implementing a memory-based multiplier, it is observed that one of the operands is kept constant, hence leading the design to a constant-coefficient multiplication. This paper shows Virtex-7 FPGA’s dual-port ROM-based implementation of an 8x8 variable-coefficient multiplier that may be used in several simple to complex DSP applications. The novelty of the proposed design is to configure the block ROM in dual-port mode and, hence, get four partial products in two clock cycles and introduce two unconventional adder approaches for partial product addition. This approach leads to fully resource utilization and the provision of a variable-coefficient multiplier. The work also shows the comparison of proposed architecture with already existing memory-based implementations and concludes the work as a novel step towards the efficient memory-based implementation of multiplier core.

Matched filtering has found its way in many diverse applications such as communication, signal processing and more. The emphasis of this paper is on the design and analysis of a sigma-delta (ΣΔ) modulated ternary Matched Filter aimed at digital signal processing. The filter coefficients are made ternary {+ 1, − 1, 0} using the Ternary Quantizer. The performance of the new design is measured on the basis of Probability of error versus Signal-to-noise ratio and it was discovered that the performance curve of the single-bit designed Matched Filter is approximately in agreement with the theoretical SNR versus Probability of error curve and works satisfactorily satisfactorily like a multi-bit Matched Filter and as an extension, the functionality of the above mentioned design is also generated on Xilinx System Generator and is successfully synthesized, simulated and verified on FPGA.

Reliability of rotating machines is highly dependent on the smooth rolling of bearings. Thus, it is very essential for reliable operation of rotating machines to monitor the working condition of bearings using suitable fault diagnosis and condition monitoring approach. In the recent past, Deep Learning (DL) has become applicable in condition monitoring of rotating machines owing to its performance. This paper proposes a novel bearing fault diagnosis method based on the processing and analysis of the vibration images. The proposed method is the UNET model that is a recent development in DL models. The model is applied to the 2D vibration images obtained by transforming normalized amplitudes of the time-series vibration data samples into the corresponding vibration images. The UNET model performs pixel-level feature learning using the vibration images owing to its unique architecture. The results demonstrate that the model can perform dense predictions without any loss of label information, generally caused by the sliding window labelling method. The comparative analysis with other DL models confirmed the superiority of the UNET model which has achieved maximum accuracy of 98.91% and F1-Score of 99%.

In the railway industry, slip control has always been essential due to the low friction and low adhesion between the wheels and the rail and has been an issue for the design, activity, and operation of railroad vehicles. Slip is an unpredictable parameter in the railroad that disintegrates the surface of the railroad with a contact surface of the boggy wheel brought about by the mechanical force of traction phenomena, it destabilizes the railway traction which does not fulfill safety and punctuality requirements. In this paper, we present the work based on developing a fuzzy logic-based anti-slip controller for the commuter train using FPGA implementation which minimizes slip parameters. The development of a fuzzy logic- based anti-slip controller for the commuter train is designed in MATLAB and then tested for area-performance parameters in FPGA through the system generator library. Simulation is performed to demonstrate the effectiveness of the proposed fuzzy logic control system for anti-slip control under various parameters, the results of simulation prove the effectiveness of the proposed control system as compared with conventional PID controller and shows high anti-slip control performance under nonlinearity of brake dynamics.

Wiener, the well-known adaptive filter is seen in almost all the applications of adaptive signal processing. It gets the weight updating by solving the Wiener –Hopf equation (ωopt = R−1P). When implemented on the state of the art hardware, like ACIS or FPGA, this filter results in substantial resource consumption. This paper proposes updating the filter weights by reducing the need for an auto-correlation matrix (R) and calculating the filter weights based on cross-correlation vector (P) only. This approach would result in a noticeable resource reduction by compromising some of the performance that may be acceptable in voice or video being less sensitive. The proposed correlation-less approach and the conventional method are first simulated in Matlab and then is implemented in Xilinx Vertex 7 FPGA for one to one comparison. The results indicate that the proposed approach reduces a significant amount of resources along with acceptable performance characteristics. Therefore, it may be incorporated in various applications of mobile communication, especially the adaptive channel equalizer.

Different multiplication algorithms have different performance characteristics. Some are good at speed while others consume less area when implemented on hardware, like Field Programmable Gate Array (FPGA)-the advanced implementation technology for DSP systems. The eminent parallel and sequential multiplication algorithms include Shift and Add, Wallace Tree, Booth, and Array. The multiplier optimization attempts have also been reported in adders used for partial product addition. In this paper, analogous to conventional multipliers, two new multiplication algorithms implemented on FPGA are shown and compared with conventional algorithms as stand-alone and by using them in the implementation of FIR filters and adaptive channel equalizer using the LMS algorithm. The work is carried out on Spartan-6 FPG that may be extended for any type of FPGA. Results are compared in terms of resource utilization, power consumption, and maximum achieved frequency. The results show that for a small length of coefficients like 3-bit, the proposed algorithms work very well in terms of achieved frequency, consumed power, and even resource utilization. Whilst for the length greater than 3-bit, the Pipelined multiplier is much better in frequency than the proposed and conventional ones, and the Booth multiplier consumes fewer resources in terms of lookup tables.

Floating-point arithmetic has various applications in the field of Science and Engineering. Specially, need of high precision floating-point multipliers is observed in Digital Signal Processing- like in filtering and transformations . High speed signal processing demands for high speed hardware. Though, various high level languages based implementations of floating-point multiplier are observed so far, but the hardware based implementation has still remained a bottleneck. With the development of Very Large Scale Integration (VLSI) technology, Field Programmable Gate Array (FPGA) has become the best candidate for implementing floating-point multipliers (due to their high integration density, low price, high performance and flexible applications). In this work, we have shown the implementation of IEEE-754 single precision floating-point multiplier on FPGA using carry-look ahead adder (for exponent addition). The multiplier may be used in adaptive filters for multiplying the fractional step size (mue) to update the filter weights. This paper also presents the comparative analysis of proposed design with Spartan 6 FPGA's built-in IPcore for floating-point multiplier. The results are compared in terms of recourse utilization, power consumption, observed delay, logic levels and maximum achieved frequency. It is shown that our design is better in terms of achieved frequency with a small increase in resource utilization.

Sigma-delta modulation (SDM), initially introduced for ADCs and DACs is now well known in an alternative domain of short word-length (SWL) algorithm based digital system design. Its applications start from simple arithmetic operations to very complex circuits, like the adaptive filters. The conventional multi-bit processing systems consume more resources in their implementation on ASICs and FPGAs, whereas, SDM based systems being processing the data in a single-bit result a compact design. This paper is an effort towards SDM based single-bit, design of adaptive filter using Wiener–Hopf equation on FPGA, along with analyzing the impact of SDM on performance parameters, like, Signal to Noise Ratio (SNR), Probability of Error (PE), and Mean Square Error (MSE). Besides, the error graph, showing the difference between the filtered signal in multi-bit and SDM based is also shown and analyzed using Matlab. As, the mobile phone operates in a continuous varying environment (for example, during the travel), and hence the statistical parameters (SNR, MSE, and PE) due to varying channel also vary accordingly in its conventional operations and architectures, but results show that instead if SDM is used, those statistical parameters remain constant, and in comparison to the multi-bit approach the SDM based system outdoes in all means of functionality as well as performance. Hence, it may be concluded that for continuous varying environments of wireless communication, especially the mobile communication systems, the SDM based approach may be adopted for reasons of good performance as well as compact system design.

In the recent past, a new set of digital signal processing algorithms are developed called short word length (SWL) DSP systems to mitigate the multiplier complexity that is an inherent part in most DSP functions. In SWL algorithms, the critical element is sigma-delta modulation (SDM). In this paper, we present the design, implementation, and hardware synthesis of the FIR filter and adaptive algorithms with the conventional and proposed multiplier schemes. Two proposed short word length adaptive algorithms namely Wiener and Steepest-Descent are compared with their counterpart LMS algorithm using conventional and proposed multiplier schemes. The hardware synthesize of these algorithms is done using Xilinx Spartan-6 and Vertex-7 FPGA and comparison is done based on area-performance-power. The overall results show that the sigma-delta modulation based adaptive DSP algorithm outperforms and is an efficient approach for mobile communication.

The advent of deep learning (DL) has transformed diagnosis and prognosis techniques in industry. It has allowed tremendous progress in industrial diagnostics, has been playing a pivotal role in maintaining and sustaining Industry 4.0, and is also paving the way for industry 5.0. It has become prevalent in the condition monitoring of industrial subsystems, a prime example being motors. Motors in various applications start deteriorating due to various reasons. Thus, the monitoring of their condition is of prime importance for sustaining the operation and maintaining efficiency. This paper presents a state-of-the-art review of DL-based condition monitoring for motors in terms of input data and feature processing techniques. Particularly, it reviews the application of various input features for the effectiveness of DL models in motor condition monitoring in the sense of what problems are targeted using these feature processing techniques and how they are addressed. Furthermore, it discusses and reviews advances in DL models, DL-based diagnostic methods for motors, hybrid fault diagnostic techniques, points out important open challenges to these models, and signposts the prospective future directions for DL models. This review will assist researchers in identifying research gaps related to feature processing, so that they may effectively contribute toward the implementation of DL models as applied to motor condition monitoring.

The advent of deep learning (DL) has transformed diagnosis and prognosis techniques in industry. It has allowed tremendous progress in industrial diagnostics, has been playing a pivotal role in maintaining and sustaining Industry 4.0, and is also paving the way for industry 5.0. It has become prevalent in the condition monitoring of industrial subsystems, a prime example being motors. Motors in various applications start deteriorating due to various reasons. Thus, the monitoring of their condition is of prime importance for sustaining the operation and maintaining efficiency. This paper presents a state-of-the-art review of DL-based condition monitoring for motors in terms of input data and feature processing techniques. Particularly, it reviews the application of various input features for the effectiveness of DL models in motor condition monitoring in the sense of what problems are targeted using these feature processing techniques and how they are addressed. Furthermore, it discusses and reviews advances in DL models, DL-based diagnostic methods for motors, hybrid fault diagnostic techniques, points out important open challenges to these models, and signposts the prospective future directions for DL models. This review will assist researchers in identifying research gaps related to feature processing, so that they may effectively contribute toward the implementation of DL models as applied to motor condition monitoring.