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For the sixth-generation (6G) communication, it is required to support the massive Internet of Things (IoT) devices with high data rate applications such as vision-based sensors. Unfortunately, the current sub-6-GHz band is already congested, and lower-band communication is hard to support the high data rate transmission. The millimeter-wave (mmWave)-based communication technology is a promising solution to support the high rate transmission in a new band. However, the high power consumption and hardware cost of the mmWave communication system violates the low-cost design principle of IoT devices, which is a heavy burden for the mmWave application on IoT. In this work, we propose the multiple IoT nodes access-based wireless beam modulation (WBM) technology for the mmWave transmission, where the WBM employs the over-the-air modulation to achieve the low-cost mmWave hardware design with hundreds of megabit per second transmission. To support multiple IoT nodes access, we first design a hyper grant-based and grant-free protocols to achieve the balance between robustness and low latency access. The multiple beam search method is proposed to accelerate the beam alignment process. The channel estimation of WBM is achieved by the pilot detection and beam estimation process, where an iterative pilot cancelation beam estimation method is proposed. According to the simulation and hardware implementation results, the WBM-based communication system can provide a much higher data rate transmission service than the current IoT-based communication systems, and much lower power consumption and hardware cost than the mmWave-based system.

For a true random number generator (TRNG) on an FPGA, the use of a pair of clocking elements has an advantage of minimal usage of its logic elements. This paper presents a novel high-speed TRNG for recent Xilinx FPGAs using their clocking elements called mixed-mode clock managers (MMCMs). By following the proposed parameter selection methods, both better randomness and higher throughput of generated bitstrings can be achieved. According to our evaluation on an Artix-7 FPGA with the most promising sets of parameters, 38.2% (42 out of 110) of the sets passed AIS-31 Procedure B, which means that an appropriate parameter set can be found by ten or less trials with more than 99% probability. The average throughput of them was 2.44 Mbit/s, which was comparable to recent FPGA-based TRNGs. An initial prototype of dynamic reconfiguration of the parameters is also presented in this paper.

In this article, we investigate neutron-induced failures of the Galaxy S7 Edge smartphone (released 2016). Anomalous changes in the neutron-irradiated Galaxy smartphone are described in detail (e.g., device current increments up to 270 mA or overheating in the proximity of the WiFi module). The discussion of system failures includes not only visual observations, but also changes in the current and device temperature of the target smartphone. The system behavior associated with failure modes is also discussed in an effort to relate single-event effects to system malfunctions. Additionally, the test results are compared to similar studies of five products (released 2007–2015). In comparison to the failure rates among those products, the system-level failure-in-time (FIT) did not show a downward trend, although the FIT per megabit (FIT/Mbit) values of static random access memory (SRAM) declined as the technology node shrank.

We propose and experimentally demonstrate a color-shift-keying embedded direct-current-optical-orthogonal-frequency-division-multiplexing (CSK-DCO-OFDM) scheme for the VLC systems. The proposed scheme can provide not only non-flickering aggregated optical power to reduce human health concerns, but also offers additional modulation dimension or flexibility to the CSK by including high data rate OFDM signal. The data rate is increased from 10 Mbit/s in the original CSK signal to 70.43 Mbit/s in the CSK-DCO-OFDM signal, and both the CSK and OFDM signals satisfy the forward-error-correction (FEC) threshold.

A problem of an increase in the range of direct chaotic ultrawideband transceivers is considered. Parameters that determine the range are theoretically estimated. Experimental transceivers with a capacity of up to 12 Mbit/s and a range of greater than 200 m are developed and fabricated. The corresponding software is developed and tested. Experimental characteristics of the devices prove the theoretical estimations.

The past few decades have shown great advancements in wireless communication systems; however, today's explosive increase in data traffic demands even further improvement in such systems toward next-generation platforms. Current 4G mobile systems provide stationary users with data speeds up to 1 Gbit/s and high-mobility users with speeds up to 100 Mbit/s for mobile online access and multimedia applications such as TV streaming, video conferencing, navigation, high-end gaming, high-definition video streaming, and high-performance imaging [1].

We demonstrate the first continuous variable quantum key distribution (CV-QKD) system with fully digital phase and polarization tracking, enabling the first wavelength division multiplexing experiment for CV-QKD. We transmit 194 × 0.5 GHz channels with 25 GHz channel spacing, demonstrating an aggregate estimated asymptotic secret key rate of 172.6 Mbit/s over 25 km.

Smart grid networks demand reliable, efficient and real-time energy management by exchanging information. Transmitting and receiving information needs a two-way, secure, reliable and high-speed communication infrastructure, which should be capable to handle impulse noise present in power system. Power division non-orthogonal multiple access scheme can fulfill this requirement through its high spectral efficiency. In this paper, we proposed a composite multiple access model based on orthogonal beamforming (OBF) and non-orthogonal multiple access scheme for exchanging information between smart grid, smart meters (SMs) and other communication units in the presence of impulse noise. We divide a cell in sectors and implement OBF between sectors to reduce inter beams interference using orthogonalization. Within the sectors, we implement power division multiple access to utilize maximum bandwidth with the help of successive interference cancelation scheme. Furthermore, to find the effect of impulse noise on performance of proposed model we consider Gaussian and Laplacian models with Bernoulli arrival rate. Simulation and numerical findings show that the proposed method does not cause interference between SMs and offers $$3\;{\text{Mbit}}/\text{s}$$ higher data rate than the traditional OFDMA systems leading to better system capacity in case of four SMs in a sector of a cell.

The purpose of this study was to write programs to define sampling sizes and observation units by probability sampling methods and to provide an idea for software developers. The algorithms of the programs were written in Python 3. The programs may be run by double-clicking on the Windows operating system or by the command prompt of the DOS operating system. Each exe file has a memory space of 5 megabits on average. In this respect, the application files are very useful in terms of sharing by email and mobility by USB memory sticks., The purpose of this study was to write programsto define sampling sizes and observation units by probability sampling methodsand to provide an idea for software developers. Thealgorithms of the programs were written in Python 3. The programs may be run bydouble-clicking on the Windows operating system or by the command prompt of theDOS operating system. Each exe file has a memory space of 5 megabits onaverage. In this respect, the application files are very useful in terms ofsharing by email and mobility by USB memory sticks.

Resistive switching memory (RSM) shows potentials for high-capacity storage because of its simple cell structure, small footprint, and good scalability. This two-part article discusses how to implement ultrahigh-density (~terabits) storage with RSM covering design considerations from device to memory array architecture. In Part I of this two-part article, an accurate and computationally efficient model is developed to study 3-D vertical RSM (VRSM). In this article, we use 3-D VRSM with a hexagon-patterned pillar layout (3-D hexagon VRSM) as an example to elaborate our approach. Using the parasitic resistance extracted from physics-based 2-D field solver as the reference, we develop a lumped resistor network for SPICE simulation to accurately capture all leakage currents of the array. This full resistor network is further simplified to a reduced network to achieve high computational efficiency and maintain the full network accuracy (with a relative error

We propose and demonstrate a green semipolar (20-21) micro-light emitting diode (LED) acting as a high speed visible light communication (VLC) photodiode (PD). The micro-LED PD has the optical-to-electrical (OE) response of 228 MHz. A record data rate of 540 Mbit/s in on-off-keying (OOK) format with free-space transmission distance of 1.1 m was achieved, fulfilling the pre-forward error correction (FEC) limit. Many transmitters (Txs) and receivers (Rxs) is required to support the high density pico/femto-cells in future wireless networks, as well as the Internet-of-Things (IOT) networks. The proposed work could allow the realization of a low-cost, small-footprint and a high level of integration of VLC Txs and Rxs on the same platform.

Persistent data storage is the basis of all modern information systems. The long-term value and volume of data are growing at an accelerating rate and pushing extant storage systems to their limits. DNA offers exciting potential as a storage medium, but no practical scheme has been proposed to date that can scale beyond narrow-band write rates. Here, we demonstrate a combinatorial DNA data encoding scheme capable of megabits per second write speeds. The system relies on rapid, combinatorial assembly of multiple smaller DNA parts that are dispensed through inkjet printing. To demonstrate this approach, we wrote approximately 25 kB of information into DNA using our system and read the information back out with commercially available nanopore sequencing. Moreover, we demonstrate the ability to replicate and selectively access the information while it is in DNA, opening up the possibility of more sophisticated DNA computation.

Visible light communication (VLC) allows the dual use of lighting and wireless communication systems by modulation of illumination devices. However, to increase the performance, typically, beam-forming measures are taken creating pencil beams, thus contradicting the illumination purpose. In order to optimize the performance trade off between efficient illumination and communication, the switching capabilities of illumination LEDs are examined. Illumination LEDs with standard drivers and without beam-forming show limited applicability for communication purposes as they are not optimized for the necessary switching capability (f ≈11 MHz) and coherence. Methods to enhance the electrical current by pre-equalisation, biasing, carrier sweeping and current shaping are examined in respect to the illumination LED's communication performance. A novel driver scheme is derived which achieves considerably higher switching frequencies (f ≥100 MHz) without employing beamforming at the illumination LED. This driver is able to obtain a data rate of up to 200 Mbit/s at a distance of 3.2 m, using on-off keying (OOK) modulation technique. Therefore, it is feasible to apply the LED driver by implementing standardised illumination devices in VLC systems.

Random telegraph noise (RTN) read instability of high-resistance state (HRS) in hafnium–based resistive random access memory (RRAM) is investigated using megabit array statistical analytics. It is found that the RTN read current fluctuation decreases along with the resistance of HRS; this is attributed to the small quantity of perturbation sources in tunnel gap between the conductive filament and the bottom electrode. Our experiment shows that maximum current fluctuation for the HRS tail bit of the megabit array is less than $1~\mu \text{A}$ during 106 successive read operations, and should eliminate the potential RTN-related obstacles for embedded RRAM technology development.

Background Practical applications for data analysis may require combining multiple databases belonging to different owners, such as health centers. The analysis should be performed without violating privacy of neither the centers themselves, nor the patients whose records these centers store. To avoid biased analysis results, it may be important to remove duplicate records among the centers, so that each patient’s data would be taken into account only once. This task is very closely related to privacy-preserving record linkage. Methods This paper presents a solution to privacy-preserving deduplication among records of several databases using secure multiparty computation. It is build upon one of the fastest practical secure multiparty computation platforms, called Sharemind. Results The tests on ca 10 million records of simulated databases with 1000 health centers of 10000 records each show that the computation is feasible in practice. The expected running time of the experiment is ca. 30 min for computing servers connected over 100 Mbit/s WAN, the expected error of the results is 2−40, and no errors have been detected for the particular test set that we used for our benchmarks. Conclusions The solution is ready for practical use. It has well-defined security properties, implied by the properties of Sharemind platform. The solution assumes that exact matching of records is required, and a possible future research would be extending it to approximate matching.

Minimum device dimensions in 4 Mbit dynamic random access memories (DRAMs) are below 1 μm. This level of miniaturization requires the development of novel structures for the memory cell such as trench capacitors and fully overlapping bitline contacts. TEM of thin cross sections was used to study morphological details such as oxide thinning at the trench edges and configurations of multilayer dielectrics. Furthermore, novel metallization systems like selective CVD of W in contact holes and TiN/Ti barrier layers were investigated with respect to interface reactions.

We demonstrate a CV-QKD system that achieves key rates of 2.5 Mbit/s over 20 km using a cost-efficient transmitter based on a commercially available integrated coherent transceiver module.

A novice scalable MBIT unit with MISR signature analysis is proposed in this project. Enhancement of MBIST architecture with signature analysis significantly improvises resolution of fault detection in memories in comparison to conventional MBIST Architecture. The proposed MBIST Algorithm is optimized by using only 14 states for 7 March algorithms, hence improvising the scalability of the MBIST without area overhead. The proposed architecture has an interface check MISR which features isolated detection of fault in memory interface and memory, hence improving resolution and accuracy. Rapid Fault check is enabled by Memory pre-check using MISR. Benchmarking for this project in terms on the accuracy, feature enhancement, scalability and the ability to detect early faults in less time are done via Random constrained verification of the developed RTL Model....

Custom experiment setups in physics often require control electronics to execute actions and measurements on a small time scale. When further constraints limit the experiment's environment, for example when the experiment is inside a sounding rocket, conventional network systems will not suffice those constraints because of weight, heat or budget limitations. This paper proposes a network architecture with a time resolution of less than 1 ns over a pair of plastic fibers while using low-cost commercial hardware. The plastic fibers in comparison to copper fibers have a low weight and additionally can isolate parts of the setup galvanically. Data rates of 40 Mbit/s enable the network to transfer large amounts of measurements and configuration data over the network. Proof-of-concept implementations of network endpoints and switches on small FPGAs are analyzed in terms of synchronicity, data rate and resource usage. Using commercial parts the resolution of 1 ns is reached with a standard deviation of less than 100 ps. Compared to a copper wire implementation the weight is reduced by about one order of magnitude. With its low weight at a low cost, the network is useful in space or laboratory setups which require high time resolution., Comment: 12 pages, 8 figures

Multipliers are present in a large variety of applications. However, it is usually responsible for most of the power dissipation. On the other hand, the squared multiplier is a particular case of the general-purpose multiplier, in which both operands are the same, proportioning many architecture optimizations. This paper introduces the radix-2m squared array multiplier architecture. Our architecture proposal for the squared multiplier is the first to reduces the partial products by splitting the operands into mbit groups. Our squared multiplier architecture explores different adder schemes in the multipliers adder tree. As a case study, we demonstrate our squared multiplier proposal for m=2 (radix-4). We investigated the Wallace and Dadda addition trees employing as final carry propagating adder (CPA) the Ripple Carry adder (RCA) and with the adder automatically selected by the synthesis tool. Our best radix-4 squared multiplier proposal employs the Dadda technique and the RCA to implement the adder tree, showing significant energy savings of 20.5%, 56.5%, and 47.4%, for 8, 16, and 32 bits, respectively, compared to the squared multiplier automatically selected by the synthesis tool. Furthermore, our best radix-4 squared multiplier proposal outperforms the Vedic squared multiplier with energy savings in about 21.5%, 71.0%, and 9.0%, respectively, for 8, 16, and 32 bits.

A True Random Number Generator (TRNG) using a pair of Phase-locked Loops (PLLs) or Digital Clock Managers (DCMs) has an advantage of minimal usage of logic elements of FPGA. This paper focuses on a new clocking element of Xilinx FPGAs called mixed-mode clock manager (MMCM) and presents its effective use for better randomness and higher throughput. According to an evaluation on an Artix-7 FPGA using 132 sets of parameters, 89 sets passed AIS-31 Procedure B with the proposed method, while only 9 sets passed when simply porting an existing DCM-based method. The average throughput was 1.18 Mbit/s, which was 5x faster than an existing DCM-based method.

Signal processing hardware designers of Low-Density Parity-Check (LDPC) decoders used in modern optical communications are confronted with the need to perform multi-parametric design space exploration, targeting very high throughput (hundreds of Mbit/s) and low-power systems. This work addresses the needs of current designers of dedicated GF(2m) NB-LDPC decoders that necessitate robust approaches for dealing with the ever-increasing demand for higher BER performance. The constraints pose tremendous pressure on the on-chip design of irregular data structures and micro-circuit implementation for supporting the complex Galois field mathematics and communications of hundreds of check nodes with hundreds of variable node processors. We have developed kernels targeting GPU and FPGA (HLS and its equivalent RTL) descriptions of this class of complex circuits for comparing area, frequency of operation, latency, parallelism and throughput. Exploiting techniques such as using custom bit-widths, pipelining, loop-unrolling, array-partitioning and the replication of compute units, results in considerably faster design cycles and demands less non-recurring engineering effort. We report a throughput performance of 800 Mbps for the FPGA case.

The foundation of a smart and connected community is its advanced digital infrastructure. Kilobits of bandwidth to the home and smart business became available in the 1970s via dial-up. Two decades after that in the 1990s, megabits became available via cable modem. Another two decades introduced gigabit to the home and small business in the 2010s. Gigabit networking to the home and small business has created a gigabit frontier of new applications. Gigabit has changed the game for applications delivered to homes and small businesses in three fundamental ways: increased flow size, reduced response times, and ability to accommodate multiple segregated flows of differential Quality of Experience. Examples of US Ignite gigabit applications and services deployed within the 30 US Ignite Smart Gigabit Communities are discussed. The COVID-19 pandemic adds additional rationale for gigabit networking. Future applications for gigabit applications that may arrive later in the 2020s are discussed. Academics are beginning to experiment with terabit networking which appears to be on-schedule for deployment to homes and small businesses in the 2030s.

Physical unclonable functions are integrated circuits well-known for their potential to replace dedicated secure storage of cryptographic keys. On FGPAs, ring-oscillators have received great attention as the most preferable implementation. Many measurement data sets have been published with large quantities of ring-oscillators on large quantities of chips. Yet, all these data sets are missing large quantities of readouts, which limits their usage for proving the efficiency of error correction algorithms. In this work, we present multiple different approaches of measurement control and readout extraction for external storage. We cover the full development process, beginning with slow extraction in early stages for maximum control up to final extraction with automated high-speed designs. Targeting a Zynq-7000 architecture, the final design extracts 3800 �� 10000 readouts within 8.04 s, which relates to a data extraction rate of 36 Mbit/s. In comparison to an early stage design, which took 452.91 s for the same measurement, a reduction in total run time of 98.2% was achieved., acceptedVersion

Here we present the experimental characterization of 1 Mbit/s optical wireless communication system by simulating an intra-CubeSat environment where we exploit the reflections to transmit in the 2U CubeSat. The optical system uses infrared-LEDs, silicon-Avalanche photodiode, digital optical power meter and optical attenuators.

Nowday, UAV is new technologie among the next generation monitoring system which has the following properties: efficient, real time, secure and reliable. UAV occupied a great importance in many fileds especially national defense in order to protect the human. In fact, the size of transferred data is a basic demand for realtime video communication, partically for military service since the bandwidth limitation in UAV networks.Exprimental results show that the H264 standard outperforms MPEG 4 (Motion Picture Expert Group) encoder in termes of PSNR (Peak signal to noise ratio). The H264’PSNR gain is 6.88% better than MPEG 4. In addition, the H264 standard did not exceed 20 Mbit\s for wireless video transmission.

The read disturb performance and industrially applicable model of mega-bit level embedded RRAM with standard 28 nm select transistor are demonstrated in this study. At first, 100k endurance test on 0.5 Mb RRAM 1 T1R array is implemented and non-degraded memory window with high read disturb immunity results are acquired. Contrary to conventional analysis on major bits, the read disturb model is especially investigated on tail bits in this work. Furthermore, the read disturb performance for chip user condition with nano-second level pulse width is well emulated by long pulse, which provides a time-efficient way to evaluate read disturb performance at product level. As a consequence, the mega-bit 28 nm RRAM array in this work is able to sustain larger than 1 E 18 read counts at a rigorous fail criteria.

We perform experiments on the wireless communication between a drone flying at different heights and a commercial 5G base station. An Android-based tool deployed on a 5G test platform is used to record radio link parameters in the up- and downlink. In the downlink, measurements show a throughput of 600 Mbit/s on average with peaks above 700 Mbit/s. The uplink has a significantly lower throughput, comparable to 4G, with a few tens of Mbit/s.

The paper presents a description of the quadrature phase shift keying (QPSK) signal shaping methodology based on the structure of a globally linearized synchronization system (GLSS). The results of simulation modeling of the QPSK-GLSS shaper, which performs the modulation process directly at the operating frequency in the microwave range, under conditions when the use of a programmable element base becomes ineffective, are presented. To synthesize the QPSK signal, the structure of the GLSS is supplemented with special control units that transform the phase portrait in such a way that the points of stable equilibrium of the system are located in steps equal to π/2 radians. The first control unit implements static shifts of the locations of the system stable equilibrium points equal to ±π/4 along the phase axis of the system phase portrait, depending on the polarity of the control signal. The second unit of binary control implements alternate synchronization of the GLSS system at two points of stable equilibrium located at a distance of $\boldsymbol{\pi}$ radians from each other. Joint combinations of control actions give a complete set of phase shifts of the system output signal relative to the reference oscillation, which corresponds to the QPSK manipulation: [-π/4; π/4; 3π/4; 5π/4]. The dynamic characteristics of the QPSK-GLSS shaper (modulator) are illustrated by the results of simulation when generating a signal directly at a frequency of 6.4 GHz and a data transfer rate equal to 300 Mbit/s.

Robustness of communication is essential for many automotive and industrial Ethernet applications due to real-time and safety features that are required. Existing data transmission structures have to be used for higher transmission rates in some application. Likewise, some new installation require cost-effective cabling with non-ideal transmission characteristics such as unshielded single twisted pair. This enables economic feasibility of Industrial Internet of Things networking of simple sensors and actors. We introduce a universal platform for physical layer analysis for such physical layers. It covers communication channels up to some 10 Mbit/s, which are typically found in industrial and automotive Ethernet. We present a combined soft- and hardware solution. It comprises an end-to-end communication and facilities spectrum, correlation and constellation analysis. Application to and results for unshielded twisted pair cabling are presented.

Some terrestrial Internet access links provide only low data rates. Internet access via geostationary satellites on the other hand provides data rates of up to 50 Mbit/s, but suffers from high latencies. The combination of low data rate, low latency Internet access (e.g., DSL light) and high data rate, high latency Internet access (e.g., geostationary satellites) can utilize the advantages of both. We discuss multipath communication architectures and scheduling strategies for such heterogeneous link combinations. The solution described in this paper relies on Split TCP and Performance Enhancement Proxies. We implement and evaluate the solution with the network simulator ns-3. A well-established traffic model for loading websites is enhanced with different HTTP variants. The results show that the combination of heterogeneous link types can result in page load times close to as if there was a high data rate, low latency Internet access.

We investigate a continuous variable quantum key distribution system with digital tracking of both polarization and phase. Stable operation over 25km for 36 hours with secret key rates between 1.9 and 2.8 Mbit/s is demonstrated.

Wired or wireless network has become the essential way to use the Internet and complete people’s task these days. As the number of people accessing the wireless network increases, it gets complicated to rely on an incorrupt signal due to the jammed airwaves. Though Wi-Fi delivers a speed up to 1300 Megabits per second, it is not adequate to hold all the users. To redress this drawback of Wi-Fi, a new concept is being introduced called as Li-Fi, which provides a speed up to 224 Gigabits per second. This is very analogous to Wi-Fi. The major disparity is that visible light is used by Li-Fi and radio frequency is used by Wi-Fi to transmit data. In this project an Android application is created to transfer binary data from one device to another device through Li-Fi, whereas for audio transfer, a hardware setup is implemented using LED, solar cell, and speaker.

The data rates of uncompressed digital video signals range from 270 Mbit/s (SDTV) through 1.5 Gbit/s (HDTV) or 3 Gbit/s (HDTV) to 12 Gbit/s (UHDTV). However, these data rates are too high for efficient storage or transmission, so they need to be first compressed using a so-called perceptual coding to reduce the amount of data. This process is called source coding. In digital TV broadcasting this compression is one of the tasks of the so-called headend, but such operations are sometimes also performed when the video signals are recorded (reportage camera, home video camera, mobile phone, etc.).

A novel True Random Number Generator (TRNG) based on analog RRAM is developed. For the first time, the proposed TRNG harvests the variation of the pulse number in programming the analog states as the random source, and utilizes the parity of the pulse number to generate random bits. The TRNG throughput reaches >1 Mbit/sec for a single cell. The feasibility for chip-level parallel operation on multiple cells is verified experimentally to further improve the throughput. Excellent stability against temperature variation is also demonstrated. All the generated random bit streams pass the NIST tests across –40 to 125 °C. With an optimized small analog switching window, the endurance problem is significantly relieved as the functionality of TRNG is retained after 1011 incremental switching cycles. Our high-speed and high-reliability TRNG design is compatible with the existing memory block and convenient for circuit implementation, making it suitable for future IoT applications.

Very high throughput satellites (HTS), where single transponders have large bandwidths (in the order of 500 MHz), significantly reduced the cost per Mbit for satellite communications, and are therefore omnipresent for applications like broadband, mobile and enterprise connectivity. An HTS transponder can amplify single or multiple carriers. Single carrier transmission is still the most efficient mode in a nonlinear channel due its lower peak-to-average power ratio. In order to avoid too complex and expensive receivers, the wide carrier (around 500 MHz) is chopped in time slices such that receivers can decode their part of the very wide carrier. This crosslayer technology, applied for single carrier transmission, may bring overhead in some cases, also leading to some inefficiencies. In this paper, we will introduce and explain timeslicing and present a holistic efficiency comparison between single carrier transmission with timeslicing and multi-carrier transmisson without timeslicing, with and without non-linear predistortion. We conclude that Newtec non-linear predistortion (present in Newtec Equalink) with single or multi-carrier transmission outperforms single carrier transmission without non-linear predistortion. In addition, the throughput gain of single carrier transmission with respect to dual (four) carrier transmission is around 6% (9%) for linearized channels, the nowadays standard. Adding Newtec Equalink on top of single carrier transmission yields a total gain around 15% and 20% over dual and four carrier transmission without non-linear predistortion, respectively.

DNA is a promising data storage medium due to its remarkable durability and space-efficient storage. Early bit-to-base transcoding schemes have primarily pursued information density, at the expense however of introducing biocompatibility challenges or at the risk of decoding failure. Here, we propose a robust transcoding algorithm named the “Yin-Yang Codec” (YYC), using two rules to encode two binary bits into one nucleotide, to generate DNA sequences highly compatible with synthesis and sequencing technologies. We encoded two representative file formats and stored them in vitro as 200-nt oligo pools and in vivo as an ~54-kb DNA fragment in yeast cells. Sequencing results show that YYC exhibits high robustness and reliability for a wide variety of data types, with an average recovery rate of 99.94% at 104molecule copies and an achieved recovery rate of 87.53% at 100 copies. In addition, the in vivo storage demonstration achieved for the first time an experimentally measured physical information density of 198.8 EB per gram of DNA (44% of the theoretical maximum for DNA).

International audience; After decennia of developing leading-edge 2D video compression technologies, the Moving Picture Expert Group (MPEG) is currently working on the new era of coding for immersive applications, referred to as MPEG-I, where “I” refers to the “Immersive” aspects. It ranges from 360° video with head-mounted displays to free navigation in 3D space with head-mounted and 3D light field displays. Two families of coding approaches, covering typical industrial workflows, are currently considered for standardization—MultiView + Depth (MVD) Video Coding and Point Cloud Coding—both supporting high-quality rendering at bitrates of up to a couple of hundreds of megabits per second. This paper provides a technical/historical overview of the acquisition, coding, and rendering technologies considered in the MPEG-I standardization activities.

1. Memory Cell 2. Dry Etching 3. Thin Film Insulator 4. Impurity Doping 5. Metalization 6. Crystal Technology 7. SOI Device Technology 8. Lithography 9. Chemical Vapor Deposition 10. Process and Device Simulation

Recent advances in 5G digital communication standard implementations advocate for the use of polar codes for the Enhanced Mobile Broad Band (EMBB) control channels. However, in many cases, implementing efficient hardware decoder over a short duration is very challenging. Specialized knowledge is required to facilitate testing, rapid design iterations and fast prototyping. In this paper, we present a model-based design methodology to generate efficient hardware SC polar decoders from high-level synthesis tools. The abstraction level flexibility is evaluated and generated decoders architectures are compared to competing approaches. It is shown that the fine-tuning of computation parallelism, bit width, pruning level and working frequency enable high throughput decoder designs with moderate hardware complexities. Decoding throughput between 10 to 310 Mbit/s and hardware complexity between 1,000 and 21,000 LUTs are reported for the generated architectures.

True random number generator (TRNG) is of the fundamental guarantees of information security. However, the commercially-available all-electronic TRNGs, no matter whether the thermal-noise-based or the oscillator-based ones, can merely reach the speed of a few Mbit/s due to the very limited entropy source, which is unable to meet the requirements of ultra-high-speed and ultra-large capacity of information propagation or storage. This paper proposes the design and implementation of semiconductor superlattice random number generator (SSL-RNG) by employing semiconductor superlattice chaos as entropy source. We introduce the entropy estimation method to evaluate the raw data from the entropy harvester quantitatively, thus optimized the parameter design of the LFSR-Toeplitz extractor for post-processing. We have also integrated the entropy acquisition circuit into an embedded FPGA-based platform as a standalone design to trade off the performance and cost. The resulting hardware's output passes the NIST standard statistical test with a full entropy throughput above 300 Mbit/s.

Most applications nowadays require protection of their data from tampering to ensure secure transfer of information. At the same time, they need to be secured quickly and within available resources. In this paper, efficient hardware architecture has been designed and implemented for the Advanced Encryption Standard (AES) algorithm based on the Field Programmable Gate Array (FPGA) using High Level Language (HLL). The design focused on the optimal use of available resources, thus iterative looping architecture is suggested to minimize the hardware resources utilization and power consumption. The design is synthesized and simulated using Xilinx ISE 14.7 and ModelSim software, respectively. The implementation is compared with other previous works in terms of area, and power consumption. The results show that the proposed design achieves significant decrease in area (utilize 423 slices) and power consumption (3.68 W). The throughput reaches the value of 2457 Mbit/Sec implemented on Virtex-6 xc6vlx195t-3 of Xilinx device family. This makes the proposed design suitable for applications, where resources are limited.

FPGAs are being used in data center applications in large quantities. Single-event upsets (SEUs) occur more frequently within large-scale deployments of SRAM-based FPGAs. This work estimates the neutron cross section for SEUs in the configuration memory and memory blocks of a 14-nm FinFET Stratix 10 FPGA. SEU data was collected using a custom SEU data collection system. The developed system takes advantage of SEU mitigation features available on the device. The New York City FIT rate for SEUs is estimated to be 3.2 FIT per Mbit for configuration memory and 7.1 FIT per Mbit for memory blocks.

We present for the first time a co-integrated FinFET with vertical nanosheet transistor (VFET) process on a 300 mm silicon wafer for STT-MRAM applications and its related avenues with a holistic design-technology-co-optimization (DTCO) and power-performance-area-cost (PPAC) approach. The STT-MRAM bitcell and a 2 Mbit macro have been optimized and designed to address the viability of the co-integration process and advantages of vertical channel transistors for STT-MRAM selectors. An architectural system simulator GEM5 has been also employed with Polybench workloads to assess energy saving at system-level. In order to enable this co-integration, four extra masks are required, which costs below 10% in embedded chips. A 36% area reduction can be achieved for the STT-MRAM bitcell implemented with VFET selectors. With a UVLT flavor, the STT-MRAM bitcell comprising of 3-nanosheet could deliver the same performance of the 4-fin LVT FinFET selector. A 2 Mbit STT-MRAM macro designed with VFET selector can offer a 17% and a 21% reduction for read access latency and energy per operation respectively, and a 10% for write energy per operation. A 7% energy saving for the STT-MRAM L2 cache using VFET selector has been observed at the system level with Polybench workloads.

Quantum key distribution (QKD) guarantees unconditional security and has thus been intensely studied both from a theoretical and an experimental point of view [1]. However, limitations due to transmission loss and noise are still detrimental for these systems performance in terms of reachable distance and key rates, having so far confined QKD implementations to the use of dedicated channels and hence reduced a successful integration with the classical network, with few exceptions [2–6]. In this work we demonstrate a step forward in the co-existence of QKD with classical bright signals, exploiting a 7.9-km long 37-core heterogeneous multicore fiber (MCF) [7], and a space division multiplexing (SDM) technique to achieve a total of 87 Mbit/s secret key generation rate (SKR) in the finite key scenario with a simultaneous co-propagating classical signal of 10 Gbit/s.

This article discusses the specifics of high voltage power line carrier channels construction with application of new wideband power line carrier equipment with packet switching. It presents distinctive features of W-DPLC systems in comparison with classic high voltage PLC, discusses issues about planning of wideband channels and results of field trials on complex 110 kV line with high frequency bridges and tapping line. Tests showed that W-DPLC systems can provide megabit bit rates, coexist with other PLC channels in conditions of high load of frequency spectrum and work with overlapping attenuation more than 60 dB, what guarantees reliable operation of such channels even in bad weather conditions and ice-crust

Wireless body area network (WBAN)using millimeter wave (mmW)is expected to reduce inter-WBAN interference because of large attenuation, however it is necessary to consider the connectivity of the mmW intra-WBAN communication. We have proposed the toe-hop mmW WBAN in the walking pause and measured on-body propagation losses at 60 GHz. In this paper, we evaluate a channel capacity to show the reliability of the proposed method. Monte carlo simulation shows that the proposed method can ensure the channel capacity of 10 Mbit/s with a probability of more than 99.6% in a walking situation.

Wireless connectivity has become a de-facto standard in daily computer use, both in small office/home office environment and in large business organisations. The beginnings of wireless connectivity started with the 802.11a and b standard, which enabled a theoretical data rate of 54 and 11 Mbit/s. The umbrella organisation Wi-Fi Alliance has decided to use a simplified naming scheme for wireless standards, so the currently widespread standard 802.11n (aggregate rate up to 600 Mbit/s) will now be named Wi-Fi 4, and the standard 802.11ac (aggregate rate up to 7 Gbit/s1) will be called Wi-Fi 5. In addition, Wi-Fi 6 or 802.11ax is in course of preparation and will enable theoretical rates of up to 10 Gbit/s. The answer to the question of whether there is a rationale for switching to Wi-Fi 5 will be provided by measuring the performance of Wi-Fi 4 and Wi-Fi 5 standards according to the following criteria: Wi-Fi signal strength in 2.4 and 5 GHz frequency bands, average throughput – data rate (transmitting and receiving data), maximum throughput and playback of 4K video content in a simulated SOHO environment. Performance ratio (performance per price) is also calculated.

A novel architecture structuring MIMO Detection with a Trellis search is presented. Therefore, several optimizations are explored reducing complexity and increasing efficiency. Implementing orthogonal real-value decomposition outperforms the basic implementation by a factor of 2.7 in terms of area throughput efficiency, preserving a comparable communication performance. This concept also allows suitable scaling towards higher modulation orders and also offers a potential for further architectural scaling. optimizations are applied on algorithmic and architectural level to reduce complexity and increase efficiency. A design space exploration of the sorting subtask is also presented. It achieves the IEEE 802.11n standard’s peak data rate, even for two detector decoder iterations (2 × 720 Mbit=s).