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BiCMOS circuits which can realise the different mathematical operations within a fuzzy system are presented in this paper. To maximise the operating speed of these circuits and increase the packing density, an analog approach is adopted throughout. The initial focus is on the design of circuits to implement fuzzification and intersection. The remainder of the paper focuses on the hardware implementation of implication and defuzzification, thus completing the fuzzy cell library. A major objective of this work is to maintain a design strategy which yields simple circuits so as to minimise cell density. Therefore, the circuits presented are relatively simple but effective with regard to the mathematical functions that they are required to generate within the cell. For example, fuzzification is achieved using the current spike derived from a CMOS inverter during switching. Both intersection and implication are realised using a single MOS transistor operating in the triode region. The remaining circuitry consists mainly of an operational amplifier in the summing mode to realise the function of defuzzification. The complete fuzzy system is simulated and a transfer characteristic is presented and discussed. Keywords: Fuzzy, BiCMOS, fuzzification, intersection, implication, defuzzification

This paper discusses a novel architecture and synapse design for area-efficient hardware implementations of neural networks. The proposed architecture offers an intermediate solution to the on-chip interconnect problem by the introduction of the concept of 'virtual' neurons. Using a previously developed model a significant reduction in silicon area is suggested. The proposed synapse designs represent alternatives to conventional multiplier-based synaptic cells. These synapses, designed for minimal implementation size, include two targeted for analog implementation and one for digital implementation. Training of neural networks based on the proposed synapses has been considered and a modified version of the backprogagation algorithm is discussed. Results of neural network operation based on one of the new synapses are presented. Keywords: Neural network, VLSI, hardware implementation