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We report the performance of 1-eV GaNAsSb-based photovoltaic samples grown on a Si substrate using molecular beam epitaxy at different As/Ga beam equivalent pressure (BEP) ratios. The light current–voltage curve and spectral response of the samples were measured. The sample grown at an As/Ga BEP ratio of 10 showed the highest energy conversion efficiency with an open circuit voltage (VOC) of 0.529 V and a short circuit current density of 17.0 mA/cm2. This measured VOC is the highest ever reported value in GaNAsSb 1-eV photovoltaic cell, resulting in the lowest ever reported Eg/q-VOC of 0.50 eV. The increase in the As/Ga BEP ratio also resulted in an increase in the bandgap-voltage offset value (Eg/q-VOC) and a decrease in quantum efficiency up to As/Ga BEP ratio of 18. Copyright © 2015 John Wiley & Sons, Ltd.

Single-layer antireflective coating (SLARC) materials and design for GaAs1_xPx/Si tandem cells were analyzed by TCAD simulation. We have shown that optimum SLARC thickness is a function of bandgap, thickness, and material quality of top GaAs 1-x P x /Sisubcell. Cells are analyzed for P fractions x = 0, 0.17, 0.29, and 0.37, and ARC materials: Si 3 N 4 , SiO 2 , ITO, 11fO 2 , and Al 2 O 3 . Optimum ARC thickness ranges from 65-75 nm for Si 3 N 4 and ITO to ~100-110 nm for SiO2. Optimum ARC thickness increases with increasing GaAs1_xPx absorber layer thickness and with decreasing P fraction x. Simulations show that optimum GaAs 1-x P x /Siabsorber layer thickness is not a strong function of ARC material, but it increases from 250 nm for x = 0 to1 μm for x = 0.29 and 0.37. For all P fractions, Si 3 N 4 , 11fO 2 , and Al 2 O 3 performed almost equally, while SiO2 and ITO resulted in ~1% and ~2% lower efficiency, respectively. Optimum SLARC thickness increases as the material quality of the top cell increases. The effect of ARC material decreases with decreasing GaAs1_xPx material quality. The maximum efficiencies are achieved for cells with ~1-μm GaAs0.71P0.29 absorber (r = 10 ns): ~26.57% for 75-nm Si 3 N 4 SLARC and 27.62% for 75-nm SiO2/60-nm Si 3 N 4 double-layer ARC.

Strain fields arising from a non-uniform distribution of misfit dislocations in an underlying compositionally graded buffer are shown to be sufficiently strong to modify indium incorporation in III-phosphide light emitting layers. Composition fluctuations ( x In ±0.02) in lattice-mismatched (Al y Ga 1− y ) x In 1− x P thin films with length-scales of 5–10 μm and a broadened light emission spectra are observed. Cathodoluminescence, photoluminescence and wavelength dispersive x-ray spectroscopies are used in this analysis to generate spatial maps of luminescence spectra and element distributions in metal-organic chemical vapor deposition (MOCVD) grown films. It is seen that these fluctuations due to misfit dislocations are hard to eliminate via growth-kinetics alone but can be lowered through the use of miscut substrates or spacer layers between the graded buffer layer and the active layer. A link between crosshatch surface-roughness and group-III atom distribution under group-V rich growth conditions in both AlInP and GaInP films is also demonstrated. In summary, the interaction of the dislocation strain field with the growth surface can affect the optical characteristics of lattice-mismatched LEDs even if the final threading dislocation density is low.

High quality epitaxial growth of GaAsP on SiGe templates would allow access to materials and band gaps that would enable novel, high performance devices on Si. However, GaAsP/SiGe interface engineering has proved to be very complex. In this paper, we explore the effects of strain at the heterovalent interface between GaAsP and SiGe alloys on the overall defect morphology.

Integration of III-V compound (III-V) semiconductors with Si complementary metal-oxide semiconductor (CMOS) has been an area of great interest because of the circuit performance enhancement that can be gained by placing Si and III-V devices in close spatial proximity. The Silicon-on-Lattice-Engineered Substrate (SOLES) platform enables this integration monolithically. The SOLES wafer is a silicon wafer with an embedded template suitable for epitaxial III-V device growth. 1‐3 CMOS devices are fabricated on the surface silicon and III-V devices are built on the template layer in windows. In collaboration with other groups, we have successfully demonstrated differential amplifiers with InP heterojunction bipolar transistors (HBT) and Si CMOS devices on SOLES substrates. 4 In this previous work, Si and III-V contact metallization steps were performed separately in traditional CMOS and III-V infrastructure, respectively. We envision parallel metallization of the CMOS and III-V devices using common CMOS infrastructure, in a manner consistent with Si processing, as a final step toward ultimate monolithic integration. A few key requirements must be considered in choosing the optimal contact structure. Contacting the III-V films through a Si encapsulation layer which fully embeds the III-V device and minimizes exposureofIII-VmaterialstotheCMOSsequencewillcausetheleast disruption to CMOS processes. This Si may be grown in an epitaxial step that is integrated with III-V device growth, streamlining the growth process. Using CMOS-friendly metals and processing steps which parallel those currently found in CMOS processing will also ease the integration. This metal must have a thermal budget of formation that is low to minimize effects on the III-V device structure. But the contact must also be able to withstand the temperatures of Si back-end processing steps (typically temperatures up to 500 ◦ C). Nickel silicide metallurgies, which are standard to CMOS technology, have low thermal budgets of formation and are used in more advanced CMOS processes, are explored in this work for Si-encapsulated III-V ohmic contacts. Carriertransportbetweensilicidesandsemiconductorfilmsoccurs through a tunneling mechanism requiring the silicon-encapsulation layers to be degenerately doped in order to promote tunneling. Tunneling may also occur via mid-gap interface states, which also affects thebandstructure.Inthiswork,weinvokesimilarmethodsforanalyzing our contact structures between nickel silicide and Si-encapsulated III-Vfilms. The effect of mid-gap states could be especially important in these contacts through Si-encapsulated III-V films because the lat

Two approaches for metalorganic chemical vapor deposition (MOCVD)-grown compositionally graded metamorphic buffers on 6° offcut bulk GaAs were investigated. The first approach consisted of tandem graded layers of InGaAs and InGaP with compositional grading of the In concentration. This tandem approach was found to be necessary because phase separation in the InGaAs alloys leads to surface roughening and high threading dislocation density when grading to lattice constants greater than that of In 0.30 Ga 0.70 As. An In x Ga 1− x As graded buffer was grown at 700 °C for low In concentration ( X In =0–0.10) and then the growth temperature was decreased to 450 °C for high In concentration ( X In =0.10–0.30) to suppress the phase separation. The growth temperature was then increased to 650 °C and the graded In y Ga 1− y P system was implemented to continue grading the lattice constant from In 0.30 Ga 0.70 As to InP, which allowed us to achieve InP on 6° offcut GaAs with a threading dislocation density of 7.9×10 6 cm −2 and an RMS surface roughness of 33.0 nm on a 40 μm×40 μm AFM scale. The second approach used GaAsSb alloys with compositional grading of the Sb concentration. Graded mixed-anion GaAsSb alloys grown at 575 °C did not exhibit phase separation, resulting in high quality InP lattice constant films on GaAs without the need to transition to another material system for compositional grading. We demonstrated a GaAsSb alloy on GaAs (with a grading rate of 1.06% strain/μm) lattice-matched to InP with a threading dislocation density of 4.7×10 6 cm −2 and a roughness of 7.4 nm on a 40 μm×40 μm AFM scale. It was further demonstrated that the threading dislocation density of the GaAsSb graded buffer can be lowered to 2.7×10 6 cm -2 with a slower grading rate (0.64% strain/μm).

Si CMOS-based contact metallurgies to III-V compounds will allow parallel interconnection of Si CMOS and III-V devices and promote monolithic integration. In this study, we report the use of nickel silicides to contact n++ GaAs encapsulated with n++ Si. The structure and electrical properties of contacts with varying reaction depths is correlated. Specific contact resistivities lower than 5e-7 ohm-cm2 are measured on NiSi/Si/GaAs structures.

Front end integration of III-V compound semiconductor devices with Si complimentary metal-oxide-semiconductor (CMOS) technology requires the development of commercially viable engineered substrates. The fabrication of engineered substrates currently utilizes technologies such as epitaxy, wafer bonding and layer exfoliation. In this paper we report on the development of GaAs-oninsulator (GaAsOI) structures without the use of Smart Cut technology. Epitaxial GaAs/Ge/GaAs stacks containing an embedded Ge sacrificial release layer were grown with metal-organic chemical vapor deposition (MOCVD) and exhibit both a low defect density as well as surface properties suitable for wafer bonding. A room temperature oxide-oxide bonding process was developed to enable the integration of substrates with a large difference in their coefficients of thermal expansion. The release of the donor substrate and transfer of the GaAs layer onto the handle substrate was realized through room temperature, gas-phase lateral etching of the embedded Ge sacrificial layer by exposure to xenon difluoride (XeF2). This GaAsOI fabrication process is shown to be successful on a small scale, though implementation for the production of commercially-viable large area GaAsOI substrates at full wafer scale is currently limited by the long gas transport distance associated with a wafer-scale lateral etching process. In order to explore possibilities for overcoming this limitation we established a model that identifies the rate limiting processes and discuss potential approaches that will allow for the implementation of our gas phase lateral etching process for the fabrication of large diameter GaAsOI substrates.

Integration of GaP on Si will enable the generation of yellow and green light from Si and also the creation of high efficiency and low cost solar cells based on Si. Despite the lattice-matched condition of GaP on Si, low defect density GaP on Si has not been recently recorded in the literature. Experimental studies of GaP on Si growth have reported that, unlike GaAs on Ge, this system tends to grow with a three-dimensional island morphology with a high density of microstructural defects, including stacking faults, threading dislocations and twins. Si1-xGex is important for accommodating the mismatch between Si and Ge. One can envision a process in which a Si1-xGex graded buffer is grown on a Si wafer to extend the lattice parameter part of the way to GaAs, at which point a lattice-matched GaAsyP1-y is grown on the Si1-xGex surface, followed by tensile grading of the GaAsyP1-y until GaP is reached. In this study, we report about the successful growth of high-quality lattice-matched GaAsyP1-y on Si0.5Ge0.5, Si0.4Ge0.6, and Si0.3Ge0.7 virtual substrates. Identifying the composition where the transition can be made from Si1-xGex to GaAsyP1-y depending on the application is an integral objective of this study. This will provide the flexibility to engineer the lattice constants from Si to Ge and GaP to GaAs while maintaining low threading dislocation density (TDD) and surface morphology suitable for device processing.

We report on a direct epitaxial growth approach for the heterogeneous integration of high-speed III–V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBT) structures were successfully grown on Si-on-lattice-engineered- substrate (SOLES) and Ge-on-insulator-on-Si (GeOI/Si) substrates using molecular beam epitaxy. Structurally, the epiwafers exhibit sharp interfaces and a threading dislocation density of 3.5×10 7 cm −2 as measured by plan-view transmission electron microscopy. HBT devices fabricated on GeOI/Si substrates have current gain of 55–60 at a base sheet resistance of 650–700 Ω/sq, and f t and f max of around 220 GHz. HBT structures with DC and RF performance similar to those grown on lattice-matched InP were also achieved on patterned SOLES substrates with growth windows as small as 15×15 μm 2 . These results demonstrate a promising path of heterogeneous integration and selective placement of III–V devices at arbitrary locations on Si CMOS wafers.

We summarize our work on creating substrate platforms, processes, and devices for the monolithic integration of silicon CMOS circuits with III-V optical and electronic devices. Visible LEDs and InP HBTs have been integrated on silicon materials platforms that lend themselves to process integration within silicon fabrication facilities. We also summarize research on tensile Ge, which could be a high mobility material for III-V MOS, and research on an in-situ MOCVD Al2O3/GaAs process for III-V MOS.

In this paper we present theoretical analysis for upper efficiency limit of a novel 2 terminal dual junction stepcell. Results show that step cell design relaxes bandgap requirements for efficient tandem cell. While conventional tandem cell with optimized bandgap combination (1.64 / 0.96 eV) has the highest efficiency (45.78 %), the step-cell design provides significant efficiency improvement for cells with non-optimized bandgap values. Efficiency upper limit for Si based step-cell with top cell bandgap equal to 1.41 eV (~ GaAs), efficiency upper limit increases from ~21% in conventional tandem cell to 38.7% for optimized step-cell design. Step-cell design provides opportunity for wider selection of materials used in tandem solar cell applications.

We investigate the growth, microstructure and device characteristics of 1.71eV bandgap GaAs0.76P0.24 solar cells grown on Si substrates using SiyGe1−y graded buffers. Our optimized growth conditions suppress defect nucleation at the GaAsP/SiGe heterointerface and enable the demonstration of single junction solar cells with a threading dislocation density of 3.4×106 cm−2, a 3× reduction compared to reported GaAsxP1−x cells grown on Si. The solar cells have high open-circuit voltages (Voc) of 1.22 V, bandgap-voltage offset (Woc) of 0.48 V (representing a 45 mV reduction over prior art). The short-circuit current density (jSC) is 11 mA/cm2 and the fill factor (FF) 82%, under AM1.5G irradiance without an anti-reflection coating (ARC). Integration of an ARC would push these GaAs0.77P0.23 single junction solar cells to >15% efficiency, making them well suited to cascade with a Si solar cell for high efficiency tandem solar cells.

The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device template layer which serves as a seed surface for epitaxial growth of III-V devices. In this work, different approaches for fabricating SOLES wafers comprised of Ge and InP template layers are characterized and InP-based SOLES structures are demonstrated for the first time. Ge-based SOLES are robust for long durations at temperatures up to 915°C and Ge diffusion can be controlled by engineering the oxide isolation layers adjacent to the Ge. InP SOLES structures alleviate lattice and thermal expansion mismatches between the template layer and subsequent device layers. Although allowable processing temperatures for these wafers had been expected to be higher due to the higher melting temperature of InP, high indium diffusion through the SiO[subscript 2] and InP melting actually lead to lower thermal stability. This research elucidates approaches to enhance the process flexibility and wafer integrity of Ge-based and InP-based SOLES., United States. Defense Advanced Research Projects Agency. COSMOS Program, United States. Office of Naval Research (Contract N00014-07-C-0629)

Effect of strained-Si thickness on electrical properties of furnace grown gate oxide has been investigated. Interface state density ( D it ) versus energy characteristics shows that D it increases with decreasing strained-Si thickness, probably due to the presence of Ge at the interface. From conductance measurement, two different types of traps are observed in the gate oxide. In thinner strained-Si samples, the onset of F–N tunneling happens at higher voltages, indicating thicker gate oxide. Gate voltage oscillations were observed during constant current stress under gate injection at low stress current. This sinusoidal characteristics are possibly due to the trapping and detrapping of charges in the oxide.

SiGe-free strained Si on insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced capacitance and improved scalability of thin film silicon on insulator (SOI). We demonstrate fabrication of 20% Ge equivalent strain level SSOI substrates with Si thicknesses of 100 and 400 A by hydrogen-induced layer transfer of strained Si layers from high quality graded SiGe virtual substrates. The substrate properties are excellent: wafer scale strained Si film thickness uniformities are better than 8%, strained Si surface roughnesses are better than 0.5 nm RMS, and robust tensile strain levels are maintained during anneals as long as 80 min at 1100 °C. Fully depleted n-MOSFET electrical results show that biaxial tensile strain, and hence enhanced mobility, is fully maintained in the 400 A 20% SSOI films through the substrate and device fabrication processes, even after a generous FET fabrication thermal budget. Long channel devices exhibit nearly ideal subthreshold slopes of 66 mV/decade and exhibit 112% electron mobility enhancements at Ninv=1×1013 cm−2, identical to devices on bulk strained Si substrates. Furthermore, a photoemission microscopy study was used to confirm that the useable SSOI layer thickness significantly exceeds the critical thickness for fabrication of bulk strained Si FETs without deleterious leakage current effects. The fabrication of epitaxially defined, thin strained Si layers directly on a buried insulator is an ideal platform for future generations of Si-based microelectronics.

Carrier generation lifetime ( τ g ) in strained-Si/SiGe has been investigated using capacitance transient method in MOS structure. Interface properties of thermally grown gate oxide on strained-Si/SiGe has been studied prior to transient capacitance measurements. Average midgap value of interface state density ( D it ) extracted from quasi-static CV measurement is around 2×10 10 to 5×10 10 cm −2 eV −1 for both strained-Si and bulk-Si samples. The observed non-linear behavior of capacitance transient characteristics for strained-Si/SiGe heterostructure are due to the carrier confinement in the potential wells caused by virtue of the valence band and conduction band discontinuities. Generation lifetime in strained-Si and SiGe buffer layer estimated from the segments of Zerbst plot having different slopes. The value of generation lifetime in strained-Si, SiGe buffer and co-processed bulk-Si is ranges from 120 to 170 μs, 20 to 90 μs and 177 μs, respectively.

This paper studies the effect of the strained silicon thickness on the characteristics of strained silicon MOSFETs on SiGe virtual substrates. NMOSFETs were fabricated on strained silicon substrates with various strained silicon thicknesses, both above and below the strained silicon critical thickness. The low field electron mobility and subthreshold characteristics of the devices were measured. Low field electron mobility is increased by about 1.8 times on all wafers and is not significantly degraded on any of the samples, even for a strained silicon thickness far greater than the critical thickness. From the subthreshold characteristics, however, it is shown that the off-state leakage current is greatly increased for the devices on the wafers with a strained silicon thickness that exceeds the critical thickness. The mechanism of the leakage was examined by using photon emission microscopy. Strong evidence is shown that the leakage mechanism is source/drain electrical shorting caused by enhanced dopant diffusion near misfit dislocations.

In order to study the luminescent efficiency of InGaAs quantum wells on Si via SiGe interlayers, identical In0.2Ga0.8As quantum well structures with GaAs and Al0.25Ga0.75As cladding layers were grown on several substrates by an atmospheric metalorganic vapor deposition system. The substrates used include GaAs, Si, Ge, and SiGe virtual substrates. The SiGe virtual substrates were graded from Si substrates to 100% Ge content. Because of the small lattice mismatch between GaAs and Ge (0.07%), high-quality GaAs-based thin films with threading dislocation densities

The effects of growth temperature, substrate offcut, and dislocation pileup formation on threading dislocation density (TDD) in compositionally graded SiGe buffers are explored. To investigate dislocation glide kinetics in these structures, a series of identical samples graded to 30% Ge were grown at temperatures between 650 and 900 °C on (001)-, (001) offcut 6° towards an in-plane 〈110〉-, and (001) offcut 6° towards an in-plane 〈100〉-oriented Si substrates. The field threading dislocation density (field TDD) in the on-axis samples varied exponentially with temperature, from 3.7×106 cm−2 at 650 °C to 9.3×104 cm−2 at 900 °C. The activation energy for dislocation glide in this series, calculated from the evolution of field TDD with growth temperature, was 1.38 eV, much lower than the expected value for this composition. This deviation indicates that strain accumulating during the grading process at low growth temperatures is forcing further dislocation nucleation, resulting in a deviation from pure glide-limited relaxation. The TDD of samples grown on offcut substrates exhibited a more complicated temperature dependence, likely because films grown on offcut substrates have an increased tendency towards saturation in dislocation reduction reactions at high temperature. Dislocation reduction processes were further explored by initiating compositional grading up to 15% Ge at 650 °C and continuing the grade to 30% Ge at 900 °C. The low temperature portion of this growth provided an excess concentration of threading dislocations which could subsequently be annihilated during the high temperature portion of the growth, enabling a comparison of reduction rates for different substrate offcuts. Combining these results with threading dislocation densities in a variety of other samples, a complete picture of strain relaxation kinetics in compositionally graded SiGe/Si emerges. Generally, strain relaxation in these structures is limited by dislocation glide, and threading dislocation densities are independent of final Ge content. However, we theorize that dislocation pileup formation inhibits the strain relaxation process and is therefore accompanied by a rise in field threading dislocation density. Based on these results, we now have a predictive model for TDD in compositionally graded SiGe/Si over a wide range of growth conditions.

III-V solar cells on Si substrates are of interest for space photovoltaics since this would combine high performance space cells with a strong, lightweight and inexpensive substrate. However, the primary obstacles blocking III-V/Si cells from achieving high performance to date have been fundamental materials incompatabilities, namely the 4% lattice mismatch between GaAs and Si, and the large mismatch in thermal expansion coefficient. In this paper, we report on the molecular beam epitaxial (MBE) growth and properties of GaAs layers and single junction GaAs cells on Si wafers which utilize compositionally graded GeSi Intermediate buffers grown by ultra-high vacuum chemical vapor deposition (UHVCVD) to mitigate the large lattice mismatch between GaAs and Si. Ga As cell structures were found to incorporate a threading dislocation density of 0.9-1.5 x 10 (exp 6) per square centimeter, identical to the underlying relaxed Ge cap of the graded buffer, via a combination of transmission electron microscopy, electron beam induced current, and etch pit density measurements. AlGaAs/GaAs double heterostructures wre grown on the GeSi/Si substrates for time-resolved photoluminescence measurements, which revealed a bulk GaAs minority carrier lifetime in excess of 10 ns, the highest lifetime ever reported for GaAs on Si. A series of growth were performed to ass3ss the impact of a GaAs buffer to a thickness of only 0.1 micrometer. Secondary ion mass spectroscopy studies revealed that there is negligible cross diffusion of Ga, As and Ge at he III-V/Ge interface, identical to our earlier findings for GaAs grown on Ge wafers using MBE. This indicates that there is no need for a buffer to "bury" regions of high autodopjing,a nd that either pn or np configuration cells are easily accomodated by these substrates. Preliminary diodes and single junction Al Ga As heteroface cells were grown and fabricated on the Ge/GeSi/Si substrates for the first time. Diodes fabricated on GaAs, Ge and Ge/GeSi/Si substrate show nearly identical I-V characteristics in both forward and reverse bias regions. External quantum efficiencies of AlGaAs/GaAs cell structures grown on Ge/GeSi/Si and Ge substrates demonstrated nearly identical photoresponse, which indicates that high lifetimes, diffusion lengths and efficient minority carrier collection is maintained after complete cell processing.

Lattice-mismatched relaxed graded composition layers in the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems have recently been created with unprecedented high quality due to advances in understanding the impact of epitaxial growth conditions. The key process–property correlation is the impact of growth conditions on dislocation dynamics. In particular, the SiGe/Si system has recently been well explored experimentally, allowing the dislocation dynamic model to be tested. We show that the dislocation dynamics model is in general applicable to graded layers in any material system as long as dislocation flow is not impeded. In the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems, with moderately dislocated graded layers, these mechanisms can be absent under appropriate growth conditions. However, in all systems, threading dislocation impediments eventually occur under continued deformation through continued grading. The mechanism in SiGe/Si is related to the impediment of dislocation flow from the surface morphology and strain-fields from misfit dislocations. In the III–V systems, we observe that a planar defect, referred to here as branch defects, can form under a wide range of growth conditions, and these defects will lead to inhibited dislocation flow. The quantitative nature of these effects can be empirically modeled with the same dislocation dynamic model by incorporating a composition-dependent change in the effective strain experienced by threading dislocations during grading-induced deformation.

Recent advances in the understanding and control of threading dislocations in substantially relaxed SiGe buffer layers on Si are presented. A model for threading dislocation flow in relaxed graded SiGe buffers is used to determine the potential lower limit of threading dislocation density in relaxed SiGe buffers. Greater densities than expected from the model are seen in relaxed graded alloys with final concentrations greater than 50%. We show that the culprits of the higher threading dislocation density are threading dislocation pile-ups. Observation of early development of pile-ups confirms that inhomogeneous misfit dislocation densities in the graded buffer form regions of more severe crosshatch on the surface that impede dislocation flow. By using chemomechanical planarization (CMP), deleterious pile-up formation can be avoided, and previously formed pile-ups can be destroyed by regrowth of a graded layer. Experiments with CMP and regrowth of graded layers suggest that dislocation annihilation can be effective at reducing threading dislocation densities to densities of the order expected by the model. High quality Ge on Si layers created with the CMP process were used as templates to grow high quality GaAs on Si with strong room temperature photoluminescence and record minority carrier lifetime.

We have measured the lifetimes of two zone-center longitudinal acoustic phonon modes, at 320 and 640 GHz, in a 14 nm GaAs/2 nm AlAs superlattice structure. By comparing measurements at 296 and 79 K we separate the intrinsic contribution to phonon lifetime determined by phonon–phonon scattering from the extrinsic contribution due to defects and interface roughness. At 296 K, the 320 GHz phonon lifetime has approximately equal contributions from intrinsic and extrinsic scattering, whilst at 640 GHz it is dominated by extrinsic effects. These measurements are compared with intrinsic and extrinsic scattering rates in the superlattice obtained from first-principles lattice dynamics calculations. The calculated room-temperature intrinsic lifetime of longitudinal phonons at 320 GHz is in agreement with the experimentally measured value of 0.9 ns. The model correctly predicts the transition from predominantly intrinsic to predominantly extrinsic scattering; however the predicted transition occurs at higher frequencies. Our analysis indicates that the 'interfacial atomic disorder' model is not entirely adequate and that the observed frequency dependence of the extrinsic scattering rate is likely to be determined by a finite correlation length of interface roughness., United States. Dept. of Energy. Office of Basic Energy Sciences (Award DE-FG02-00ER15087), United States. Dept. of Energy. Office of Basic Energy Sciences (Award DE-SC0001299/DE-FG02-09ER46577)

Strained silicon-on-insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced parasitic capacitance and improved MOSFET scalability of thin-film SOI. We demonstrate fabrication of highly uniform SiGe-free SSOI wafers with 20% Ge equivalent strain and report fully depleted n-MOSFET results. We show that enhanced mobility is maintained in strained Si films transferred directly to SiO/sub 2/ from relaxed Si/sub 0.8/Ge/sub 0.2/ virtual substrates, even after a generous MOSFET fabrication thermal budget. Further, we find the usable strained-Si thickness of SSOI significantly exceeds the critical thickness of strained Si/SiGe without deleterious leakage current effects typically associated with exceeding this limit.

SiGe-free strained Si on insulator substrates were fabricated by wafer bonding and hydrogen-induced layer transfer of strained Si grown on bulk relaxed Si0.68Ge0.32 graded layers. Raman spectroscopy shows that the 49-nm thick strained Si on insulator structure maintains a 1.15% tensile strain even after SiGe layer removal. The strain in the structure is thermally stable during 1000 °C anneals for at least 3 min, while more extreme thermal treatments at 1100 °C cause slight film relaxation. The fabrication of epitaxially defined, thin strained Si layers directly on a buried insulator forms an ideal platform for future generations of Si-based microelectronics.

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.

We measure the lifetime of the zone-center 340 GHz longitudinal phonon mode in a GaAs-AlAs superlattice excited and probed with femtosecond laser pulses. By comparing measurements conducted at room temperature and liquid nitrogen temperature, we separate the intrinsic (phonon-phonon scattering) and extrinsic contributions to phonon relaxation. The estimated room temperature intrinsic lifetime of 0.95 ns is compared to available calculations and experimental data for bulk GaAs. We conclude that ∼0.3 THz phonons are in the transition zone between Akhiezer and Landau-Rumer regimes of phonon-phonon relaxation at room temperature., United States. Dept. of Energy. Office of Basic Energy Sciences (Award DE-SC0001299), United States. Dept. of Energy (Grant DE-FG02-00ER15087)

We present recent results on the direct heterogeneous integration of InP HBTs and Si CMOS on a silicon template wafer or SOLES (Silicon On Lattice Engineered Substrate). InP HBTs whose performance are comparable to HBTs on the native InP substrates have been repeatedly achieved. 100% heterogeneous interconnect yield has been achieved on daisy chain test structures with CMOS-InP HBT spacing (interconnect length) as small as 2.5um. In DARPA COSMOS Phase 1 we designed and fabricated a differential amplifier that met the program Go/NoGo metrics with first pass design success. As the COSMOS Phase 2 demonstration vehicle we designed and fabricated a low power dissipation, high resolution, 500MHz bandwidth digital-to-analog converter (DAC).

The methodology for a heterodyned laser-induced transient thermal grating technique for non-contact, non-destructive measurements of thermal transport in opaque material is presented. Phase-controlled heterodyne detection allows us to isolate pure phase or amplitude transient grating signal contributions by varying the relative phase between reference and probe beams. The phase grating signal includes components associated with both transient reflectivity and surface displacement whereas the amplitude grating contribution is governed by transient reflectivity alone. By analyzing the latter with the two-dimensional thermal diffusion model, we extract the in-plane thermal diffusivity of the sample. Measurements on a 5 {\mu}m thick single crystal PbTe film yielded excellent agreement with the model over a range of grating periods from 1.6 to 2.8 {\mu}m. The measured thermal diffusivity of 1.3 \times 10-6 m2/s was found to be slightly lower than the bulk value., Comment: 19 pages, 6 figures

Minority carrier lifetimes and interface recombination velocities for GaAs grown on a Si wafer using compositionally graded GeSi buffers have been investigated as a function of GaAs buffer thickness using monolayer-scale control of the GaAs/Ge interface nucleation during molecular beam epitaxy. The GaAs layers are free of antiphase domain disorder, with threading dislocation densities measured by etch pit density of 5×105–2×106 cm−2. Analysis indicates no degradation in either minority carrier lifetime or interface recombination velocity down to a GaAs buffer thickness of 0.1 μm. In fact, record high minority carrier lifetimes exceeding 10 ns have been obtained for GaAs on Si with a 0.1 μm GaAs buffer. Secondary ion mass spectroscopy reveals that cross diffusion of Ga, As, and Ge at the GaAs/Ge interface formed on the graded GeSi buffers are below detection limits in the interface region, indicating that polarity control of the GaAs/Ge interface formed on GeSi/Si substrates can be achieved.

The thermal budget/integration challenges for SOLES have been investigated. A process window has been found that allows for the successful demonstration of a monolithically integrated III-V/Si differential amplifier. A method of increasing the integration flexibility of SOLES by introducing SiN x interlayers has been demonstrated. Future work will explore the increased thermal budget/integration flexibility of SOLES provided by incorporating embedded GaAs layers.

We present results on the direct monolithic integration of III–V devices and Si CMOS on a silicon substrate. InP HBTs (0.5 × 5 um2 emitter) with ft and fmax ≫ 200GHz were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). A BCB based multilayer interconnect process was used to interconnect the InP HBT and Si CMOS to create a differential amplifier demonstration circuit. The heterogeneously integrated differential amplifier serves as the building block for high speed, low power dissipation mixed signal circuits such as ADCs and DACs.

We present results on the direct monolithic integration of III–V devices and Si CMOS on a silicon substrate. Through optimization of device fabrication and material growth processes III–V devices with electrical performance comparable to devices grown on native III–V substrates were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). While the results presented here are for InP HBTs, our direct heterogeneously integration approach is equally applicable to other III–V electronic (FETs, HEMTs) and opto-electronic (photodiodes, VSCLS) devices and opens the door to a new class of highly integrated, high performance, mixed signal circuits.

We report on a direct epitaxial growth approach for the heterogeneous integration of high speed III-V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBTs) structures were successfully grown on patterned Si-on-Lattice-Engineered-Substrate (SOLES) substrates using molecular beam epitaxy. DC and RF performance similar to those grown on lattice-matched InP were achieved in growth windows as small as 15×15μm2. This truly planar approach allows tight device placement with InP-HBTs to Si CMOS transistors separation as small as 2.5 μm, and the use of standard wafer level multilayer interconnects. A high speed, low power dissipation differential amplifier was designed and fabricated, demonstrating the feasibility of using this approach for high performance mixed signal circuits such as ADCs and DACs.

MBE growth of InP-based HBTs on GeOI/Si substrates is described. A GaAs buffer is nucleated on the GeOI; then a graded InAlAs metamorphic buffer transitions the lattice constant to InP. TEM shows minimal anti-phase boundaries and limited dislocations propagating into the device layers. Large area DC parameters are similar to LM HBTs grown on InP. Small area devices exhibit peak current gain cutoff frequency (ft) of 170 GHz at 2 mA/mum2 nominal collector current density. Initial work involving selective epitaxial growth on patterned Ge substrates for future integration is also discussed.

Our direct growth approach of integrating compound semiconductors (CS) and silicon CMOS is based on a unique silicon template wafer with an embedded CS template layer of Germanium (Ge). It enables selective placement of CS devices in arbitrary locations on a Silicon CMOS wafer for simple, high yield, monolithic integration and optimal circuit performance. HBTs demonstrate a peak current gain cutoff frequency ft of 170GHz at a nominal collector current density of 2mA/μm2. To the best of our knowledge this represents the first demonstration of an InP-based HBT fabricated on a silicon wafer.

InxGa1−xAs structures with compositionally graded buffers were grown with organometallic vapor phase epitaxy on GaAs substrates and characterized with plan-view and cross-sectional transmission electron microscopy, atomic force microscopy, and x-ray diffraction. The results show that surface roughness experiences a maximum at growth temperatures where phase separation occurs in InxGa1−xAs. The strain fields from misfit dislocations induce this phase separation in the 〈110〉 directions. At growth temperatures above and below this temperature, the surface roughness is decreased significantly; however, only growth temperatures above this regime ensure nearly complete relaxed graded buffers with the most uniform composition caps. With the optimum growth temperature for grading InxGa1−xAs determined to be 700 °C, it was possible to produce In0.33Ga0.67As diode structures on GaAs with threading dislocation densities

An 86% electron mobility improvement and over 20% I/sub dn-sat/ enhancement were demonstrated for a 70 nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained-Si process delivered 95% higher inverter peak-current and a 2.2 ps reduction in ring oscillator delay for the same drive current. Strained and bulk CMOS featured equivalent gate leakage through a 16 /spl Aring/ nitrided oxide, which remained the dominant leakage source despite dislocation-induced junction leakage observed on strained-Si wafers. Self-heating of strained-Si CMOS due to the low thermal conductivity SiGe virtual substrate reduces I/sub dn-sat/ by 7% during DC operation.

The properties of InAsxP1−x compositionally graded buffers grown by metal organic chemical vapor deposition are investigated. We report the effects of strain gradient (e/thickness), growth temperature, and strain initiation sequence (gradual or abrupt strain introduction) on threading dislocation density, surface roughness, epi-layer relaxation, and tilt. We find that gradual introduction of strain causes increased dislocation densities (>106/cm2) and tilt of the epi-layer (>0.1°). A method of abrupt strain initiation is proposed which can result in dislocation densities as low as 1.01 × 105 cm−2 for films graded from the InP lattice constant to InAs0.15P0.85. A model for a two-energy level dislocation nucleation system is proposed based on our results.

The physical origin of the crosshatch electrical activity in relaxed GeSi films was studied using a near-field scanning optical microscope (NSOM). The contrast and patterns in the near-field photocurrent images depend on the polarization direction of the NSOM light. These results rule out composition nonuniformity, junction depth variation, and scanning artifacts as dominant sources of the contrast. Numerical calculations show that local changes in band structure due to strain fields of the misfit dislocations are responsible for the experimental observations.

The realization of monolithic optical interconnects by integration of III-V materials with conventional Si circuitry has long been hindered by materials incompatibilities (i.e. lattice mismatch and heterovalent interface) and practical processing constraints. We have demonstrated successful integration of hetero-epitaxially grown InGaAs/Si diodes with an n-well CMOS process on (001) Si offcut 6 degrees towards [110]. The In0.15Ga0.85As/InxGa1- xAs/GaAs/Si diodes were grown by atmospheric pressure organo-metallic chemical vapor deposition (OMCVD) and features a room temperature R0A product of 20,000 ohm-cm2. No degradation of PMOS or NMOS transistor characteristics was detected upon integration of the III-V devices. Further improvement of III-V/Si device characteristics are anticipated in future efforts by incorporating relaxed, compositionally- graded Ge/GexSi1-x/Si with low threading dislocation densities (approximately 2 X 106/cm2) to bridge the gap in lattice constants between Si and GaAs. Recent progress towards this end includes the suppression of antiphase disorder during GaAs growth on Ge/GexSi1-x/Si by OMCVD and strong room temperature photoluminescence from In0.20Ga0.80As QW test structures on GaAs/GexSi1- x/Si at 920 nm.

InxGa1−xAs structures with compositionally graded buffers were grown by metal-organic vapor phase epitaxy (MOVPE) on GaAs substrates and characterized with plan-view and cross-sectional transmission electron microscopy (PV-TEM and X-TEM), atomic force microscopy (AFM), and x-ray diffraction (XRD). The results show that surface roughness experiences a maximum at growth temperatures where phase separation occurs in InxGa1−xAs. The strain energy due misfit dislocations in the graded buffer indirectly influences phase separation. At growth temperatures above and below this temperature, the surface roughness is decreased significantly; however, only growth temperatures above this regime ensure nearly complete relaxed graded buffers with the most uniform composition caps. With the optimum growth temperature for grading InxGa1−xAs determined to be 700°C, it was possible to produce In0.33Ga0.67As diode structures on GaAs with threading dislocation densities < 8.5 × 106/cm2

We have designed and developed 1, 16, 256, and 512 element linear monolithic InGaAs-on-silicon infrared detector array for the 1-3 micrometers SWIR band. A methodology of monolithically integrating InGaAs photodetectors and high density complex CMOS readout electronics all on a single silicon substrate has been developed. The innovation consists of an improved 'selective' epitaxial technique that significantly reduces the misfit dislocation density caused by the severe lattice mismatch between the InxGa1-xAs photodetector's absorption region and the silicon substrate. The individual pixel size of (40 X 40) and (80 X 80) micrometers 2 exhibits room temperature RoA product of 40 to 45 (Omega) - cm2. The InGaAs photodetectors are operated at a zero bias voltage to eliminate leakage current integration, reduce the 1/f noise, and maintain a uniform bias for light detection. The CMOS readout circuitry for each individual pixel consists of an integrating pre-amplifier, a CDS signal processor, and a voltage to current converter. The column scanner for the linear array is a D type shift register with a master clear signal reset once per frame. The master clock signal shifts the bit through the registers one column per clock cycle. When a pixel is selected, the output signal at the voltage to current converter is coupled to a transimpedance amplifier. This amplifier drives the line capacitance of the output bus line to achieve 25 MHz output speed. Power dissipation of less than 100 mW has been demonstrated for 10 MHz operation.© (1997) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

InxGa1−xAs structures with compositionally graded buffers were grown with organometallic vapor phase epitaxy (OMVPE) on GaAs substrates and characterized with plan-view and cross-sectional transmission electron microscopy (PV-TEM and X-TEM), atomic force microscopy (AFM), and x-ray diffraction (XRD). The results show that surface roughness experiences a maximum at growth temperatures where phase separation occurs in In.Gal.,As. The strain fields from misfit dislocations induce this phase separation in the directions. At growth temperatures above and below this temperature, the surface roughness decreases significantly; however, only growth temperatures above this regime ensure nearly complete relaxed graded buffers with the most uniform composition caps. With the optimum growth temperature for grading InxGa1−x,As determined to be 700 °C, it was possible to produce In0.33Ga0.67As diodes on GaAs with threading dislocation densities < 8.5 × 106/cm2.

Direct-bandgap InAlP alloy has the potential to be an active material in nitride-free yellow-green and amber optoelectronics with applications in solid-state lighting, display devices, and multi-junction solar cells. We report on the growth of high-quality direct-bandgap InAlP on relaxed InGaAs graded buffers with low threading dislocation densities. Structural characterization reveals phase-separated microstructures in these films which have an impact on the luminescence spectrum. While similar to InGaP in many ways, the greater tendency for phase separation in InAlP leads to the simultaneous occurrence of compositional inhomogeneity and CuPt-B ordering. Mechanisms connecting these two structural parameters are presented as well as results on the effect of silicon and zinc dopants on homogenizing the microstructure. Spontaneous formation of tilted planes of phase-separated material, with alternating degrees of ordering, is observed when InAlP is grown on vicinal substrates. The photoluminescence peak-widths of these films are actually narrower than those grown on exact (001) substrates. We find that, despite phase-separation, ordered direct-bandgap InAlP is a suitable material for optoelectronics.

In this paper, we demonstrate high electron mobility In0.53Ga0.47As quantum-well metal oxide semiconductor field effect transistor (MOSFET) structures. The Al2O3 (gate dielectric)/ In0.53Ga0.47As-In0.52Al0.48As (barrier)/In0.53Ga0.47As (channel) structures were fabricated, and the mobility was obtained by Hall measurements. The structures with in-situ chemical vapor deposition (CVD) Al2O3 displayed higher mobility than identical structures fabricated with in situ atomic layer deposition Al2O3, which indicates that CVD process resulted in a lower Al2O3/In0.53Ga0.47As interfacial defect density. A gate bias was applied to the structure with CVD Al2O3, and a peak mobility of 9243 cm2/V s at a carrier density of 2.7 × 1012 cm−2 was demonstrated for the structure with a 4 nm In0.53Ga0.47As-In0.52Al0.48As barrier. A model based on internal phonon scattering and interfacial defect coulomb scattering was developed to explain the experimental data and predict the mobility of In0.53Ga0.47As MOSFET structures.

High quality epitaxial germanium (Ge) thin films grown on lattice matched and mismatched III-V compound may lead to development of new electronic and optoelectronic devices. Understanding the doping and electronic properties of these Ge thin films is the first step in this development. In this paper, we report on high-quality epitaxial Ge thin films grown on GaAs and AlAs by metal-organic chemical vapor deposition. Cross-sectional transmission electron microscopy and atomic force microscopy reveal the high structural quality of the Ge thin films. Using photoluminescence, secondary ion mass spectrometry, and spreading resistance analysis, we investigated the unintentional doping characteristics of the fabricated Ge-on-III-V thin films. We found that arsenic (n-type doping) concentration is determined by the background partial pressure of volatile As-species (e.g., As2 and As4), which incorporate into the Ge thin films via gas phase transport during the growth. Group III element (p-type doping) incorporatio...