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In this work, hafnium zirconium oxide (HZO)-based 100 × 100 nm2 ferroelectric tunnel junction (FTJ) devices were implemented on a 300 mm wafer platform, using a baseline 65 nm CMOS process technology. FTJs consisting of TiN/HZO/TiN were integrated in between metal 1 (M1) and via 1 (V1) layers. Cross-sectional transmission electron microscopy and energy dispersive x-ray spectroscopy analysis confirmed the targeted thickness and composition of the FTJ film stack, while grazing incidence, in-plane x-ray diffraction analysis demonstrated the presence of orthorhombic phase Pca21 responsible for ferroelectric polarization observed in HZO films. Current measurement, as a function of voltage for both up- and down-polarization states, yielded a tunneling electroresistance (TER) ratio of 2.28. The device TER ratio and endurance behavior were further optimized by insertion of thin Al2O3 tunnel barrier layer between the bottom electrode (TiN) and ferroelectric switching layer (HZO) by tuning the band offset between HZO and TiN, facilitating on-state tunneling conduction and creating an additional barrier layer in off-state current conduction path. Investigation of current transport mechanism showed that the current in these FTJ devices is dominated by direct tunneling at low electric field ( E 0.4 MV/cm). The modified FTJ device stack (TiN/Al2O3/HZO/TiN) demonstrated an enhanced TER ratio of ∼5 (2.2× improvement) and endurance up to 106 switching cycles. Write voltage and pulse width dependent trade-off characteristics between TER ratio and maximum endurance cycles (Nc) were established that enabled optimal balance of FTJ switching metrics. The FTJ memory cells also showed multi-level-cell characteristics, i.e., 2 bits/cell storage capability. Based on full 300 mm wafer statistics, a switching yield of >80% was achieved for fabricated FTJ devices demonstrating robustness of fabrication and programming approach used for FTJ performance optimization. The realization of CMOS-compatible nanoscale FTJ devices on 300 mm wafer platform demonstrates the promising potential of high-volume large-scale industrial implementation of FTJ devices for various nonvolatile memory applications.

Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.

Limitations related to the von Neumann bottleneck have resulted in novel circuits and architectures, including designs that utilize Resistive Random Access Memory (ReRAM) as nonvolatile memory (NVM) devices. ReRAM implemented with hafnium oxide (HfO 2 ) is a strong candidate for such applications. The non-volatility of these devices and their amenability to compute in memory functionality makes them ideal for neuromorphic applications, deep learning, and mathematical accelerator circuits (e.g. Vector Matrix Multiplication - VMM). However, these devices suffer from stochastic switching variability that currently limits their usage and performance. To realize the full potential of these devices, reliability analysis is required. In this work, a reliability study was performed using previously developed a 65 nm CMOS/Memristor process on a 300 mm wafer platform. To address the influence of switching compliance current on the variability of Low Resistance State (LRS) and High Resistance State (HRS), a total of 23 different compliance current values were implemented. The effects of temperature on device performance was also measured.

In this work, we have improved switching reliability of Hafnium Oxide (HfO 2 ) based CMOS integrated RRAM devices by tuning Atomic Layer Deposition (ALD) Co-reactant pulse time for HfO 2 switching layer deposition. Three different pulse times for H 2 O vapor pulses were chosen for this split: standard pulse time, 1.5X pulse time and 5X pulse time. Based on full wafer device testing results, the 5X pulse time RRAM devices showed higher mean forming voltages attributed to lower leakage current density. Additionally, 1T1R cells fabricated with 5X cycle time showed more than 2X improvement in memory window and significant reduction in HRS switching variability. We also report $\gt 95$% switching yield and a sigma of $\lt 0.5$ for cell-to-cell switching variability based on over 450 tested 1T1R devices across full 300 mm wafers, demonstrating the robustness of our process.

In this work, we have addressed cycle to cycle switching variability by modifying a key step in CMOS integrated RRAM devices fabrication, namely the atomic layer deposition (ALD) process used to deposit the HfO 2 switching layer. Two different HfO 2 ALD processes were utilized, one with an organic-based precursor, the other with a chlorine-based precursor. The trade-off between memory window (MW) and variability in the high resistance state (HRS) for RRAM cells was investigated with respect to compliance currents and reset voltages for multiple devices using both ALD precursors. The RRAM devices fabricated with the Cl-based precursor showed significant improvement in their MW/HRS resistance variability trade-off, compared to devices fabricated with the organic-based precursor over a range of compliance currents (150 μΑ to 450 μΑ) and reset voltages (−1.3V to −1.7V). Additionally, the MW shows stronger correlation with resistance variability as a function of reset voltage, mostly due to the significant change in average HRS values. To gain a statistically significant comparison, all 64 1 Transistor 1 RRAM (1T1R) cells in an 8×8 RRAM array were tested on a center die on wafers processed using both ALD precursors. Based on those 64 tested 1T1R cells, we demonstrated more than 80% switching yield for the Cl precursor HfO 2 based RRAM devices, as compared to 38% for the organic precursor devices. Additionally, 1T1R RRAM arrays fabricated using the Cl-based precursor showed more than 2× improvement in MW versus those fabricated using the organic-based precursor.

A simplified voltage stability analysis method is to use a static Thevenin equivalent to represent the electrical connection to a load center. Assuming fixed values of the Thevenin voltage and reactance, a power-voltage ( $PV$ ) curve analysis can be performed to find the voltage collapse point and stability margin. This paper proposes a method to compute the static Thevenin equivalent voltage and reactance of a power system using measured data. The method is validated with simulated PMU data and with 24-hour SCADA data at a wind hub on a medium voltage transmission system in the US western system. For the wind hub, the Thevenin equivalent parameters are used to compute the maximum power transfer capability of the wind hub as constrained by voltage stability. Then the method is extended to online application by using short data windows and forgetting factors.

This paper provides a method to estimate Thevenin equivalent models for voltage stability analysis of a wind hub with about 600 MW of rated generation. The estimation uses 24-hour SCADA data on two medium voltage transmission lines. The estimation is based on a recently developed method whose objective is to find, from long data records, a fixed Thevenin reactance value that yields a mostly fixed Thevenin voltage. This method is reliable as it does not perform curve fitting through data points that may be noisy and exhibit little variations. The load bus voltage calculated from the estimated Thevenin parameters matches well with the measured load bus voltage.

We introduce a data analysis methodology for multifrequency charge-pumping (CP) measurements, which allows extracting both spatial and energy profiles of the CP-active traps in the gate dielectrics along with the defect energy characteristics. The analysis is based on the charge trapping/detrapping model accounting for carriers tunneling between the substrate and the oxide traps and multiphonon-assisted structural trap relaxation associated with charge carrier localization in the trap. Comparison of the spatial and energy trap distribution profiles obtained from CP data collected on a set of high-k dielectric gate stacks of different thicknesses facilitate the calibration of the model parameters. Extraction of the bulk trap characteristics, including trap ionization and relaxation energies, extends the utility of the CP technique from quantifying defect density toward identifying the nature of defects in the dielectric.

Spatial and temporal variability of HfOx-based resistive random access memory (RRAM) are investigated for manufacturing and product designs. Manufacturing variability is characterized at different levels including lots, wafers, and chips. Bit-error-rate (BER) is proposed as a holistic parameter for the write cycle resistance statistics. Using the electrical in-line-test cycle data, a method is developed to derive BERs as functions of the design margin, to provide guidance for technology evaluation and product design. The proposed BER calculation can also be used in the off-line bench test and build-in-self-test (BIST) for adaptive error correction and for the other types of random access memories., Comment: 4 pages. Memory Workshop (IMW), 2015 IEEE International