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This article explores the passivity properties of a dc–dc converter's unterminated all-port MIMO admittance matrix, for analyzing and preventing the converter's destabilizing impact in grid-connecting (interlinking) scenarios with an arbitrary, even meshed, termination (grid impedance). In addition to the passivity properties of the converter's unterminated input and output self admittances, the coupling passivity property is examined, which accounts for the possible destabilizing impact of port-coupling. The dependence of these properties on the control loop parameters is exemplified using a current-controlled buck converter. Examples of two techniques for enhancing a converter's all-port MIMO admittance passivity, by active damping impedance emulation and multisampled pulse width modulation, are examined and shown to be effective. The proposed methodology is validated both in frequency and time domain, using control hardware-in-the-loop simulations, as well as experimentally, using a laboratory prototype.

This article introduces a power controller for three-phase inverters in microgrids that can be used in three-phase three-wire and three-phase four-wire systems. The controller enables active and reactive power tracking and unbalanced current control during grid-tied operation, while also allowing seamless transitions into islanded operation. The proposal is motivated by the compelling need in forthcoming power-electronics-dominated grids to provide ancillary services for the main grid and to support grid-forming functionalities for the microgrid, especially in case of islanded operation. The control is developed on the symmetrical components framework. Power tracking is achieved by dedicated control loops that, exploiting $P$$-$$f$ and $Q$$-$$V$ droop laws applied on positive-sequence powers, accommodate output-power control during grid-tied operation as well as grid-forming capabilities during islanded operation. The controller also includes synchronous $dq$-frame control for negative-sequence current regulation for providing unbalanced current compensation. The proposed solution addresses the challenge of simultaneously providing concurrent grid-tied control features, such as output power tracking, during grid-tied operation as well as grid-forming capabilities during islanded operation. The related challenge stems from the intrinsically different control actions involved in the two modes of operation, namely, grid tied and islanded. The proposal is verified on an experimental setup composed of converters rated 3 kW.

This article presents a formal mathematical correlation between the standardly used port-level (terminated) single-input single-output (SISO), and the recently acknowledged device-level (unterminated) multiple-input multiple-output (MIMO) impedance-based method for the stability assessment of dc–dc interlinking converters. Based on this, the conditions that must be met to ensure the correct stability assessment by the SISO method applied to a single port-pair are derived. It is shown that without prior knowledge on whether these conditions are met, the SISO method must be applied to every port-pair to account for possible port-level hidden dynamics. Alternatively, the MIMO method can be used, which is revealed to inherently account for any port-level hidden dynamics. It is further analyzed which method is advantageous in terms of computational complexity, intuitiveness, and simplicity for applications featuring meshed grids or multiport interlinking converters, as well as in terms of interpreting the resulting stability margins. Finally, suitability of the MIMO method for termination-independent stability-oriented controller design and stability assessment based on measurements is highlighted. The presented methodology is illustrated for a simplified dc system with a current-controlled buck converter. Analytical stability predictions are validated using hardware-in-the-loop simulations and also experimentally, using a laboratory hardware prototype.

This article reveals, analyzes, and proposes the method to mitigate nonlinear effects of multisampled multiupdate (MSMU) digital pulsewidth modulation (PS-DPWM) that appear in unbalanced multicell voltage-source converters (MC-VSCs). For balanced MC-VSCs, the harmonic cancellation of PS-DPWM allows for an increase in the sampling frequency, ensuring that the average current is acquired at the peaks, valleys, and intersections of all the triangular carriers. For unbalanced operation, which is typically encountered in practice, e.g., due to cell voltage mismatch in multilevel MC-VSCs and inductance mismatch in interleaved MC-VSCs, harmonic cancellation of PS-DPWM is compromised and, thus, the increased sampling frequency brings switching ripple in the feedback signal. Since in MSMU control the modulating signal is also updated at peaks, valleys, and intersections of all the carriers, this may cause vertical intersections between the modulating signal and the carriers, resulting in specific nonlinear effects. The nonlinearities are shown to introduce limit-cycle oscillations (LCOs) and output waveform distortion. A method to prevent such detrimental impact of MSMU-PS-PWM is also proposed. A simple analytical procedure is proposed to quantify the analyzed nonlinear effects, revealing that they are more emphasized for higher levels of imbalance and control bandwidth. Moreover, the modulator nonlinearity is shown to decrease as the number of cells increases. The analyses are verified in simulations and experiments, using laboratory prototypes of three- and four-level MC-VSCs.

Active balancing techniques have become increasingly popular for mitigating voltage mismatches in series-connected lithium-ion (Li-ion) batteries. These techniques outperform passive balancing in enhancing battery capacity as the battery ages, leading to an increased lifetime, especially in the electric transportation sector, where residual capacitance plays a crucial role in determining battery lifespan. This study proposes a circuit configuration that utilizes a multiport active half-bridge converter for active cell balancing. The proposed method offers a high degree of flexibility owing to multiple operating modes and a relatively straightforward circuit configuration. Based on the state of charge of each cell, bidirectional power flow can be controlled between two or more arbitrary cells or between the entire battery string and a group of batteries. The proposed approach has been experimentally validated in a battery pack of seven Li-ion cells.

This article addresses switching noise propagation and its suppression in current-controlled systems with multisampled pulsewidth modulation (MS-PWM). MS-PWM enables very high control bandwidths by reducing digital delays. However, when the sampling instants occur near the commutation ones, system performance is prone to being impaired by switching noise. It is analyzed how using the typically considered moving average filters (MAFs) in feedback may have an adverse effect, especially when the number of the noise-corrupted samples is high compared with the number of averaged samples. It is also shown that, without any filters, MS-PWM on its own may mask the negative impact of noise, due to modulator-related nonlinear effects. However, these nonlinearities can lead to an undesirable response to transients and output waveform distortion. Hence, this article proposes MS-PWM with median-based feedback filtering. To avoid ranking within median filter (MED) being affected by the switching ripple, repetitive ripple removal (RRR) is added before MED. The effectiveness of the proposed strategy in suppressing the switching noise is verified in simulations and experiments, during dc and ac operations. RRR+MED successfully suppresses noise-sensitive operating point regions that appear with MAF. Finally, it is shown that, even with added RRR+MED, MS-PWM still retains dynamic improvements over the standard DS-PWM without any filters, offering better reference tracking and disturbance rejection.

This article analyzes the problem of modeling the lifetime in semiconductor power devices subjected to power cycling stress using artificial neural networks (ANNs). This article discusses the optimal configuration of ANNs for the considered problem, aiming at minimizing the error in the predicted lifetime and at reducing the required number of training data. Moreover, being the device lifetime a stochastic parameter, the suitability of ANNs is verified in the case of variability in the input training data. Power cycling tests are conducted on insulated gate bipolar transistor (IGBT) devices and the experimental number of cycles to failure are adopted for the training process of the ANN.