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3. Layout dependence modeling for 45-nm CMOS with stress-enhanced technique

10. DESIGN OF THIN-DOUBLE-WALL VACUUM VESSEL WITH D-SHAPE CROSS SECTION FOR JT-60U

15. High performance bulk planar 20nm CMOS technology for low power mobile applications

16. New layout dependency in high-k/Metal Gate MOSFETs

18. Performance elements for 28nm gate length bulk devices with gate first high-k metal gate

21. Competitive and cost effective high-k based 28nm CMOS technology for low power applications

22. A micro optical blood flow sensor and its application to detection of avian influenza

23. A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes

24. A low power 40nm CMOS technology featuring extremely high density of logic (2100kGate/mm2) and SRAM (0.195μm2) for wide range of mobile applications with wireless system

25. A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process

26. Steeper Indium Halo Formation of nMOSFET by Reducing Interstitial Supersaturation with Flash Lamp pre-Annealing and its Modeling with Atomistic Kinetic Monte Carlo

31. High-Performance 45nm node CMOS Transistors Featuring Flash Lamp Annealing (FLA)

33. Layout-Design Methodology of 0.246-¿m2-Embedded 6T-SRAM for 45-nm High-Performance System LSIs

35. A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

37. Scalable eSiGe S/D Technology with Less Layout Dependence for 45-nm Generation

38. Suppression Effects of Threshold Voltage Variation with Ni FUSI Gate Electrode for 45nm Node and Beyond LSTP and SRAM Devices

40. High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

46. Impact of Two-Step Recessed SiGe S/D Engineering for Advanced pMOSFETs of 32 nm Technology Node and Beyond.

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