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In the practical ASIC and SOC designs the multiple clocks are used and the designs are called as multiple clock domain designs. These kinds of designs need to be described using the efficient design architectures and Verilog RTL. This chapter focuses in the key design techniques which are used to describe the multiple clock domain designs while passing data from one of the clock domain to other. The chapter key highlights are the detail description for the synchronizers, data path, and control path synchronization logic using the efficient Verilog RTL. This chapter also discusses on the key design challenges in the multiple clock domain designs and even this chapter focuses on the design guidelines to describe the efficient clock domain designs.

After the seminal paper by L. Lamport, which introduced (scalar) logical clocks, several other data structures for keeping track of causality in distributed systems have been proposed, including vector and matrix clocks. These are able to capture causal dependencies with more detail but, unfortunately, also consume a substantially larger amount of network bandwidth and storage space than Lamport clocks. This raises the question of whether the benefits of these more complex structures are worth their cost. We address this question in the context of partially replicated systems. We show that for some workloads the use of more expensive clocks does bring significant benefits and that for other workloads no visible benefits can be observed. The paper provides a characterization of the scenarios where each type of clock is more beneficial, helping designers to develop more efficient distributed storage systems.

This paper studies the impact of clock mismatches and quantization on networked control systems. We consider a scenario where the plant's state is measured by a sensor that communicates with the controller through a network. Variable communication delays and clock jitter do not permit a perfect synchronization between the clocks of the sensor and controller. We investigate limitations on the clock offset tolerable for stabilization of the feedback system. For a process with a scalar-valued state, we show that there exists a tight bound on the offset above which the closed-loop system cannot be stabilized with any causal controllers. For higher dimensional plants, if the plant has two distinct poles, then the effect of clock mismatches can be canceled with a finite number of measurements, and hence there is no fundamental limitation. We also consider the case where the measurements are subject to quantization in addition to clock mismatches. For first-order plants, we present necessary conditions and sufficient conditions for stabilizability, which show that a larger clock offset requires a finer quantization.

The Internet of Things is a trending future technological revolution that emerging distributed computing and real-time based application and its development depends on dynamic technical innovation in a number of important fields from wireless sensors to nanotechnology. Cloud integration with IoT made things more convenient and easy. Clock synchronization between systems in a distributed network is the complex and tedious job. It is mandatory to get sync with other and source as well. There are many proposed ways of data synchronization protocols like NTP, global position system to maintain sync process between Systems or IoT devices network. In this paper, we are proposing a clock synchronization approach to sync clocks between IoTs and Cloud which are connected with each other in distributed network. Here we have used cloud service Software as a Service to collect the information to analysis and trigger the results action to IoTs. In this paper, we present the Clock Synchronization based on precision time protocol between IoTs simulation model for Omnet++ with INET framework, which allows us to check clock sync accuracy with a different network configured topologies. We have tried to minimize the clock drift with clock offset updating and with master–slave phenomena also minimize the master–slave delay. To show our simulation results we have used chunks nodes of IoTs in distributed manner placed in different places with different clock values. The simulation result shows that proposed approach works in the desired manner within ideal and network delay symmetry.

The aim of this letter is to improve the performance of clock synchronization in EtherCAT networks. Although EtherCAT synchronizes the slave clocks to the reference clock using a distributed clock synchronization mechanism, a synchronization error still exists between them. We propose a method to estimate and significantly reduce this error. In addition, we implement the method within the existing synchronization mechanism without adding an excessive computational load. The experimental results for synchronization performance verify that the proposed method improves the accuracy of clock synchronization in EtherCAT networks.

Time synchronization is crucial for wireless sensor networks (WSNs) since it maintains data consistency, coordination, and enables other fundamental operations. Over the last decade, a number of powerful time synchronization algorithms have been proposed for clock accuracy optimization by using signal processing techniques. However, most of these algorithms attempt to estimate the clock phase offset and skew and do not correct the node's local clock at every timing packet exchange before the clock parameters are jointly estimated, which reduces the network synchronization accuracy during the estimation of clock parameters and limits the applicability of the synchronization algorithms for some practical sensor networks where a global time scale is consistently required. Motivated by this, this paper investigates the synchronization scheme of having inactive nodes overhearing the pairwise sender-receiver time synchronization based on acknowledgement with clock correction at every synchronization. Assuming exponential random delays, the maximum likelihood estimators (MLEs) of clock skew and the corresponding approximate Cramer-Rao lower bounds (CRLBs) for active and overhearing nodes are derived. In addition, we also consider a linear synchronization model that the clock skew is directly estimated. Simulation results verify the efficiency of the clock skew estimators.

Time synchronization plays an important role in the spacecraft formation flight and constellation autonomous navigation, etc. For the application of clock synchronization in a network system, it is not always true that all the observed nodes in the network are interconnected, therefore, it is difficult to achieve the high-precision time synchronization of a network system in the condition that a certain node can only obtain the measurement information of clock from a single neighboring node, but cannot obtain it from other nodes. Aiming at this problem, a novel method of high-precision time synchronization in a network system is proposed. In this paper, each clock is regarded as a node in the network system, and based on the definition of different topological structures of a distributed system, the three control algorithms of time synchronization under the following three cases are designed: without a master clock (reference clock), with a master clock (reference clock), and with a fixed communication delay in the network system. And the validity of the designed clock synchronization protocol is proved by both stability analysis and numerical simulation.

Timestamp free clock synchronization in a master–slave network, i.e., synchronization where no timestamps are exchanged between the nodes, is considered. For highly accurate synchronization, a novel discrete-valued clock model is introduced. It is based on the observation that clocks are discrete counters in digital wireless radios. Considering this model, it is shown that the round-trip time (RTT) measurements follow specific pulse or step shaped functions. The estimated parameters of these RTT functions are used to determine the clock parameters (clock skew and phase) and the propagation delay. Numerical analysis illustrate that when RTT measurements are collected using discrete-valued clocks, the proposed estimation schemes outperform estimators derived from the continuous clock model, which is used in the state-of-the-art methods. Moreover, the presented scheme performs similar to recently presented discrete-valued clock approaches with more stringent hardware assumption. The correctness of the proposed models is validated through hardware experiments.

Clock networks are required to be constructed with adequate safety margins in the skew constraints to operate correctly even under the influence of variations. In this work, a scalable clock scheduler is developed to drive a synthesis framework that constructs useful skew clock trees with large safety margins that are tailored to the tree topology. Sequential elements are clustered early in the topology, if it is impossible provide adequate robustness to variations using only safety margins. Compared to earlier studies, the proposed framework performs the clock scheduling one to two orders of magnitude faster and improves yield and capacitive cost on several synthesized circuits.

We argue that grid structures are a very promising alternative to the standard approach for distributing a clock signal throughout VLSI circuits and other hardware devices. Traditionally, this is accomplished by a delay-balanced clock tree, which distributes the signal supplied by a single clock source via carefully engineered and buffered signal paths.Our approach, termed HEX, is based on a hexagonal grid with simple intermediate nodes, which both control the forwarding of clock ticks in the grid and supply them to nearby functional units. HEX is Byzantine fault-tolerant, in a way that scales with the grid size, self-stabilizing, and seamlessly integrates with multiple synchronized clock sources, as used in multi-synchronous Globally Synchronous Locally Asynchronous (GALS) architectures. Moreover, HEX guarantees a small clock skew between neighbors even for wire delays that are only moderately balanced. We provide both a theoretical analysis of the worst-case skew and simulation results that demonstrate very small typical skew in realistic runs.

A high precision multi-node clock network for multiple users was built following the precise frequency transmission and time synchronization of 120 km fiber. The network topology adopts a simple star-shaped network structure. The clock signal of a hydrogen maser (synchronized with UTC) was recovered from a 120 km telecommunication fiber link and then was distributed to 4 sub-stations. The fractional frequency instability of all substations is in the level of 10-15 in a second and the clock offset instability is in sub-ps in root-mean-square average.

Recently, wireless sensor networks (WSNs) have drawn great interest due to their outstanding monitoring and management potential in medical, environmental and industrial applications. Most of the applications that employ WSNs demand all of the sensor nodes to run on a common time scale, a requirement that highlights the importance of clock synchronization. The clock synchronization problem in WSNs is inherently related to parameter estimation. The accuracy of clock synchronization algorithms depends essentially on the statistical properties of the parameter estimation algorithms. Recently, studies dedicated to the estimation of synchronization parameters, such as clock offset and skew, have begun to emerge in the literature. The aim of this article is to provide an overview of the state-of-the-art clock synchronization algorithms for WSNs from a statistical signal processing point of view. This article focuses on describing the key features of the class of clock synchronization algorithms that exploit the traditional two-way message (signal) exchange mechanism. Upon introducing the two-way message exchange mechanism, the main clock offset estimation algorithms for pairwise synchronization of sensor nodes are first reviewed, and their performance is compared. The class of fully-distributed clock offset estimation algorithms for network-wide synchronization is then surveyed. The paper concludes with a list of open research problems pertaining to clock synchronization of WSNs.

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered 0.18 mm CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

Clock trees are commonly used to deliver clock signals to sequential elements in circuits. However, by construction, tree structures are inherently prone to failure caused by variations. The robustness of a clock tree can be improved by inserting redundancy in the form of cross links or multilevel fusion trees. Such near-tree structures can provide robustness at low cost. In this paper, we establish that the locations of the inserted redundancy are crucial in providing cost-effective robustness. We present two methods to systematically insert redundancy. The redundancy is realized by either inserting cross links or performing local merges. Moreover, we present a vertex reduction method that reduces the amount of redundancy that needs to be inserted in our near-tree structures. Empirical results show that our structures are more robust to variations and have lower power consumption compared to the state-of-the-art clock networks. Furthermore, our near-tree structures provide smooth trade-offs between cost and robustness, reducing clock skews by 11%–39% at an expense of 3%–68% higher power consumption.

In this paper, a novel hierarchical clock distribution network is implemented with regard to the new characteristics of very deep sub-micro process. The clock distribution network is constructed with a mixed clock structure based on a global H-tree network and regional Mesh network. The regional Mesh network, which is also known as a local Mesh grid, is different from conventional global Mesh networks. Experiments indicate that this clock distribution network has a tiny clock skew and a high tolerance for process variations. The clock skew is within 10 ps. The impact of process variations on clock skew is in the ratio of 10%. These features are useful for timing sequence optimization of high-performance micro process cores.

Designing appropriate clock synchronization schemes and maintaining time consistency among many sensor nodes are crucial for novel distributed applications environments such as Internet of Thing (IoT). However, analyzing the various factors leading to clock inconsistency should be conducted first. The traditional analysis methods are primarily experiential and qualitative, and dynamic disturbances existing among the factors are not considered; moreover, the emerging IoT is rapidly evolving in terms of large-scale feature, service-oriented trend, complexity, and dynamics. Such developments present difficulties in the use of traditional methods in IoT for the analysis of factorial effects on system clocks. To remedy these problems, we propose a novel dynamic evolution model called clock finite state automata (CFSA) using formal methods, exhibiting the overall changing processes of global clock states. We also develop a clock consistency evolution algorithm using CFSA to quantitatively evaluate the influencing factors. The experimental evaluation shows that network delay (41.4% on average) is the greatest impact factor; the frequent entry and exit of the sensor nodes (29.9%) are the second greatest, and the oscillator jitter of computers (11.1%) is the least impact factor. Compared with traditional analysis methods, our method has good feasibility, effectiveness, and novelty. The analysis results can guide the designers of new clock synchronization algorithms for distributed sensor nodes in IoT.

Causal consistency is an intermediate consistency model that can be achieved together with high availability and high-performance requirements even in presence of network partitions. In the context of partitioned data stores, it has been shown that implicit dependency tracking using clocks is more efficient than explicit dependency tracking by sending dependency check messages. Existing clock-based solutions depend on monotonic psychical clocks that are closely synchronized. These requirements make current protocols vulnerable to clock anomalies. In this paper, we propose a new clock-based algorithm, CausalSpartan, that instead of physical clocks, utilizes Hybrid Logical Clocks (HLCs). We show that using HLCs, without any overhead, we make the system robust on physical clock anomalies. This improvement is more significant in the context of query amplification, where a single query results in multiple GET/PUT operations. We also show that CausalSpartan decreases the visibility latency for a given data item comparing to existing clock-based approaches. In turn, this reduces the completion time of collaborative applications where two clients accessing two different replicas edit same items of the data store. Like previous protocols, CausalSpartan assumes that a given client does not access more than one replica. We show that in presence of network partitions, this assumption (made in several other works) is essential if one were to provide causal consistency as well as immediate availability to local updates.

Clock ensembles are at the core of many applications in which precise time or frequency is required. The widely used time scale algorithms need cumbersome modifications when clocks can be potentially faulty. Fault-tolerant clock synchronization algorithms from distributed systems allow to build time scales without the need of special detection systems for anomalous behavior of the clocks. We present a short overview of the general principles underlying these algorithms and their advantages and disadvantages when being used for time scales.

Usage of a precise and accurate clock synchronization solution is unavoidable in modern distributed systems. In industrial usage IEEE 1588:2008 standard is becoming ubiquitous as it provides in-band, cost-effective and reasonably accurate distributed clocks to implement. The reliability is mostly discussed in a cybersecurity perspective, as maintaining the integrity of the clock synchronization messages is crucial to protect the consistency of the clock synchronization network. The current (NTP) and proposed (IEEE 1588v3) clock synchronization standards contain mitigation methods to counter these issues. The PTP protocol uses tens of variables to calculate the hierarchy of the synchronization tree, and update the state variables/clock servos of the synchronizing nodes. The temporal properties of these variable may induce sensitivity to transient memory errors. For example bit errors in static (or rarely recalculated) variables may introduce reconfigurations in the clock sync network which may lead to undesired consequences. This paper examines the robustness and reliability of the IEEE 1588:2008 implementations from a different point of view. The implementation of operational memories, caches, register files used in runtime hardware employ several competing volatile memory technologies. All of them are more or less sensitive to perturbations induced by their environment or to aging. This paper analyses the causes and effects of potential problems related to operation memory corruption and offers solutions so the possible breakdowns could be mitigated or at least detected.

Wireless sensor network works based on the clock synchronization, which need to eliminate hardware-induced drift as well as clock offset. This paper presents an Advanced Virtual Clock Synchronization protocol based on the index approximation.Each node accesses to the network with an unique clock drift and offset, the more difference between the node and the virtual clock, the fast the node adjusts it's drift and offset, thus improve the synchronization efficiency. Simulation data proves that this protocol can effectively improve the synchronization efficiency.

Precise clock synchronization is essential in emerging time-critical distributed control systems operating over computer networks where the clock synchronization requirements are mostly focused on relative clock synchronization and high synchronization precision. Existing clock synchronization techniques such as the Network Time Protocol (NTP) and the IEEE 1588 standard can be difficult to apply to such systems because of the highly precise hardware clocks required, due to network congestion caused by a high frequency of synchronization message transmissions, and high overheads. In response, we present a Time Stamp Counter based precise Relative Clock Synchronization Protocol (TSC-RCSP) for distributed control applications operating over local-area networks (LANs). In our protocol a software clock based on the TSC register, counting CPU cycles, is adopted in the time clients and server. TSC-based clocks offer clients a precise, stable and low-cost clock synchronization solution. Experimental results show that clock precision in the order of 10 microseconds can be achieved in small-scale LAN systems. Such clock precision is much higher than that of a [email protected]?s Time-Of-Day clock and is easily sufficient for most distributed real-time control applications over LANs.

Synchronization is a pre-requisite for many sensor network applications. However, it remains challenging in sensor networks due to both the limited resources and the dynamic environments. In this paper, we propose a new two-phase clock synchronization scheme. The first one is the external clock synchronization phase, during which nodes update their clock by exchanging timestamp messages with the reference clock. Different from the conventional solutions, we propose to directly remove the clock skew during the external synchronization to achieve a higher synchronization accuracy and lower computational complexity. The second one is the clock self-calibration phase, as the accumulated clock skew will make the synchronized clock drift away again, we need to compensate the clock skew to maintain the clock synchronization accuracy. However, the compensation is non-trivial as the clock skew may not be constant due to the changing environment. Thus we propose the temperature-assisted clock self-calibration (TACSC) to dynamically compensate the clock skew according to the working temperature. Extensive simulation demonstrates that the proposed synchronization scheme can achieve a much lower root mean square error in the external synchronization phase. Furthermore, during the clock self-calibration phase, the TACSC scheme can improve the synchronization accuracy by more than one order of magnitude, which is verified by both simulation and testbed experimentation.

An improved clock synchronization algorithm for time triggered architecture has been proposed in this paper. A single reference real time is added in the system, so periodically calibration to real time can be achieved. This algorithm is based on the classical Welch-Lynch[1] fault tolerant clock synchronization process. Systematic clock drift problem has been solved by using the algorithm. Formal analysis is presented, and verification is taken on Matlab/Simulink platform. Simulation result has verified the performance of the algorithm, and the clock difference is bounded as expected.

In this paper, an IEEE1588 based clock synchronization technique for CAN (Controller Area Network) is presented. Clock synchronization plays a key role to the success of a networked embedded system. Recently, the IEEE1588 algorithm making use of dedicated chipsets has been widely adopted for the synchronization of various industrial applications using Ethernet. However, there is no chipset available for CAN. This paper presents the implementation of IEEE1588 for CAN, which is implemented using only software and CAN packets without any dedicated chipset. The proposed approach is verified by the comparison between the estimated synchronization precision with a simple model and the measured precision with experimental setup. ※ 본 연구는 미래창조과학부 및 정보통신산업진흥원의 IT융합 고급인력과정 지원사업의 연구결과로 수행되었음 (NIPA-2013-H0401-13-1005) First Author : 경북대학교 전자공학부 고신뢰성 임베디드 제어 시스템 연구실, itisuptous@nate.com, 학생회원 ° Corresponding Author : 경북대학교 전자공학부 고신뢰성 임베디드 제어 시스템 연구실, dilee@ee.knu.ac.kr, 정회원 * 경상공업고등학교 지능형로봇과, solitarykim@hanmail.net 논문번호:KICS2014-02-035, 접수일자:2014년 2월 4일, 심사일자:2014년 2월 17일, 최종논문접수일자:2014년 2월 21일 I. 서 론 1980년대 이후 마이크로프로세스 기술과 이를 이 용한 산업용 네트워크 기술의 발전에 힘입어 다양한 분야에서 네트워크 기반 임베디드 시스템의 적용이 이루어지고 있다. 필드버스(fieldbus) 또는 데이터버스 (databus)로 불리는 산업용 네트워크는 단순히 복잡한 배선 문제를 개선하는 것 뿐 아니라, 모듈화 설계, 유 지보수 효율성, 시스템 설치 및 수정보완 편리성 등의 장점을 제공하므로, 최근에는 고도의 안전성과 신뢰도 가 요구되는 경성실시간(hard real-time) 시스템에서 도 많이 이용되고 있다. 1980년대 중반 독일의 Bosch 사에 의해 차량내 통신 용도로 개발된 CAN (Controller Area Network) 은 짧고 주기적인 메시지 한국통신학회논문지(J-KICS) '14-02 Vol.39B No.02 124 그림 1. Round-robin 스케줄을 적용한 시간기반 시스템 Fig. 1. Round-robin scheduling of time-triggered system. 의 전송에 적합한 대표적인 필드버스이다. CAN은 차 량에 성공적으로 적용되어 안정성이 검증되었을 뿐 아니라, 사용이 간편하고, 전용 칩과 개발장비를 비롯 해 다양한 지원 제품들이 개발됨에 따라 최근에는 자 동차 산업 외에도 제트엔진, 풍력발전, 잠수함 등에 이르기까지 CAN의 적용분야가 꾸준히 확대되는 추 세이다 . 하지만 최대 1Mbps의 데이터 전송률, 우 선순위가 낮게 지정된 메시지의 과도한 전송지연, 메 시지 충돌 발생시 전송지연이 랜덤하게 변하는 특성 등으로 인해 CAN을 제동장치나 조향장치 등 경성실 시간 시스템에 직접 적용하기에는 어려움이 있다. 이 러한 문제점을 극복하기 위한 대안으로써 시스템을 시간기반(time-triggered)으로 설계 및 구현하는 방안 이 자주 이용된다 . 즉 네트워크에 연결된 노드들이 수행하는 태스크에 대해 그림 1과 같은 round-robin 방 식의 스케줄을 적용함으로서 네트워크의 대역폭 사용효 율을 높이고, 메시지 충돌이 발생하지 않도록 하여 우선 순위와 무관하게 일정한 전송 특성을 얻을 수 있다. 그러나 시간기반 시스템 구현을 위해서는 높은 신뢰 도와 정밀도를 가지는 시간동기(clock synchronization) 의 확보가 반드시 필요하며 , CAN 기반 시스템의 시 간동기에 대한 연구도 다수 발표된 바 있다 . 하지 만 기존 연구에서 제시한 방법들은 ‘in-house’ 구현, 즉 해당 시스템을 위해 자체 개발한 소프트웨어에 의 존하므로 여러 가지 문제점이 따른다. 무엇보다 동기 알고리즘의 신뢰성을 검증하기 어렵고, 소프트웨어 엔 지니어의 역량에 따라 시간동기 성능의 편차가 발생 할 수 있으며, 새로운 시스템 또는 네트워크 적용시 시간동기 소프트웨어를 재작성할 필요가 있다. 이러한 문제점은 표준화된 시간동기 기법을 적용하여 극복 가능하다. 대표적인 임베디드 네트워크용 시간동기 표 준으로 IEEE1588 을 들 수 있다. PTP(Precision Time Protocol)로 불리우는 IEEE1588은 마스터-슬레 이브 방식의 시간동기 기법이며, 마스터가 전송하는 Sync 메시지와 FollowUp 메시지를 이용하여 전송지연 에 의한 동기오차를 보상한다. 멀티캐스트(multicast) 방식의 네트워크에 모두 적용가능 하지만, 아직까지는 EtherCAT, TTEthernet 등 산업용 Ethernet에만 이용 되고 있다. 일반적으로 IEEE1588의 적용을 위해서 전 용 칩을 사용하는데 현재까지 상용화된 칩은 모두 Ethernet 용도로 개발되었기 때문이다. 최근에는 IEEE1588의 동기성능 개선 또는 마스터 고장 상황 인지 및 복구 기법 등에 관한 연구결과가 제시되고 있 으나 이들 역시 Ethernet에 적용한 연구들이 대부분이 다 . 본 논문에서는 CAN 기반 시스템의 시간동기를 위 해 IEEE1588을 소프트웨어로 구현하고, 실험용 네트 워크를 구성하여 동기정밀도를 정량적으로 분석한다. 아울러 시간동기 정밀도 추정을 위한 모델을 도출하 여, 실험을 통해 얻은 정밀도와 모델의 결과를 비교한 다. 일반적으로 IEEE1588 전용 칩을 이용하여 Ethernet에 적용시 수 us 수준의 동기정밀도를 얻을 수 있으나, 본 논문에서는 소프트웨어 방식의 구현과 저사양 클럭 및 CAN의 낮은 전송속도를 고려하여 수 백 us 수준의 동기정밀도를 얻는 것을 목표로 한다.

Clock tree of a complex system-on-chip is modeled across different design stages independently, resulting in multiplication of time and effort needed to develop clock tree models. Model-based design is an emerging methodology that can improve the efficiency, time, and cost of a system design. We propose an approach to modeling clock tree of a complex system-on-chip by exploiting patterns in hardware architectures. Based on patterns, we create parametrized models of clocks which are represented in the form of a template. The specification of a clock consists of specifying parameter values for the template model. The modeling approach is used to generate clock tree models for a variety of design activities including system-level models for power management design.

This paper presents an approach of Time-Triggered Ethernet (TTEthernet, TTE) clock synchronization. Firstly it introduces the roles of each device in clock synchronization algorithm, then analysizes the synchronization steps and their two sub-algorithms:permanencealgorithm andcompressedalgorithm. At last it presents the process of clock correction in different devices.

A fully asynchronous network with one sensor and M anchors (nodes with known locations) is considered in this letter. We propose a novel asymmetrical time-stamping and passive listening (ATPL) protocol for joint clock synchronization and ranging. The ATPL protocol exploits broadcast to not only reduce the number of active transmissions between the nodes, but also to obtain more information. This is used in a simple estimator based on least-squares (LS) to jointly estimate all the unknown clock-skews, clock-offsets, and pairwise distances of the sensor to each anchor. The Cramer-Rao lower bound (CRLB) is derived for the considered problem. The proposed estimator is shown to be asymptotically efficient, meets the CRLB, and also performs better than the available clock synchronization algorithms.

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

Time consistency of each node and each core is one of the kernel problems that must be addressed to promote the development of many-core cluster system that keeps the distributed system in step, and it is the basis of performance evaluation. In this study, a new model of hybrid time synchronization architecture was established to improve the precision of internal clock synchronization of a many-core cluster and the accuracy of time. First, some clock synchronization method was compared for clock synchronization model decision. Second, a high precision time acquire method based on was explored. Third, a hybrid clock synchronization and time acquire architecture on cluster system was designed to enhance the time precision and internal clock consistency. Finally, the architecture was implemented on a Zynq SoC and Epiphany many-core processor combined platform. An experiment was conducted to evaluate the precision and accuracy of this architecture. The result shows that the hybrid architecture achieved a higher level time precision and internal clock consistency than common clock synchronization method like NTP. And result demonstrates the promising application of the proposed architecture in study many-core cluster system and in supplying reliable time reference for the evaluation of distributed system performance.

As distributed systems such as automotive, medical, manufacturing automation become larger and more complex, it is difficult to test these systems. Also, the synchronization of distributed applications make the testing more difficult. In the Software-in-the-Loop (SiL) simulation, a synchronization method among clock of applications is provided for virtual hardware devices and environment. A typical synchronization technique is that a single global clock synchronizes local clocks of other sites but may make high accuracy but low performance in SiL simulation because synchronization occurs in all nodes when the global clock ticks. Also there are some issues of which node should be selected, how much time the global clock drifts when adding new sites, etc. In the paper, we propose a method of clock synchronization based on relative time to enhance the simulation performance.

Time-Triggered (TT) communication, which enhances real-time requirement and packets transmission certainty, can satisfy the requirements of Distributed Integrated Modular Avionic (DIMA). Due to clock skew between source end and destination systems, the end to end performance is inaccurate. Therefore, clock synchronization service is crucial for TT messages transmission in Time-Triggered Ethernet (TTEthernet). There are two kinds of clock synchronization services: external synchronization service and internal synchronization service. The main difference between two services is the presence of a standard time basis. As an internal synchronization service standard of TTEthernet, AS6802 is used to calculate the average difference between timestamp values of end systems in TTEthernet. However, the clock compensation policy after calculation has not been discussed. In this paper, the compensated algorithm based on modified least squares (LS) is proposed. The clock skew can be eliminated online by LS method to get clocks perfectly synchronized. First, the basic theories about reasons of clock offset are analyzed and the process of clock synchronization in TTEthernet is researched; second, the drifted rates of clocks are changed incessantly due to temperature variation or aging. On that account, clocks are modeled as accurately as possible; besides, the simulation platform is built, including end systems, switch models, network topology to verify the effectiveness of the compensated algorithm; finally, the method of this paper compares with the traditional compensation policies. Simulation shows algorithm in the paper can obtain better clock synchronization precision than other algorithms.

A clock synchronization scheme is crucial for obtaining accuracy in time-based positioning systems. Existing clock synchronization schemes are mostly based on a simplified linear clock model, which unfortunately have a poor long-term synchronization accuracy. Assuming a two-way time transfer protocol, we propose a novel clock synchronization algorithm based on a precise physical clock model to realize joint clock synchronization and propagation delay estimation. The Cramer-Rao lower bound (CRLB) is derived for this clock model and shows that the estimation is asymptotically efficient and converges to the lower bound. For long time spans, this model performs better than a linear clock model.

The evolution of deep submicron (DSM) era has resulted in rapid shrinking of the System-on-Chip (SoC) simultaneously with the exponential increase in the design complexity. Larger designs require numerous Intellectual Properties (IPs) composed of millions of combinational and sequential cells to serve the purpose which further require an extensive web of complex clock tree architecture for effective functionality. But with the increase in complexity, it is becoming more and more difficult to keep track about the clock signal effectively reaching to each intended sequential leaf cell. Clock signal, if gets blocked, can hamper the functionality of that particular IP and the effect, in essence, can further ripples down to broken functionality of the complete design. It is therefore imperative to thoroughly check the design for the locations where clock signal is unavailable in early stages of design implementations. This paper provides an algorithm in form of prototype debugger tool which aims at identifying the root cause of no clock signal reaching the clock pin of sequential cell in single iteration. It moves a step further by looking ahead and detecting all the possible potential blocking reasons, apart from the actual ones within a given clock path to a sequential cell in the same iteration. Experimental results on set top box chip show the effectiveness and the efficiency of this method by capturing all the actual and additional probable clock blocking reasons in a single step.

In distributed applications, a group of multiple processes are cooperating with one another by exchanging messages in networks. Information systems like cloud computing systems are getting scalable, which are composed of a huge number of processes. We assume a physical clock which each process reads is synchronized with a time sever, i.e. maximum offset of each clock to UTC time is bounded by some value. Furthermore, processes are interconnected in various types of networks. In this paper, we consider a scalable group composed of subgroups. Processes in each subgroup are interconnected in a local network (LN) and each pair of subgroups are interconnected in a global network (GN). We assume each network supports every pair of processes with reliable and synchronous communication. That is, no message is lost and maximum delay time between every pair of nodes is bounded by some value. An LN and GN support shorter and longer maximum delay time than the maximum clock offset, respectively. Messages are causally delivered by taking usage of both linear clock and physical clock. In the linear clock, some pair of messages which are not required to be causally delivered may be unnecessarily ordered. In order to reduce the number of pairs of unnecessarily ordered messages in the linear clock, the physical clock is additionally used. We evaluate the protocol and show the number of pairs of unnecessarily ordered messages can be reduced compared with the linear clock protocol.

Nanonetwork is a promising research field. It is composed of a number of nanoscale devices and is envisioned to apply to many potential applications. Clock synchronization is essential to establish a distributed cooperation among the nano-devices. This paper investigates the clock synchronization issue for the molecular communication system in the presence of Gaussian distributed propagation delay. A two-way message exchange mechanism is proposed. The closed-form expressions of maximum likelihood estimators for the clock offset and the clock skew are derived. Simulation results further demonstrate the effectiveness of the proposed estimators. This work lays a foundation for the complex cooperation of nanomachines in the nanonetworks.

Nowadays clock synchronization has become crucial in wireless sensor network (WSN), in particular for those scenarios where the common reference time is vital for applications. The existing approaches often suffer from synchronizing errors since the effect of clock granularity is overlooked. In this paper, a novel algorithm is proposed on the basis of PulseSync algorithm. Compared with PulseSync, the improvement of the presented algorithm is twofold: First, clock discreteness is abated via applying filter method. Second, for reducing the deviation of estimated clock skew through several hops, relative logical clock rate is straightly delivered. Our approach, along with the deeper analyses, is further validated with EXP5438 platform using Contiki operating system in Cooja simulator. The result illustrates that the proposed algorithm outperforms PulseSync in synchronization accuracy.

In high-performance synchronous chip design, a buffered clock tree with small clock skew is essential for improving clocking speed. Due to the insufficient accuracy of timing models for modern chip design, embedding simulation into a clock-tree synthesis flow becomes inevitable. Consequently, the running time for clock-tree synthesis becomes prohibitively huge as the complexity of chip designs grows rapidly. To construct a buffered clock tree efficiently, we propose an efficient timing-model independent approach to perform skew minimization by structural optimization. To achieve the goal, a novel clock-tree structure, called symmetrical structure, is presented. At each level of a symmetrical clock tree, the number of branches, the wirelength, and the inserted buffers are almost the same. It is natural that the clock skew could be minimized if the configurations of all paths from the clock source to sinks are similar. By symmetrically constructing a clock tree, the clock skew can be minimized without referring to simulation information. Experimental results show that our approach can not only efficiently construct a buffered clock tree but also effectively minimize clock skew with marginal wiring overheads. Based on a set of commonly used IBM benchmarks, e.g., a state-of-the-art work without (with) ngspice simulation results in averagely 10.04X (3.44X) clock skew and requires 163X (61906X) running time over our approach.

We present a new software-based clock synchronization scheme that provides high precision time agreement among distributed memory nodes. The technique is designed to minimize variance from a reference chimer during runtime and with minimal time-request latency. Our scheme permits initial unbounded variations in time and corrects both slow and fast chimers (clock skew). An implementation developed within the context of the MPI message passing interface is described, and time coordination measurements are presented. Among our results, the mean time variance for a set of nodes improved from 20.0 milliseconds under standard Network Time Protocol (NTP) down to 2.29 secs under our scheme.

A tree-driven clock grid has become the choice of clock delivery for most microprocessors, due to its ability to achieve lower skew and lower variability than clock trees, and is becoming the choice of clock delivery for certain high-end application-specific integrated circuit designs. This paper reports on a clock routing tool that was used in designing multiple tree-driven clock grids in a 2.3 GHz processor system-on-chip, which achieved below 5 ps skew within 500 μm Manhattan distance and below 10 ps skew across each clock grid. This clock routing tool employs a nonsequential algorithm comprised of linear programming and combinatorial heuristics. Its robust length-matching capability enables flexible buffer placement, improved clock signal quality, and robustness to variations.

In this paper, we propose a distributed asynchronous clock synchronization (DCS) protocol for Delay Tolerant Networks (DTNs). Different from existing clock synchronization protocols, the proposed DCS protocol can achieve global clock synchronization among mobile nodes within the network over asynchronous and intermittent connections with long delays. Convergence of the clock values can be reached by compensating for clock errors using mutual relative clock information that is propagated in the network by contacted nodes. The level of clock accuracy is depreciated with respect to time in order to account for long delays between contact opportunities. Mathematical analysis and simulation results for various network scenarios are presented to demonstrate the convergence and performance of the DCS protocol. It is shown that the DCS protocol can achieve faster clock convergence speed and, as a result, reduces energy cost by half for neighbor discovery.

Clock synchronization is essential for a large number of applications ranging from performance measurements in wired networks to data fusion in sensor networks. Existing techniques are either limited to undesirable accuracy or rely on specific hardware characteristics that may not be available in certain applications. In this paper, we examine the clock synchronization problem in networks where nodes lack the high-accuracy oscillators or programmable network interfaces some previous protocols depend on. This paper derives a general model for clock offset and skew and demonstrates its application to real clock oscillators. We design an efficient algorithm based on this model to achieve high synchronization accuracy. This algorithm applies the Kalman filter to track the clock offset and skew. We demonstrate the performance advantages of our schemes through extensive simulations and real clock oscillator measurements.

The clock skew, or the physical ticking rate difference between two digital clocks, has been revealed to have potential on serving as the device fingerprint for identification/authentication purpose. However, it remains as an open issue to detect clock skew replication behavior, which is realized by sending altered timestamps. In this study, it is confirmed that an attacker may fake any target skew with the error being no more than 1ppm in local network environments. Besides, it is also observed that the value of fake timestamps are affected by the time resolution of the attacker's system clock. When the resolution is 1 ms or lower, a relatively large jump between consecutive offsets happens regularly, and the scale of each jump is theoretically the very time resolution of the attacker's system clock. This characteristic is thus adopted to develop a filtering method such that the receiver is able to detect fake timestamps. When the periodical jumps are detected, the filter module abandons these jumps to recover the original clock skew. Experimental results on 15.6 ms and 1 ms time resolutions show that the developed method is effective to detect skew replication attacks, and the errors of the recovered clock skews are no more than 1ppm from the real skews of the attackers.

Time synchronization is a critical and vital piece of infrastructure for any distributed system or sensor network design or real time simulation. Sensor network have many of the same requirements as traditional distributed systems. Distributed wireless sensor networks make extensive use of synchronized time stamps in swarm navigation. Our target is to investigate the time synchronization in the network agents and determine the parameters of individual clock elements of the network. Therefore this paper shows design of clock model, time stamp exchange principle and linear regression for clock time update. It is found from the real-time simulation that the mean of error Probability Distribution Function (PDF) is 20 ms with maximum error probability 2.2% for free running oscillator. The outlayers were removed, and the error was minimized by linear regression method.

We use the Uppaal model checker for timed automata to verify the Timing-Sync time-synchronization protocol for sensor networks (TPSN), the clock-synchronization algorithm of Lenzen, Locher and Wattenhofer (LLW) for general distributed systems, and the clock-thread technique of the software monitoring with controllable overhead algorithm (SMCO). Clock-synchronization algorithms such as TPSN, LLW, and SMCO must be able to perform arithmetic on clock values to calculate clock drift and network propagation delays. They must also be able to read the value of a local clock and assign it to another local clock. Such operations are not directly supported by the theory of timed automata. To overcome this formal-modeling obstacle, we augment the Uppaal specification language with the integer clock-derived type. Integer clocks, which are essentially integer variables that are periodically incremented by a global pulse generator, greatly facilitate the encoding of the operations required to synchronize clocks as in the TPSN, LLW, and SMCO protocols. With these integer-clock-based models in hand, we use Uppaal to verify a number of key correctness properties, including network-wide time synchronization, bounded clock skew, bounded overhead skew, and absence of deadlock. We also use the Uppaal Tracer tool to illustrate how integer clocks can be used to capture clock drift and resynchronization during protocol execution.

A novel clock synchronization scheme is proposed in this paper, which smartly takes the advantages of the inner delay-locked loop(DLL) to compensate for the delay generated by board-level feedback, combining with conventional external clock tree scheme to achieve the system clock synchronization.

Clock synchronization is a critical component in the operation of wireless sensor networks (WSNs), as it provides a common time frame to different nodes. It supports functions such as fusing voice and video data from different sensor nodes, time-based channel sharing, and coordinated sleep wake-up node scheduling mechanisms. Early studies on clock synchronization for WSNs mainly focused on protocol design. However, the clock synchronization problem is inherently related to parameter estimation, and, recently, studies on clock synchronization began to emerge by adopting a statistical signal processing framework. In this article, a survey on the latest advances in the field of clock synchronization of WSNs is provided by following a signal processing viewpoint. This article illustrates that many of the proposed clock synchronization protocols can be interpreted and their performance assessed using common statistical signal processing methods. It is also shown that advanced signal processing techniques enable the derivation of optimal clock synchronization algorithms under challenging scenarios.

We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power supply–properties that are considered highly desirable for future technology nodes.

Efficient and accurate clock synchronization is a challenge for wireless sensor networks (WSNs). Unlike previous works on clock synchronization in WSNs that consider communication delay as the main cause of clock inaccuracy, we propose a new adaptive synchronization scheme, AdaSynch, which considers the principium of the clock. We aim to overcome the challenges posed by WSNs' resource constraints such as limited energy and bandwidth, low precision oscillators and random factors. By implementing some experiments on TelosB platform, we find that the clock system switches between multiple clock models. Motivated by experiment results, we establish a general clock model which describes the clock offset in terms of the oscillators. We then design two kinds of basic Kalman filter models to achieve clock synchronization. In order to execute Kalman filtering, we propose a recursion method based on the Expectation-Maximization (EM) algorithm to access the parameters of the Kalman filter model adaptively. To describe alternation in the clock model, we propose a Multimodel Kalman filter, and put forward an adaptive method based on hypothesis testing to describe these complexities in the clock model. We demonstrate the performance gains of our scheme through experiments using different Kalman filter models based on experiment data.