129 results on '"Masuhara, T."'
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2. Challenge of low voltage and low power IC toward sustainable future.
3. Decorated character recognition by topological matching with self-organizing map.
4. Effects of cholinergic and adrenergic agonists on the secretion of fluid and protein by submandibular glands of the guinea-pig and the mouse
5. Complementary DMOS process for LSI.
6. Optimum crystallographic orientation of submicron CMOS devices.
7. Advanced Hi-CMOS device technology.
8. Induction of experimentalCandidaarthritis in rats
9. Radiographic features of experimental Candida arthritis in rats.
10. Fully symmetric cooled CMOS on.
11. Low-temperature CMOS 8 × 8 bit multipliers with sub-10-ns speeds.
12. Optimum crystallographic orientation of submicrometer CMOS devices operated at low temperatures.
13. Performance and hot-carrier effects of small CRYO-CMOS devices.
14. Design consideration and performance of a new MOS imaging device.
15. A soft error rate model for MOS dynamic RAM's.
16. Low 1/f noise design of Hi-CMOS devices.
17. 2K × 8 bit Hi-CMOS static RAM's.
18. A high-speed low-power Hi-CMOS 4K static RAM.
19. Low-level currents in ion-implanted MOSFET.
20. A precise MOSFET model for low-voltage circuits.
21. Induction of experimental Candida arthritis in rats.
22. A 15-ns 1-Mbit CMOS SRAM.
23. Operation of bulk CMOS devices at very low temperatures.
24. A 256K CMOS SRAM with variable impedance data-line loads.
25. A 20 ns 64K CMOS static RAM.
26. A Hi-CMOSII 8Kx8 bit static RAM.
27. A high-speed Hi-CMOSII 4K static RAM.
28. 2K x 8 Bit Hi-CMOS Static RAM's.
29. Complementary DMOS process for LSI.
30. A high-performance N-channel MOSLSI using depletion-type load elements.
31. Back-gate-input MOS—-A new low-power logic concept.
32. Control and design of MOSFET low-level currents by ion-implantation.
33. Vitamin D and the Intestinal Absorption of Iron and Cobalt
34. MOS imaging with random noise suppression
35. A high-speed, low-power Hi-CMOS 4K static RAM
36. MOS buried load logic
37. A Soft Error Rate Model for MOS Dynamic RAM's
38. Device Design of an Ion Implanted High Voltage MOSFET
39. 2K×8b HCMOS static RAMs
40. Buried J-FET Powered Static RAM Cell
41. A HI-CMOSII 8K × 8b static RAM
42. HI-CMOSII 4K static RAM
43. A 20ns 64K CMOS SRAM
44. Technology and Performance of N-channel MOS-LSI Using Depletion-Type Load Elements
45. Device Design of E/D Gate MOS-FET
46. Stability Investigation of N-channel MOS-FET Utilizing Alumina Film for Large Scale Dynamic Memory Array
47. A high-performance N-channel MOS-LSI using depletion-type load elements
48. A 42ns 1Mb CMOS SRAM
49. A 256K CMOS SRAM with variable-impedance loads
50. A 256K CMOS SRAM with internal refresh
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