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A new 3D printer equipped novel nozzle structure for continuous carbon fiber-reinforced thermoplastics (C-CFRTP) was developed and the suitable printing conditions were studied. C-CFRTP filament and additional matrix resin were supplied independently using each extruder, which is useful for variety printing and precise form control in 3D printing. To measure the mechanical properties, specimens for tensile strength testing were fabricated using C-CFRTP filament (Vf:50%) without additional matrix resin. The experimental results indicate that the tensile strength and Young’s modulus were approximately 700 MPa and 53 GPa, respectively. The recrystallization effect through annealing after 3D printing yielded no drastic improvement. The mechanical properties were considerably improved by a hot-press treatment after 3D printing. The tensile strength and Young’s modulus increased to approximately 1400 MPa and approximately 90 GPa, respectively. These results suggest that one of the useful applications of C-CFRTP...

This paper describes a method to calibrate high current (20 kA) transformers, using a current comparator with a maximum test current of 100 A as a primary standard. In order to fill the large gap in the test current between 20 kA and 100 A, two novel techniques are developed, i.e., 1) the current-ratio transfer standard (CRTS), and 2) the improved equivalent ampere-turn method. The CRTS is a two-stage current transformer with two selectable current ratios of 500A/5A and 100A/5A. The two ratios are realized by the selection of parallel or series combination in the primary windings of the CRTS. The design and the performance of the 100-A primary standard, a coaxial-type self-calibratable current comparator, is also described.

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-/spl mu/m CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 /spl mu/A/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)/spl times/5.6 (V) /spl mu/m/sup 2/. Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively.

Amplified MOS imagers (AMIs) have random noise figures comparable with those of charge-coupled devices (CCDs) but suffer from significant fixed pattern noise (FPN). AMIs are now being experimentally scaled down to a size of 250, 000 pixels per quarter inch for possible use in Hi-Vision systems. We fabricated test devices in order to determine which elements make the greatest contribution to FPN after scaling down. The amplification transistors and reset transistors proved to make comparable contributions to FPN and, in addition, exhibited similar gate-length fluctuations (rms value about 21 nm). Fluctuations in the gate lengths of other components of the devices produced no significant effect on FPN. In the amplification transistors, variations in the voltage threshold produced four times as great an effect on FPN as variations in the gain factor. On exposure to light, FPN increased with aperture.

A 1/4-inch format 250k pixel amplified MOS image sensor has been developed with the CMOS process. We developed a new circuit technique that uses a 0.8μm design rule to reduce pixel size while attaining vertical two line mixing and high sensitivity. Considering high speed operation and stacking photoconversion layers, we have designed scanner circuits and determined photodiode potential. As a result, a dynamic range of 75 dB and a sensitivity of 1.8μA/lx have been attained for a pixel size of 7.2 (H) × 5.6 (V) μm2. Fixed pattern noise is-55dB for saturation current, additional smear is under 2.5 × 10-6, and lag is under 1% on first field. We also confirmed high-speed operation up to a HDTV data rate.

An image sensor for image processing has been developed. A 1/4-inch 250, 000 pixel amplified MOS imager has been equipped with three independent outputs. The amplified MOS imagers nondestructive read-out operation and three lines of memory built in the sensor make it possible to output the signals of three independent lines simultaneously. By applying this function, a vertical DTL circuit and an FPN suppression of 10.8 dB are realized without an external memory.

To calibrate a Current Transformer CT, the Current Comparator CC must be most reliable standard [1][2]. However, it is difficult to assembling CC or estimating errors at high current. Meanwhile, there were some chances to test a high-current CT that exceeds a current limit of the existing traceable standard. The widely known parameter measurement should be a possible approach to prepare CT as a working standard. This paper proposed an improved parameter measurement and presented sample data for a window type CT WS whose nominal current is 20 kA.

The drift of the error of a window-type high current transformer(CT) was observed by an automated calibration system that consists of a current comparator(CC) [1] and a current ratio transfer standard(CRTS) [2]. Furthermore, the shielding by means of aluminum plates for preventing local magnetic saturation is also proposed in this paper.

A one-inch format 1.5 M pixel Interline Transfer (IT) CCD image sensor has been developed for an HDTV camera system. We focused on two areas to achieve a low smear ratio while maintaining high sensitivity. One is the VCCD device structure. By using the device simulator, we have developed a new impurity profile for the buried P+-layer under the VCCD. The other focus area is the optical structure. Considering the incident angle, we simulated the optical path. This simulation helped us determine the size of an optical shield and an onchip microlens made of a deep-UV resist. We have achieved a sensivity of 80 nA/lx, a maximum charge handling capacity of 1.2×105 electrons, and a smear ratio less than-110 dB. A high-fidelity picture with a horizontal resolution of 820 TV lines has been obtained.

A 1-in. format 1.5-million pixel IT (interline transfer) CCD (charge coupled device) image sensor has been developed for an HDTV (high-definition television) camera system. To achieve a low smear ratio while maintaining a high level of sensitivity, the authors have developed a new impurity profile of a buried P/sup +/-layer and an on chip microlens array whose material is a deep-UV resist. Using this sensor, a high-fidelity picture with a horizontal resolution of 820 TV lines has been obtained. The IT-CCD sensor has achieved a smear ratio of less than -90 dB, a sensitivity level of 80 nA/Lx, and a maximum charge handling capacity of 1.2*10/sup 5/ electrons. >

A 1/4 inch format 250K pixel amplified MOS image sensor has been developed with the CMOS process. We have developed a new circuit technique using a 0.8 /spl mu/m design rule to achieve reduction of pixel size while realizing vertical two line mixing and high sensitivity. Considering high speed operation and stacking photoconversion layers, we have designed scanner circuits and photodiode potential. As a result, a dynamic range of 75 dB and a sensitivity of 1.8 /spl mu/ A/lx have been attained at a pixel size of 7.2(H)/spl times/5.6(V)/spl mu/ m/sup 2/. Also we confirmed high speed operation up to a HDTV data rate. >

Recent progress in solid-state imaging sensor technology has increased the number of pixels. The increased sensor array size inevitably raises the data rate and leads to difficulties in image processing. Most of these difficulties come from the scanning operation in which spatially adjacent vertical pixels are arranged separately in a time axis. To solve the problem, this amplified MOS imager (AMI) outputs three neighboring lines simultaneously. This permits signals from spatially-adjacent vertical pixels to be handled at the same time. Two advantages made it possible to realize this sensor. One is signal charge amplification to prevent SNR degradation, the other is a non-destructive read-out function. The sensor is fabricated with 0.8 /spl mu/m, double-polysilicon double-aluminum CMOS process technology. >

The polarization reversals in a surface stabilized ferroelectric liquid crystal were experimentally studied, and the switching mechanism seems to depend on the layer structure. Computer analyses of the switching process are performed and a good agreement with the experiments is obtained.

Phase transitions and switching behavior in a fluorine containing ferroelectric liquid crystal, whose optical purity was controlled by mixing (R) and (S) enantiomorphs, were studied. Only for the pure (R) or (S) enantiomorphs, the phase transition from the SmA to the third state SmCA *, occurred directly. For the mixtures of (R) and (S) enantiomorphs, the phase transition occurred from the SmA to the SmCA * via the SmC*. In these mixtures, with decreasing temperature in SmC*, internal disclination loops changed from “boat type” to “stripe type”.

Simulations of the switching behavior in a ferroelectric liquid crystal were carried out with the model proposed by Handschy and Clark. There appear to be various types of switching processes for changing surface anchoring force. Results of simulations are compared with experimental observations, some of which seem to be well reproduced by the Handschy-Clark model.

The switching characteristics of a ferroelectric liquid crystal with negative dielectric anisotropy were studied. An anomalous behavior has been found in the applied voltage dependence of the switching time, i.e., with increasing applied voltage in the low voltage region the switching time decreases monotonically, while in the high voltage region it attains a minimum and then increases.