207 results on '"Masaki Hashizume"'
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2. Fault Securing Techniques for Yield and Reliability Enhancement of RRAM.
3. Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators.
4. On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC.
5. On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection.
6. Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes.
7. Fault-Aware Dependability Enhancement Techniques for Flash Memories.
8. A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification.
9. Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design.
10. A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type.
11. Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories.
12. Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs.
13. On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects.
14. A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume.
15. A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs.
16. Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories.
17. Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories.
18. Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories.
19. Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines.
20. An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories.
21. Electrically testable CMOS image pixel circuit.
22. Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit.
23. On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs.
24. Electrical interconnect test method of 3D ICs by injected charge volume.
25. Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories.
26. Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs.
27. A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs.
28. Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories.
29. A built-in supply current test circuit for electrical interconnect tests of 3D ICs.
30. Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories.
31. Efficient test length reduction techniques for interposer-based 2.5D ICs.
32. Delay Testable Design Using Modified Boundary Scan
33. Detectability of Open Defects at Interconnects between Dies in 3D Stacked ICs with Relaxation Oscillators
34. Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs.
35. Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs.
36. Fault Scrambling Techniques for Yield Enhancement of Embedded Memories.
37. Diagnosing Resistive Open Faults Using Small Delay Fault Simulation.
38. Education on Electronic Packaging in Department of Electronic and Electrical Engineering
39. A built-in test circuit for open defects at interconnects between dies in 3D ICs.
40. Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture.
41. A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing.
42. A supply current testable register string DAC of decoder type.
43. Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code.
44. Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.
45. A Novel Approach for Improving the Quality of Open Fault Diagnosis.
46. New Class of Tests for Open Faults with Considering Adjacent Lines.
47. Open Defect Detection in Assembled Circuit Boards With Built-In Relaxation Oscillators
48. Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.
49. Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines.
50. Current Testable Design of Resistor String DACs.
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