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A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate the radio frequency (RF) energy harvesting and sensing operations during circuit simulations. The ME antenna of this work is interfaced with a CMOS energy harvester chip towards the goal of developing a wireless communication link for fully integrated implantable devices. One role of the integrated system is to receive pulse-modulated power from a nearby transmitter, and another role is to sense and transmit low-magnitude neural signals. The measurements reported in this paper are the first results that demonstrate simultaneous low-frequency wireless magnetic sensing and high-frequency wireless energy harvesting at two different frequencies with one dual-mode ME antenna. The proposed behavioral ME antenna model can be utilized during design optimizations of energy harvesting circuits. Measurements were performed to validate the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip designed in 65nm CMOS technology. Furthermore, this dual-mode ME antenna enables concurrent sensing using a carrier signal with a frequency that matches the second 63.63 MHz resonance mode. A wireless test platform has been developed for evaluation of ME antennas as a tool for neural implant design, and this prototype system was utilized to provide first experimental results with the transmission of magnetically modulated action potential waveforms.

Wireless implantable medical devices (IMDs) are hamstrung by both size and efficiency required for wireless power transfer. Here, Zaeimbashi et al. present a magnetoelectric nano-electromechanical systems that can harvest energy and sense weak magnetic fields like those arising from neural activity.

Abstract Massive deployments of wireless sensor nodes (WSNs) that continuously detect physical, biological or chemical parameters are needed to truly benefit from the unprecedented possibilities opened by the Internet-of-Things (IoT). Just recently, new sensors with higher sensitivities have been demonstrated by leveraging advanced on-chip designs and microfabrication processes. Yet, WSNs using such sensors require energy to transmit the sensed information. Consequently, they either contain batteries that need to be periodically replaced or energy harvesting circuits whose low efficiencies prevent a frequent and continuous sensing and impact the maximum range of communication. Here, we report a new chip-less and battery-less tag-based WSN that fundamentally breaks any previous paradigm. This WSN, formed by off-the-shelf lumped components on a printed substrate, can sense and transmit information without any need of supplied or harvested DC power, while enabling full-duplex transceiver designs for interrogating nodes rendering them immune to their own self-interference. Also, even though the reported WSN does not require any advanced and expensive manufacturing, its unique parametric dynamical behavior enables extraordinary sensitivities and dynamic ranges that can even surpass those achieved by on-chip sensors. The operation and performance of the first implementation of this new WSN are reported. This device operates in the Ultra-High-Frequency range and is capable to passively and continuously detect temperature changes remotely from an interrogating node.

This paper presents a second-order complex baseband operational transconductance amplifier-capacitor (OTA-C) filter design for wireless receivers. It employs a novel adaptive biasing circuit for large-signal linearization that extends the filter’s usable signal swing range. An analysis of this linearization technique provides insights into its underlying concepts to assist the design process. The method is demonstrated with the first experimental evaluation of a second-order complex baseband filter prototype having a center frequency of 2 MHz and a bandwidth of 850 KHz. Fabricated in a standard 130nm CMOS technology, the filter prototype measurement results show a gain of 35.1 dB and an image rejection ratio of 39.7 dB while operation from a supply voltage of 0.95 V and consuming 0.13 mA. This design advances the low-power bandpass filter state-of-the-art by having an in-band and out-of-band SFDR of 62 dB and 64 dB respectively due to the use of the large-signal linearization approach.

This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.