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A common way of improving performance of applications for multi-core processors is to exploit parallelism. In deep learning (DL), training or tuning parameters use user’s sensitive data, and thus preserving privacy is critical. Hardware-assisted protection mechanisms (i.e., trusted execution environments - TEEs) offer a practical privacy-preserving solution, nowadays available both in private and public data centers. We present SGX-OmpSs, a new approach combining a task-based programming model (i.e., OmpSs) with TEEs (i.e., Intel Software Guard Extensions). SGX-OmpSs supports asynchronous task parallelism and hardware heterogeneity by using the data dependencies between tasks of the application, easily specified by code annotations. We evaluate SGX-OmpSs via several microbenchmarks and state-of-the-art DL applications and datasets (e.g., YOLO and MNIST). SGX-OmpSs achieves 94% gain speedup while offering additional security guarantees., Peer Reviewed, Postprint (author's final draft)

This work is focused on the transparent execution of Cellular Automata models on a multi-GPU architecture. Although Cellular Automata models can be easily parallelized on a single GPU, the domain size and transition function complexity may require the use of multiple GPUs. Our goal is to allow modellers to be completely unaware of the parallel execution context, i.e., the code implementing the Cellular Automata model remains the same regardless if the execution is performed on CPU, single GPU, or multi-GPU systems. This paper supplies meaningful technical insights on how to ensure both transparency and efficiency in multi-GPU execution of Cellular Automata models. In particular, an object-oriented approach is exploited in which a transparent layer is devised that abstracts the parallelization details and allows a strong “separation of concerns” between the execution parallelism issues and the model implementation. Preliminary experiments have been carried out on the multi-GPU cluster CTE-POWER available at the Barcelona Supercomputing Center (BSC), witnessing good speedups notwithstanding the transparency feature supplied by our approach., This research was partially funded by the Italian “ICSC National Center for HPC, Big Data and Quantum Computing” Project, CN00000013 (approved under the Call M42C – Investment 1.4 – Avviso “Centri Nazionali” - D.D. n. 3138 of 16.12.2021, admitted to financing with MUR Decree n. 1031 of 06.17.2022). This work was funded by the Next Generation EU - Italian NRRP, Mission 4, Component 2, Investment 1.5, call for the creation and strengthening of ’Innovation Ecosystems’, building ’Territorial R&D Leaders’ (Directorial Decree n. 2021/3277) - project Tech4You - Technologies for climate change adaptation and quality of life improvement, n. ECS0000009. This work was supported by Italian Ministry of Research (MUR) under PNRR projects FAIR “Future AI ResearcH” - Spoke 9 - CUP H23C22000860006. This research was partially funded by the Spanish Ministry of Education (PID2019-107255GB-C22) and the Generalitat de Catalunya (2021-SGR-01007)., Peer Reviewed, Postprint (author's final draft)

Field Programmable Gate Arrays (FPGA) are still relatively new in the High Performance Computing (HPC) field. Hence, they still lack a mature ecosystem that allows non-FPGA experts to scale an application with many devices operating in parallel. In this paper, we add support for message passing inspired by the Message Passing Interface (MPI) to the Marenostrum Exascale Emulation Platform (MEEP) cluster, a state-of-the-art FPGA cluster. We use the OmpSs@FPGA programming model, which allows C/C++ code to run on the FPGA and call functions that behave like the well-known MPI\_Send/Recv. For that, we implement the message passing runtime over the MEEP 100Gb Ethernet network. This network includes a switch connected to the QSFP port of the FPGA cards. The switch enables all-to-all connectivity without adding routers in the FPGA fabric. We also introduce a method to manage FPGAs that are PCIe-hosted by remote CPU nodes. I.e. from any CPU node we can load the bitstream, configure it, and transfer data to FPGAs that are attached to a different node. Finally, we evaluate the bandwidth of FPGA-FPGA, and CPU-FPGA local and remote communication, as well as the performance of benchmarks scaling from 1 to 64 FPGAs using the infrastructure presented in this paper. The benchmarks are N-body, Heat with Gauss-Seidel solver and Cholesky. We compare the results with the MareNostrum 4 supercomputer and get 2.3x and 3.5x better performance per power for the N-body and Heat., We thank the MEEP project [Horizon 2020 grant number 946002] for providing us the FPGA cluster used in this work. This work was supported by the TEXTAROSSA project [Horizon 2020 grant number 956831]; the Spanish Government [grant numbers PCI2021121964, PDC2022-133323-I00, PID2019-107255GB-C21, MICIU/AEI/ 10.13039/501100011033]; and the Generalitat de Catalunya [grant number 2021 SGR 01007]., Peer Reviewed, Postprint (author's final draft)

Over the years, Field Programmable Gate Arrays (FPGA) have been gaining popularity in the High Performance Computing (HPC) field, because their reconfigurability enables very fine-grained optimizations with low energy cost. However, the different characteristics, architectures, and network topologies of the clusters have hindered the use of FPGAs at a large scale. In this work, we present an evolution of OmpSs@FPGA, a high-level task-based programming model and extension to OmpSs-2, that aims at unifying all FPGA clusters by using a message-passing interface that is compatible with FPGA accelerators. These accelerators are programmed with C/C++ pragmas, and synthesized with High-Level Synthesis tools. The new framework includes a custom protocol to exchange messages between FPGAs, agnostic of the architecture and network type. On top of that, we present a new communication paradigm called Implicit Message Passing (IMP), where the user does not need to call any message-passing API. Instead, the runtime automatically infers data movement between nodes. We test classic message passing and IMP with three benchmarks on two different FPGA clusters. One is cloudFPGA, a disaggregated platform with AMD FPGAs that are only connected to the network through UDP/TCP/IP. The other is ESSPER, composed of CPU-attached Intel FPGAs that have a private network at the ethernet level. In both cases, we demonstrate that IMP with OmpSs@FPGA can increase the productivity of FPGA programmers at a large scale thanks to simplifying communication between nodes, without limiting the scalability of applications. We implement the N-body, Heat simulation and Cholesky decomposition benchmarks, and show that FPGA clusters get 2.6x and 2.4x better performance per watt than a CPU-only supercomputer for N-body and Heat., This work was supported by the Horizon 2020 TEXTA-ROSSA project [grant number 956831]; the Spanish Government [grant numbers PCI2021-121964, PDC2022-133323-I00, PID2019 - 107255GBC21, MCIN/AEI/10.13039/501100011 033]; the Generalitat de Catalunya, Spain [grant number 2021 SGR 01007]; and partially supported by the Japan Society for the Promotion of Science (JSPS) [KAKENHI grant number JP20H 00593]., Peer Reviewed, Postprint (published version)

Dynamic Task Scheduling is an enticing programming model aiming to ease the development of parallel programs with intrinsically irregular or data-dependent parallelism. The performance of such solutions relies on the ability of the Task Scheduling HW/SW stack to efficiently evaluate dependencies at runtime and schedule work to available cores. Traditional SW-only systems implicate scheduling overheads of around 30K processor cycles per task, which severely limit the ( core count , task granularity ) combinations that they might adequately handle. Previous work on HW-accelerated Task Scheduling has shown that such systems might support high performance scheduling on processors with up to eight cores, but questions remained regarding the viability of such solutions to support the greater number of cores now frequently found in high-end SMP systems. The present work presents an FPGA-proven, tightly-integrated, Linux-capable, 30-core RISC-V system with hardware accelerated Task Scheduling. We use this implementation to show that HW Task Scheduling can still offer competitive performance at such high core count, and describe how this organization includes hardware and software optimizations that make it even more scalable than previous solutions. Finally, we outline ways in which this architecture could be augmented to overcome inter-core communication bottlenecks, mitigating the cache-degradation effects usually involved in the parallelization of highly optimized serial code., This work is supported by the TEXTAROSSA project G.A. n.956831, as part of the EuroHPC initiative, by the Spanish Government (grants PCI2021-121964, TEXTAROSSA; PDC2022-133323-I00, Multi-Ka; PID2019-107255GB-C21 MCIN/AEI/10.13039/501100011033; and CEX2021-001148-S), by Generalitat de Catalunya (2021 SGR 01007), and FAPESP (grant 2019/26702-8)., Peer Reviewed, Postprint (published version)

We propose the Active Compute Memory (ACM), a near-memory-processing architecture capable of performing key–value sort directly in the DRAM. In the ACM architecture, sort is merely the writing of data into memory with one addressing protocol (perspective) and reading it back with different perspective. The first perspective is conventional, based on the data address; the second perspective is the sorted order. The ACM requires additional tables to store the meta-data and moderate control logic enhancements that can be implemented directly in the DRAM silicon. By these modest enhancements to DRAM, ACM exploits the parallelism inherently available in the row buffer to enable sort with O ( n ) complexity. This leads to an order of magnitude improvement in ACM performance and energy compared to conventional O ( n log n ) CPU-centric sort algorithms. The ACM also shows superior performance compared to other near-memory sort accelerators. This is because the ACM processing is done near the row buffer and it exploits much lower memory access latency, higher bandwidth and wider parallel processing. The sort operation covered in this paper is just an example of an address management operation that can be efficiently implemented directly in the DRAM silicon. We release as an open source the simulation infrastructure for the ACM performance and energy modeling. We would encourage the community to use it, adapt it to other PIM proposals, and share their own evaluations., This work was funded by the Collaboration Agreement between Micron Technology, Inc. and BSC. The work was also supported by the Spanish Government, under the contracts PID2019-107255GB-C21 and CEX2021-001148-S funded by MCIN/AEI/ 10.13039/501100011033. The work also received funding from the Department of Research and Universities of the Government of Catalonia to the AccMem Research Group (Code: 2021 SGR 00807) and project DEEP-SEA funded by European Union’s Horizon 2020 research and innovation programme , under Grant Agreement no.955606 and the Spanish Government, under the contract PCI2021-121958 funded by MCIN/AEI/ 10.13039/501100011033 and “European Union NextGenerationEU/PRTR”., Peer Reviewed, Postprint (author's final draft)

Emulating chip functionality before silicon production is crucial, especially with the increasing prevalence of RISC-V-based designs. FPGAs are promising candidates for such purposes due to their high-speed and reconfigurable architecture. In this paper, we introduce our Makinote, an FPGA-based Cluster platform, hosted at Barcelona Supercomputing Center (BSC-CNS), which is composed of a large number of FPGAs (in total 96 AMD/Xilinx Alveo U55c) to emulate massive size RTL designs (up to 750M ASIC cells)1. In addition, we introduce our FPGA shell as a powerful tool to facilitate the utilization of such a large FPGA cluster with minimal effort needed by the designers. The proposed FPGA shell provides an easy-to-use interface for the RTL developers to rapidly port such design into several FPGAs by automatically connecting to the necessary ports, e.g., PCIe Gen4, DRAM (DDR4 and HBM), ETH10g/100g. Moreover, specific drivers for exploiting RISC-V based architectures are provided within the set of tools associated with the FPGA shell. We release the tool online for further extensions.2 We validate the efficiency of our hardware platform (i.e., FPGA cluster) and the software tool (i.e., FPGA Shell) by emulating a RISC-V processor and experimenting HPC Challenge application running on 32 FPGAs. Our results demonstrate that the performance improves by 8 times over the single-FPGA case., This work has received funding from the MEEP project (European High-Performance Computing Joint Undertaking (JU) under grant agreement No 946002), from ”Lenovo-BSC Contract-Framework (2022)”, from the Spanish Government (PID2019-107255GB-C21/AEI /10.13039/501100011033, CEX2021-001148-S funded by MCIN/AEI / 10.13039/501100011033), and from Generalitat de Catalunya (contract 2021-SGR-01007)., Peer Reviewed, Postprint (author's final draft)

The European Processor Initiative (EPI) is a European project that performs research to advance High-Performance Computing (HPC) through the development of European technology. EPI aims at the development of a general-purpose processor and a RISC-V-based accelerator. Barcelona Supercomputing Center (BSC) is involved in the development of a Vector Processor Unit to be connected to a RISC-V core, called Vector tile, that is part of the EPI accelerator. While the actual hardware is being produced by the silicon foundry, the project foresees the implementation of a Vector tile within an Field Programmable Gate Array (FPGA) that serves as a hardware prototype for software development. The set of hardware and software tools necessary for making the Vector tile operational as an HPC compute node is called Software Development Vehicles (SDV). The SDV functionalities rely on a Xilinx FPGA connected to a host-PC via a Peripheral Component Interconnect Express (PCIe) link. This thesis aims to study, evaluate and upgrade the current PCIe subsystem working on the EPI SDV. The main technical contribution of this work is the improvement of the PCIe link between the host-PC and the FPGAs housing the Vector tile making use of the latest Xilinx Intellectual Property (IP) and the corresponding software. This work allowed both to improve the performance of the PCIe link and to expand the portability of the SDV environment to support one more FPGA board.

(English) In a typical HPC cluster system, a node is the elemental component unit of this architecture. Memory and compute resources are tightly coupled in each node and the rigid boundaries between nodes limits compute and memory resource utilization. The problem is increased by the fact that HPC applications have a widely varying per-node memory footprint due to diverse application characteristics, differing problem sizes, and strong scaling. In fact, 25% to 76% of the system's total memory capacity typically remains idle. Disaggregated memory offers a way to improve memory utilization, as memory becomes a pool that can be dynamically composed to match the needs of the workloads. It enables fine-grained allocation of memory capacity to jobs while maintaining the cost-effectiveness and scalability of a cluster architecture. A key component for the distribution of computing power within the cluster infrastructure is the RJMS or simply resource manager. Its goal is to satisfy users' demands and achieve acceptable performance in the overall system utilization by efficiently matching requests to resources. Even though several researches on RJMS have been carried out to solve problems related to the current state-of-the-art on HPC systems, memory disaggregation is still under development. Therefore, adopting a disaggregated architecture means redesigning the resource manager services. In this thesis we propose an efficient memory disaggregated infrastructure for a cluster resource manager and its evaluation at scale through a structured simulated experimental methodology employing a contention model that models the impact of shared resources in disaggregated scenarios. Sharing common memory devices or interfaces in a disaggregated infrastructure may incur an unsatisfactory loss of performance because concurrent memory access can saturate the resource; we start our study by introducing a systematic methodology to build a contention model. Extensive real-machine experimen, (Español) En un clúster HPC. un nodo es la unidad elemental de esta arquitectura. Como la memoria y computación están estrechamente acoplados los límites rígidos entre nodos limitan la utilización de los recursos. El problema se agrava debido a que las aplicaciones de HPC tienen requerimientos de memoria muy variables. De hecho, normalmente se deja inactive entre un 25% y un 76% de la capacidad total de memoria del sistema. La memoria desagregada propone una forma de mejorar la utilización de la memoria, ya que la convierte en un conjunto que puede componerse dinámicamente. Permite una asignación de capacidad de memoria de granularidad fina a los trabajos, manteniendo a la vez la rentabilidad y escalabilidad de una arquitectura de clúster. Un componente clave para la distribución de recursos en un clúster es el RJMS o simplemente gestor de recursos. Su objetivo es satisfacer las demandas de los usuarios y lograr un rendimiento aceptable en la utilización general del sistema, mediante una asignación eficiente de los recursos. Aunque se han llevado a cabo varias investigaciones sobre RJMS, la memoria desagregada aun esta en desarrollo. En esta tesis, proponemos una infraestructura eficiente de memoria desagregada para un gestor de recursos de clúster y evaluamos su rendimiento a gran escala mediante una metodología experimental simulada y estructurada que utiliza un modelo de contención que simula el impacto de los recursos compartidos en escenarios desagregados. Compartir interfaces de memoria en una infraestructura desagregada puede generar una pérdida de rendimiento con acceso concurrente a la memoria. Comenzamos nuestro estudio presentando una metodología sistemática para construir un modelo de contención. Experimentación extensiva en máquinas reales y los resultados de las cargas de trabajo han demostrado que nuestro modelo de contención predice una degradación del rendimiento con un error promedio de 1.19% y un error máximo de 14.6%. En comparación con el estado, Postprint (published version)

In state-of-the-art FPGA, especially in chiplet-based devices, place and route has become an important challenge due to an increase in device size and complexity. In the same way, off-chip memory resources have grown in size and number of memory modules. Making efficient use of them has become a difficult task., This work is supported by the TEXTAROSSA project G.A. n.956831, as part of the EuroHPC initiative, by the Spanish Government (Grants PCI2021-121964 - TEXTAROSSA, PID2019-107255GB-C21, PID2019-107255GB-C22, MCIN/AEI/10.13039/501100011033, and CEX2021-001148-S), and by Generalitat de Catalunya (2021 SGR 01007)., Peer Reviewed, Postprint (author's final draft)

Aquest treball de fi de grau presenta el disseny, implementació i validació del suport d'OmpSs-2@FPGA per a Clang. Aquesta eina permet la programació de tasques per a la seva execució en FPGA en els llenguatges de programació C i C++, utilitzant el mateix codi que s'usaria en una implementació d'aquesta tasca per a la CPU. Aquest projecte s'ha desenvolupat al BSC (Barcelona Supercomputer Center), amb l'equip de Programing Models. Aquest projecte parteix de la implementació ja existent d'OmpSs@FPGA i d'OmpSs-2@FPGA per a Mercurium (compilador font a font del BSC), del qual se n'ha extret els coneixements principals per a la implementació del projecte. Aquesta implementació genera a partir de la informació extreta del codi de l'usuari un fitxer en C++ amb totes les transformacions necessàries perquè un segon compilador del fabricant de la FPGA pugui generar el maquinari necessari per a executar les tasques que l'usuari ha programat. Aquestes transformacions suposen tant la generació de codi addicional a partir de la informació disponible a les tasques, com la transformació del codi de l'usuari per a adaptar-lo a les necessitats de les FPGA. Addicionalment, s'ha afegit la possibilitat d'instrumentar el codi de l'usuari un cop dins la FPGA, permetent així avaluar el rendiment de les tasques generades gràcies a la llibreria d'instrumentació d'OVNI. Amb aquesta eina, s'ha simplificat el desenvolupament de codi d'usuari per a FPGA i s'ha eliminat la dependència amb Mercurium, simplificant també el desenvolupament del compilador., This final degree project presents the design, implementation, and validation of the feature support of OmpSs-2@FPGA for Clang. The tool enables the programming of tasks in the C and C++ programming languages for their execution on FPGAs, using the same code that would have been used in a CPU implementation of this same task. This project has been developed at BSC (Barcelona Supercomputer Center), with the Programming Models team. The project is based on the already existing implementation of OmpSs@FPGA and OmpSs-2@FPGA for Mercurium (a BSC source-to-source compiler), from which the main knowledge for the implementation of the project has been extracted. This implementation generates, from the information extracted from the user's code, a file in C++. This file contains all the necessary code transformations so that a second compiler from the FPGA manufacturer can generate the necessary hardware to execute the tasks that the user has programmed. These transformations involve both the generation of additional code from the information available in the tasks, and the transformation of the user's code to adapt it to the needs of the FPGAs. Additionally, the possibility of instrumenting the user's code, to be accelerated in the FPGA, has been added, thus allowing the evaluation of the performance of the tasks generated thanks to the OVNI instrumentation library. With this tool, the development of user code for FPGAs has been simplified and the dependency with Mercurium has been eliminated, also simplifying the development of the compiler.

In modern FPGA devices, place and route has become an increasingly difficult task due to an increase in resources and device complexity. This results in an exponential increase of implementation possibilities. Such a huge search space causes tools to have a hard time providing a good solution. This is even more challenging in chiplet-based devices due to their topology. In the same way, off-chip memory resources have grown both in size and number of modules. These resources are presented to the user as raw memory interfaces requiring the user to manage how accelerator kernels access off-chip memory to make effective use of the available bandwidth. Efficient usage of memory resources becomes a critical challenge as the more computational resources are added to a design the more pressure they impose on the memory subsystem. This work proposes new features to the OmpSs@FPGA programming model in order to mitigate these issues in a transparent way for programmers., This work is supported by the TEXTAROSSA project G.A. n.956831, as part of the EuroHPC initiative, by the Spanish Government (Grants PCI2021-121964-TEXTAROSSA, PID2019-107255GB-C21 MCIN/AEI/10.13039/501100011033, and CEX2021-001148- S), and by Generalitat de Catalunya (2021 SGR 01007)., Peer Reviewed, Postprint (author's final draft)

El objetivo del trabajo es mejorar y modernizar un laboratorio HPC situado en el departamento de Física de la Matéria Condensada de la Facultad de Física en la Universidad de Barcelona. Consistirá en implementar una arquitectura unificada que mejore la gestión y la seguridad de la infrastructura, integrando nodos CPU y GPU, permitiendo una administración centralizada de los recursos, y permitiendo la ejecución de trabajos con el sistema de colas SLURM., The objective of the work is to improve and modernize an HPC laboratory located in the Department of Condensed Matter Physics of the Faculty of Physics at the University of Barcelona, where I currently work and develop the role of systems administrator. This lab is used by researchers and PhD students to run high performance calculations and simulations. The infrastructure currently consists of a 40-node computing cluster based on CPUs, managed through the SGE scheduler. In addition, the laboratory has another 6 isolated GPU servers. Given the segregation between these systems, the need arises for a unified architecture that improves both the management and the security of the infrastructure. For this reason, my objective is to implement a new cluster from scratch, which integrates both CPU and GPU nodes, allowing a centralized and more sophisticated management of resources. To achieve this goal, the idea is to integrate a cluster of Linux servers managed by a SLURM queue system, in addition to implementing a multiversion software manager through EasyBuild and a module manager. On the other hand, for user management, the use of software based on the LDAP protocol and a remote backup system to provide security copies are proposed.

This paper describes two different approaches to emulate an Ethernet communication link between a host computer and a RISC-V multiprocessor system running on a FPGA accelerator by using PCIe as the real communication link. Two approaches are tested, one based on user-level applications using TUN/TAP drivers and another based on implemented kernel-mode drivers on the Linux Operation System. We have functionally validated the approaches in multiple RISC-V systems and measured the achieved performance. A maximum bandwidth of 32.5 Mbps has been achieved in a Lagarto Hun system running at 100 Mhz., The MEEP project has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 946002. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Spain, Croatia, Turkey. This project is also partly funded by the Catalan Government Research groups 2021-SGR-01623., Peer Reviewed, Postprint (author's final draft)

MPI is the de facto communication standard library for parallel applications in distributed memory architectures. Collective operations performance is critical in HPC applications as they can become the bottleneck of their executions. The advent of larger node sizes on multicore clusters has motivated the exploration of hierarchical collective algorithms aware of the process placement in the cluster and the memory hierarchy. This work analyses and compares several hierarchical collective algorithms from the literature that do not form part of the current MPI standard. We implement the algorithms on top of OpenMPI using the shared-memory facility provided by MPI-3 at the intra-node level and evaluate them on ARM-based multicore clusters. From our results, we evidence aspects of the algorithms that impact the performance and applicability of the different algorithms. Finally, we propose a model that helps us to analyze the scalability of the algorithms., This work has been supported by the Spanish Ministry of Education (PID2019-107255GB-C22) and the Generalitat de Catalunya (2017-SGR-1414)., Peer Reviewed, Postprint (author's final draft)

This document feeds research and development priorities devel-oped by the European HPC ecosystem into EuroHPC’s Research and Innovation Advisory Group with an aim to define the HPC Technology research Work Programme and the calls for proposals included in it and to be launched from 2023 to 2026. This SRA also describes the major trends in the deployment of HPC and HPDA methods and systems, driven by economic and societal needs in Europe, taking into account the changes ex-pected in the technologies and architectures of the expanding underlying IT infrastructure. The goal is to draw a complete picture of the state of the art and the challenges for the next three to four years rather than to focus on specific technologies, implementations or solutions., Peer Reviewed, Article signat per 140 autors/autores: Estela Suarez,JSC; Nico Mittenzwey, MEGWARE; Laurent Cargemel, Atos; Alessandro Russo, Leonardo; Andy Forrester, HypeAccelerator Solutions Limited; Carlo Cavazzoni, Leonardo; Craig Prunty, SiPearl; Daniele Cesarini, Cineca; David Tur, Do IT Now; Fabrizio Magugliani, E4 Computer Engineering SpA; Marc Casas, BSC; Rene Oertel, MEGWARE Computer Vertrieb und Service GmbH; Sergio Sánchez, Vicomtech; Thierry Porcher, Do IT Now; Marc Duranton, CEA / HiPEAC; Sakir Sezer, NVIDIA; Craig Prunty, SIPEARL; Alessandro Russo, Leonardo; Dirk Pleiter, KTH; Luigi Capone, Leonardo; Marco Cicala, E4 Computer Engineering SpA; Osman Unsal, BSC; Paolo Amato, Micron; Petar Radojkovic, BSC; Rod Evans, NVIDIA; Thierry Porcher, Do IT Now; Xavier Martorell, BSC; Manolis Marazakis, FORTH; Maria Perez, UPM / BDVA; Pascale Rossé-Laurent, Atos; Alberto Miranda, BSC; Alberto Scionti, LINKS Foundation; Alessandro Russo, Leonardo; David Tur, Do IT Now; Denis Maggi, Vicomtech; Georgios Goumas, ICCS; Ina Schmitz, ParTec; Jordi Guitart, BSC; Julita Corbalan, BSC; Michele Martone, LRZ; Nico Mittenzwey, MEGWARE; Nicolo Magini, Leonardo; Paolo Viviani, LINKS Foundation; Rene Oertel, MEGWARE Computer Vertrieb und Service GmbH; Sebastien Varrette, University of Luxembourg; Thierry Porcher, Do IT Now; Thomas Moschny, Par-Tec, Guy Lonsdale, SCAPOS; Paul Carpenter, BSC; Gabriel Antoniu, INRIA (BDVA); Alexander Costan, INSA Rennes/Inria; Ani Anciaux Sedrakian, IFPEN; Antonio Peña, BSC; Antonio Sciarappa, Leonardo; Christian Perez, INRIA; Francesco Iannone, ENEA; Jose Gracia, HLRS; Leonardo Arturo Bautista Gomez, BSC; Luigi Capone, Leonardo; Miguel Vasquez, BSC; Olivier Marsden, ECMWF; Paolo Viviani, LINKS Foundation; Patrick Carribault, CEA; Sebastien Varrette, University of Luxembourg; Vicenc Beltran, BSC; Xavier Martorell, BSC; Andre Brinkmann, JGU – Mainz; Sai Narasimhamurthy, Seagate; Anna Queralt, BSC; Jean-Thomas Acquaviva, DDN Storage; Jesús Carretero Pérez, UC3M; Nic, Postprint (published version)

Nowadays, a new parallel paradigm for energy-efficient heterogeneous hardware infrastructures is required to achieve better performance at a reasonable cost on high-performance computing applications. Under this new paradigm, some application parts are offloaded to specialized accelerators that run faster or are more energy-efficient than CPUs. Field-Programmable Gate Arrays (FPGA) are one of those types of accelerators that are becoming widely available in data centers. This paper proposes OmpSs@cloudFPGA, which includes novel extensions to parallel task-based programming models that enable easy and efficient programming of heterogeneous clusters with FPGAs. The programmer only needs to annotate, with OpenMP-like pragmas, the tasks of the application that should be accelerated in the cluster of FPGAs. Next, the proposed programming model framework automatically extracts parts annotated with High-Level Synthesis (HLS) pragmas and synthesizes them into hardware accelerator cores for FPGAs. Additionally, our extensions include and support two novel features: 1) FPGA-to-FPGA direct communication using a Message Passing Interface (MPI) similar Application Programming Interface (API) with one-to-one and collective communications to alleviate host communication channel bottleneck, and 2) creating and spawning work from inside the FPGAs to their own accelerator cores based on an MPI rank-like identification. These features break the classical host-accelerator model, where the host (typically the CPU) generates all the work and distributes it to each accelerator. We also present an evaluation of OmpSs@cloudFPGA for different parallel strategies of the N-Body application on the IBM cloudFPGA research platform. Results show that for cluster sizes up to 56 FPGAs, the performance scales linearly. To the best of our knowledge, this is the best performance obtained for N-body over FPGA platforms, reaching 344 Gpairs/s with 56 FPGAs. Finally, we compare the performance and power c, This work has been done in the context of the IBM/BSC Deep Learning Center initiative. This work has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 754337 (EuroEXA), from Spanish Government (PID2019-107255GBC21/AEI/10.13039/501100011033), and from Generalitat de Catalunya (2017-SGR-1414 and 2017-SGR-1328)., Peer Reviewed, Postprint (author's final draft)

In the near future, Exascale systems will need to bridge three technology gaps to achieve high performance while remaining under tight power constraints: energy efficiency and thermal control; extreme computation efficiency via HW acceleration and new arithmetic; methods and tools for seamless integration of reconfigurable accelerators in heterogeneous HPC multi-node platforms. TEXTAROSSA addresses these gaps through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models, and tools derived from European research., This work is supported by the TEXTAROSSA project (G.A. n. 956831), as part of the EuroHPC initiative., Peer Reviewed, Article signat per 56 autors/es: Giovanni Agosta (a) , Marco Aldinucci (f) , Carlos Alvarez (h) , Roberto Ammendola (n) , Yasir Arfat (f) , Olivier Beaumont (g) , Massimo Bernaschi (c) , Andrea Biagioni (j) , Tommaso Boccali (l) , Berenger Bramas (g) , Carlo Brandolese (a) , Barbara Cantalupo (f) , Mauro Carrozzo (c) , Daniele Cattaneo (a) , Alessandro Celestini (c) , Massimo Celino (b) , Iacopo Colonnelli (f) , Paolo Cretaro (j) , Pasqua D’Ambra (d) , Marco Danelutto (e) , Roberto Esposito (f) , Lionel Eyraud-Dubois (g) , Antonio Filgueras (h) , William Fornaciari (a) , Ottorino Frezza (j) , Andrea Galimberti (a) , Francesco Giacomini (k) , Brice Goglin (g) , Daniele Gregori (o) , Abdou Guermouche (g) , Francesco Iannone (b) , Michal Kulczewski (i) , Francesca Lo Cicero (j) , Alessandro Lonardo (j) , Alberto R. Martinelli (f) , Michele Martinelli (j) , Xavier Martorell (h) , Giuseppe Massari (a) , Simone Montangero (m), Gianluca Mittone (f) , Raymond Namyst (g) , Ariel Oleksiak (i) , Paolo Palazzari (b) , Pier Stanislao Paolucci (j) , Federico Reghenzani (a)∗ , Cristian Rossi (j) , Sergio Saponara (e) , Francesco Simula (j) , Federico Terraneo (a) , Samuel Thibault (g) , Massimo Torquati (e) , Matteo Turisini (j) , Piero Vicini (j) , Miquel Vidal (h) , Davide Zoni (a) , Giuseppe Zummo (b) // (a) Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Italy; (b) ENEA, Agenzia nazionale per le nuove tecnologie, l’energia e lo sviluppo economico sostenibile, Italy; (c) Istituto per le Applicazioni del Calcolo (IAC), Consiglio Nazionale delle Ricerche, Rome, Italy; (d) Istituto per le Applicazioni del Calcolo (IAC), Consiglio Nazionale delle Ricerche, Naples, Italy; (e) University of Pisa, Italy; (f) University of Torino, Italy; (g) Institut national de recherche en informatique et en automatique (Inria), France; (h) Barcelona Supercomputing Center, Spain; (i) Poznan Supercomputing and Networking Center, Poland; (j) Istituto Nazionale di Fisic, Postprint (author's final draft)

The lightning talks at EduHPC provide an opportunity to share early results and insights on parallel and distributed computing (PDC) education and training efforts. The four lightning talks at EduHPC 2022 cover a range of topics in broadening PDC education: (i) curriculum development efforts for the European Masters in HPC program, (ii) bootcamps for CI professionals who support the running of AI workloads on HPC systems, (iii) a GPU programming course following the Carpentries model and (iv) peer-review assignments to help students write efficient parallel algorithms within sustainable software libraries., Peer Reviewed, Article signat per 26 autors/es: Apan Qasem 1, Hartwig Anzt 2,3, Eduard Ayguade 4, Katharine Cahill 5, Ramon Canal 4, Jany Chan 6, Eric Fosler-Lussier 6, Fritz Göbel 2, Arpan Jain 6, Marcel Koch 2, Mateusz Kuzak 7, Josep Llosa 4, Raghu Machiraju 6, Xavier Martorell 4, Pratik Nayak 2, Shameema Oottikkal 5, Marcin Ostasz 8, Dhabaleswar K. Panda 6, Dirk Pleiter 9, Rajiv Ramnath 6, Maria-Ribera Sancho 4, Alessio Sclocco 7, Aamir Shafi 6, Hanno Spreeuw 7, Hari Subramoni 6, Karen Tomko 7 / 1 Department of Computer Science, Texas State University, USA; 2 Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany; 3 University of Tennessee (UTK), Knoxville, USA; 4 Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, Spain; 5 Ohio Supercomputer Center, USA; 6 College of Engineering, The Ohio State University, USA; 7 Netherlands eScience Center, The Netherlands; 8 ETP4HPC, The Netherlands; 9 PDC Center for High Performance Computing, KTH Royal Institute of Technology, Sweden, Postprint (author's final draft)

A la portada logo BSC, (English) The dominant programming approach for scientific and industrial computing on clusters is MPI+X. While there are a variety of approaches within the node, denoted by the ``X'', Message Passing interface (MPI) is the standard for programming multiple nodes with distributed memory. This thesis argues that the OmpSs-2 tasking model can be extended beyond the node to naturally support distributed memory, with three benefits: First, at small to medium scale the tasking model is a simpler and more productive alternative to MPI. It eliminates the need to distribute the data explicitly and convert all dependencies into explicit message passing. It also avoids the complexity of hybrid programming using MPI+X. Second, the ability to offload parts of the computation among the nodes enables the runtime to automatically balance the loads in a full-scale MPI+X program. This approach does not require a cost model, and it is able to transparently balance the computational loads across the whole program, on all its nodes. Third, because the runtime handles all low-level aspects of data distribution and communication, it can change the resource allocation dynamically, in a way that is transparent to the application. This thesis describes the design, development and evaluation of OmpSs-2@Cluster, a programming model and runtime system that extends the OmpSs-2 model to allow a virtually unmodified OmpSs-2 program to run across multiple distributed memory nodes. For well-balanced applications it provides similar performance to MPI+OpenMP on up to 16 nodes, and it improves performance by up to 2x for irregular and unbalanced applications like Cholesky factorization. This work also extended OmpSs-2@Cluster for interoperability with MPI and Barcelona Supercomputing Center (BSC)'s state-of-the-art Dynamic Load Balance (DLB) library in order to dynamically balance MPI+OmpSs-2 applications by transparently offloading tasks among nodes. This approach reduces the execution time of a mic, (Español) El modelo de programación dominante para clusters tanto en ciencia como industria es actualmente MPI+X. A pesar de que hay alguna variedad de alternativas para programar dentro de un nodo (indicado por la "X"), el estandar para programar múltiples nodos con memoria distribuida sigue siendo Message Passing Interface (MPI). Esta tesis propone la extensión del modelo de programación basado en tareas OmpSs-2 para su funcionamiento en sistemas de memoria distribuida, destacando 3 beneficios principales: En primer lugar; a pequeña y mediana escala, un modelo basado en tareas es más simple y productivo que MPI y elimina la necesidad de distribuir los datos explícitamente y convertir todas las dependencias en mensajes. Además, evita la complejidad de la programacion híbrida MPI+X. En segundo lugar; la capacidad de enviar partes del cálculo entre los nodos permite a la librería balancear la carga de trabajo en programas MPI+X a gran escala. Este enfoque no necesita un modelo de coste y permite equilibrar cargas transversalmente en todo el programa y todos los nodos. En tercer lugar; teniendo en cuenta que es la librería quien maneja todos los aspectos relacionados con distribución y transferencia de datos, es posible la modificación dinámica y transparente de los recursos que utiliza la aplicación. Esta tesis describe el diseño, desarrollo y evaluación de OmpSs-2@Cluster; un modelo de programación y librería que extiende OmpSs-2 permitiendo la ejecución de programas OmpSs-2 existentes en múltiples nodos sin prácticamente necesidad de modificarlos. Para aplicaciones balanceadas, este modelo proporciona un rendimiento similar a MPI+OpenMP hasta 16 nodos y duplica el rendimiento en aplicaciones irregulares o desbalanceadas como la factorización de Cholesky. Este trabajo incluye la extensión de OmpSs-2@Cluster para interactuar con MPI y la librería de balanceo de carga Dynamic Load Balancing (DLB) desarrollada en el Barcelona Supercomputing Center (BSC). De este modo e, Postprint (published version)

Aquest treball de final de grau és de la especialitat de Tecnologies de la Informació, impartida per la Facultat d'Informàtica de Barcelona a la Universitat Politècnica de Catalunya i realitzat per l'alumne Fermín Robledillo Ruiz. El projecte està desenvolupat en el BSC-CNS dins el departament d'Operacions i l'objectiu és instal·lar i configurar una eina open source del tipus DCIM per poder fer un inventari físic de les màquines disponibles i obtenir una visió virtual dels diferents CPD dels que disposa el centre., This final degree project is in the specialty of Information Technologies, taught by the Facultat d'Informàtica de Barcelona at the Universitat Politècnica de Catalunya and carried out by the student Fermín Robledillo Ruiz. The project is developed in the BSC-CNS within the Operations department and the aim is to install and configure a tool open source of the type DCIM to be able to make a physical inventory of the available machines and to obtain a vision virtual of the different CPDs available to the center.

Conforme la tecnologia ha anat avançant i fent-se mes complexa, la ciberseguretat ha esdevingut un factor clau per tal de garantir la seguretat dels sistemes de la informació. En aquest projecte s'ha desplegat un servei web amb l'objectiu de protegir-lo i monitoritzar-lo. Per a protegir-lo s'ha desplegat un WAF com un proxy invers entre el servidor web i el client final, i s'ha instal·lat el core rule set de l'OWASP per tal tenir un grup de regles de WAF que ens permetin detectar atacs contra el nostre servei. Addicionalment, s'ha afegit una regla addicional personalitzada per evitar l'explotació d'una vulnerabilitat del servei desplegat. Per a monitoritzar-lo s'ha fet ús d'un SIEM al núvol desplegant un col·lector que recull els esdeveniments que generen el servei web i el WAF. Un cop s'han començat a rebre esdeveniments al SIEM s'han extret els camps més importants d'aquests i s'han desenvolupat diferents alertes que ens notificaran en cas de detectar-se una anomalia o un comportament predeterminat. Addicionalment, s'ha creat un dashboard amb diferents panels que ofereixen una visualització clara del servei en temps real. Finalment, per comprovar que les mesures de seguretat aplicades han estat efectives s'han realitzat diferents escanejos de vulnerabilitats, verificant que conforme s'han implementat les diferents mesures de seguretat, el nombre de vulnerabilitats que es podien explotar s'ha vist reduït., As technology has advanced and being more complex, cybersecurity has become a key factor to guarantee the security of the information systems. In this project, a web service has been deployed in order to protect and monitor it. To protect it, a WAF has been deployed as a reverse proxy between the web server and the final client, and the OWASP core rule set has been installed to have a group of WAF rules that allow us to detect attacks against our service. Additionally, an additional custom rule has been added to avoid exploiting a vulnerability in the deployed service. To monitor it, a cloud-based SIEM has been used, deploying a collector that collects the events generated by the web service and the WAF. Once the events have begun to be received at the SIEM, the most important fields have been parsed and different alerts have been developed that will notify us in case of an anomaly has been detected or a predefined behaviour has occurred. Additionally, a dashboard has been created with different panels that offer a clear visualization of the service in real time. Finally, to verify that the security measures applied have been effective, different vulnerability scans have been carried out, verifying that as the different security measures have been implemented, the number of vulnerabilities that could be exploited has been reduced.

To achieve high performance and high energy efficiency on near-future exascale computing systems, three key technology gaps needs to be bridged. These gaps include: energy efficiency and thermal control; extreme computation efficiency via HW acceleration and new arithmetics; methods and tools for seamless integration of reconfigurable accelerators in heterogeneous HPC multi-node platforms. TEXTAROSSA aims at tackling this gap through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models and tools derived from European research., This work is supported by the TEXTAROSSA project G.A. n.956831, as part of the EuroHPC initiative., Peer Reviewed, Article signat per 51 autors/es: Giovanni Agosta, Daniele Cattaneo, William Fornaciari, Andrea Galimberti, Giuseppe Massari, Federico Reghenzani, Federico Terraneo, Davide Zoni, Carlo Brandolese (DEIB – Politecnico di Milano, Italy, name.surname@polimi.it) | Massimo Celino, Francesco Iannone, Paolo Palazzari, Giuseppe Zummo (ENEA, Italy, name.surname@enea.it) | Massimo Bernaschi, Pasqua D’Ambra (Istituto per le Applicazioni del Calcolo (IAC) - CNR, Italy, name.surname@cnr.it) | Sergio Saponara, Marco Danelutto, Massimo Torquati (University of Pisa, Italy, name.surname@unipi.it) | Marco Aldinucci, Yasir Arfat, Barbara Cantalupo, Iacopo Colonnelli, Roberto Esposito, Alberto R. Martinelli, Gianluca Mittone (University of Torino, Italy, name.surname@unito.it) | Olivier Beaumont, Berenger Bramas, Lionel Eyraud-Dubois, Brice Goglin, Abdou Guermouche, Raymond Namyst, Samuel Thibault (Inria - France, name.surname@inria.fr) | Antonio Filgueras, Miquel Vidal, Carlos Alvarez, Xavier Martorell (BSC - Spain, name.surname@bsc.es) | Ariel Oleksiak, Michal Kulczewski (PSNC, Poland, ariel@man.poznan.pl, kulka@man.poznan.pl) | Alessandro Lonardo, Piero Vicini, Francesca Lo Cicero, Francesco Simula, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Pier Stanislao Paolucci, Matteo Turisini (INFN Sezione di Roma - Italy, name.surname@roma1.infn.it) | Francesco Giacomini (INFN CNAF - Italy, name.surname@cnaf.infn.it) | Tommaso Boccali (INFN Sezione di Pisa - Italy, name.surname@pi.infn.it) | Simone Montangero (University of Padova and INFN Sezione di Padova - Italy, name.surname@pd.infn.it) | Roberto Ammendola (INFN Sezione di Roma Tor Vergata - Italy, name.surname@roma2.infn.it), Postprint (author's final draft)

This paper proposes the extension of task-based programming models with recurrent workloads concepts. The proposal introduces new clauses in the OmpSs task directive to efficiently model recurrent workloads. The clauses define the task period and/or the number of task body repetitions. Despite the new clauses are suitable for any device, their support has been implemented using the capabilities of FPGA devices in embedded systems. These heterogeneous systems are common in industrial applications that usually develop recurrent workloads. The evaluation shows a huge gap in the applications' programmability, saving lines of code, and increasing the code readability. Besides, it shows the efficient management of recurrent tasks when performed in FPGA devices, which can support one order of magnitude finer tasks. All these improvements perfectly suit the needs of cyber-physical heterogeneous systems, which are frequently used in industrial environments to run recurrent workloads., This work is partially supported by the European Union H2020 Research and Innovation Action (project 801051), by the Spanish Government (projects SEV-2015-0493 and PID2019-107255GB, grant BES-2016-078046), and by the Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017-SGR-1328)., Peer Reviewed, Postprint (author's final draft)

Recently, task-based programming models have emerged as a prominent alternative among shared-memory parallel programming paradigms. Inherently asynchronous, these models provide native support for dynamic load balancing and incorporate data flow concepts to selectively synchronize the tasks. However, tasking models are yet to be widely adopted by the HPC community and their effective advantages when applied to non-trivial, real-world HPC applications are still not well comprehended. In this paper, we study the parallelization of a production electromagnetic particle-in-cell (EM-PIC) code for kinetic plasma simulations exploring different strategies using asynchronous task-based models. Our fully asynchronous implementation not only significantly outperforms a conventional, synchronous approach but also achieves near perfect scaling for 48 cores., Peer Reviewed, Postprint (author's final draft)

This paper presents the new features of the OmpSs@FPGA framework. OmpSs is a data-flow programming model that supports task nesting and dependencies to target asynchronous parallelism and heterogeneity. OmpSs@FPGA is the extension of the programming model addressed specifically to FPGAs. OmpSs environment is built on top of Mercurium source to source compiler and Nanos++ runtime system. To address FPGA specifics Mercurium compiler implements several FPGA related features as local variable caching, wide memory accesses or accelerator replication. In addition, part of the Nanos++ runtime has been ported to hardware. Driven by the compiler this new hardware runtime adds new features to FPGA codes, such as task creation and dependence management, providing both performance increases and ease of programming. To demonstrate these new capabilities, different high performance benchmarks have been evaluated over different FPGA platforms using the OmpSs programming model. The results demonstrate that programs that use the OmpSs programming model achieve very competitive performance with low to moderate porting effort compared to other FPGA implementations., This work has received funding from EuroEXA project (European Union’s Horizon 2020 Research and Innovation Programme, under grant agreement No 754337), from Spanish Government (projects PID2019-107255GB and SEV-2015- 0493, grant BES-2016-078046), and Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017-SGR-1328)., Peer Reviewed, Postprint (author's final draft)

Recently, facial recognition systems have become extremely popular and deployments of this technology are now ubiquitous. Applications ranging from access control to automated surveillance of video feeds rely on facial recognition for precisely identifying persons at multiple locations. Modern facial recognition software targeting surveillance applications typically needs to analyze video streams in order to identify faces in crowds in real time. The first analytical step to be conducted in facial recognition systems is face detection, which mainly involves determining the precise coordinates and dimensions of all faces appearing on a given image or video frame, and constitutes the first major bottleneck in the pipeline. As opposed to other use cases such as image classification that usually work flawlessly with VGA images, surveillance applications require working with high or ultra high definition resolutions in order to be able to locate and correctly identify people in crowds. Consequently, in order to maximize the chances of obtaining facial mugshots with enough quality and pixel densities to enable accurate facial identification, it is a must to be able to develop algorithms and heuristics that are capable of working with big images. The main challenge is to perform all required computations involved in just a few milliseconds to avoid the slowdown of all subsequent stages of the facial recognition pipeline. In this thesis, we study several low-level parallelization techniques and kernels that efficiently solve the problem of face detection in a scalable manner over multithreaded data-parallel GPU architectures. The first part of the thesis covers a multilevel mechanism that exploits both coarse-grained and fine-grained parallelism in combination with a smart usage of local on-die memories to reduce GPU underutilization when evaluating boosted cascades of ensembles over high-definition videos. We demonstrate that our proposed parallelization strategy solves th, Actualment, els sistemes de reconeixement facial han augmentat la seva popularitat notablement i existeix una gran varietat de desplegaments de la tecnologia a escenaris molt diversos. Aplicacions com el control d'accés o la videovigilància automatitzada utilitzen algorismes de reconeixment facial per tal d'identificar persones de manera molt precisa a tot tipus d'ubicacions. Els sistemes de reconeixement facial optimitzats per a videovigilància massiva es basen en l'anàlisi exhaustiu en temps real de fotogrames a fluxes de vídeo per tal d'identificar cares en entorns multitudinaris. La primera etapa analítica emprada pels sistemes de reconeixement facial és la detecció facial. Aquesta etapa és l'encarregada de determinar de manera bastant exacte les coordenades i dimensions de totes les cares que apareixen en un fotograma de vídeo o imatge. La detecció facial constituteix, doncs, el principal coll d'ampolla al pipeline de reconeixement facial. A diferència d'altres casos d'ús com la classificació automatitzada d'imatges, que acostumen a funcionar òptimament amb imatges de resolució VGA, les aplicacions de videovigilància massiva automatitzada necessiten treballar amb resolucions d'alta o molt alta definició per tal de localitzar i identificar persones en entorns multitudinaris. Així doncs, per tal d'aconseguir augmentar les possibilitats de capturar imatges de cares amb suficient densitat de píxels i qualitat, és necessari desenvolupar algorismes i heurístiques que treballin a resolucions elevades. El principal repte consisteix en intentar executar tots els càlculs necessaris en uns pocs mil·lisegons per tal d'evitar retards inacceptables al computar les etapes posteriors a la detecció facial al pipeline de reconeixement facial. Aquesta tesi estudia diferents tècniques de paral·lelització a baix nivell i kernels que permeten resoldre de manera eficient el problema de la detecció facial escalable sobre arquitectures GPU multifil paral·leles. La primera part de la te, Postprint (published version)

In the context of object detection, sliding-window classifiers and single-shot convolutional neural network (CNN) meta-architectures typically yield multiple overlapping candidate windows with similar high scores around the true location of a particular object. Non-maximum suppression (NMS) is the process of selecting a single representative candidate within this cluster of detections, so as to obtain a unique detection per object appearing on a given picture. In this paper, we present a highly scalable NMS algorithm for embedded graphics processing unit (GPU) architectures that is designed from scratch to handle workloads featuring thousands of simultaneous detections on a given picture. Our kernels are directly applicable to other sequential NMS algorithms such as FeatureNMS, Soft-NMS or AdaptiveNMS that share the inner workings of the classic greedy NMS method. The obtained performance results show that our parallel NMS algorithm is capable of clustering 1024 simultaneous detected objects per frame in roughly 1 ms on both Tegra X1 and Tegra X2 on-die GPUs, while taking 2 ms on Tegra K1. Furthermore, our proposed parallel greedy NMS algorithm yields a 14–40x speed up when compared to state-of-the-art NMS methods that require learning a CNN from annotated data., This work has been partially supported by the Ministerio de Economía y Competitividad under contracts (TIN2015-65316-P, TEC2012-38939-C03-02), the Departament d’Innovació, Universitats i Empresa de la Generalitat de Catalunya under project MPEXPAR: Models de Programació i Entorns d’Execució Paral·lels (2014-SGR-1051), and the European Commission under the Horizon 2020 program (H2020-ICT-644312)., Peer Reviewed, Postprint (author's final draft)

Parallel task-based programming models, like OpenMP, allow application developers to easily create a parallel version of their sequential codes. The standard OpenMP 4.0 introduced the possibility of describing a set of data dependences per task that the runtime uses to order the tasks execution. This order is calculated using shared graphs, which are updated by all threads in exclusive access using synchronization mechanisms (locks) to ensure the dependence management correctness. The contention in the access to these structures becomes critical in many-core systems because several threads may be wasting computation resources waiting their turn. This paper proposes an asynchronous management of the runtime structures, like task dependence graphs, suitable for task-based programming model runtimes. In such organization, the threads request actions to the runtime instead of doing them directly. The requests are then handled by a distributed runtime manager (DDAST) which does not require dedicated resources. Instead, the manager uses the idle threads to modify the runtime structures. The paper also presents an implementation, analysis and performance evaluation of such runtime organization. The performance results show that the proposed asynchronous organization outperforms the speedup obtained by the original runtime for different benchmarks and different many-core architectures., This work is partially supported by the European Union H2020 Research and Innovation Action (projects 801051, 754337 and 780681), by the Spanish Government (projects SEV-2015-0493 and TIN2015-65316-P, grant BES-2016-078046), and by the Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017-SGR-1328)., Peer Reviewed, Postprint (author's final draft)

En un centre de recerca com el BSC es va identificar que la compartició de fitxers no estava ben solucionada en el model implantat actualment. S'ha fet una recerca entre diferents solucions i s'ha trobat que Nextcloud és el producte que compleix més requeriments pel que fa al producte que busquem. S'hi ha realitzat un disseny del sistema final que inclou un backend i un frontend. El backend està compost pels diferents serveis que necessita la plataforma per funcionar, que són Apache, MariaDB, PHP i Redis. Dintre del backend també hem afegit un servei de Docker per poder executar un contenidor de paquets amb la plataforma OnlyOffice de manera que els diferents usuaris de Nextcloud puguin editar fitxers concurrentment. També dintre del backend s'ha habilitat la connexió amb el servidor de LDAP del centre per utilitzar els usuaris ja existents. En la part del frontend tenim les diferents interfícies web que es trobaran els usuaris quan es connectin amb el navegador sigui per compartir arxius o per poder editar documents. S'ha realitzat el pas a producció aplicant un monitoreig als diferents serveis de manera que en cas d'alguna fallada ens salta una alarma i podem actuar en conseqüència. Una vegada testejat amb usuaris s'ha comprovat que la majoria de requeriments que teníem al principi del projecte es compleixen correctament exceptuant dos casos determinats: el bloqueig de fitxers no és suportat per aquesta plataforma i el mapeig a Windows d'una unitat per protocol de xarxa DAV és problemàtic perquè la implementació d'aquest protocol en Windows és defectuosa. Finalment s'han fet diferents tests d'usuaris per comprovar que la interfície web funciona correctament i tests d'escalabilitat comprovant mesures de rendiment de CPU, memòria i xarxa per veure que l'aplicació no carrega el servidor excessivament., We have identified that the file-sharing between users is not working correctly in BSC. Research has been done between different solutions and it has been found that Nextcloud is the product that fits best with our problem. The design of the system includes the backend and the frontend. The backend is composed of all the different services the platform needs to work, which are Apache, MariaDB, PHP, and Redis. Inside backend, we can also find Docker service, to execute OnlyOffice software where the users can edit concurrently among other users, and connection to the LDAP server, where we take the information users. Inside the frontend, we have different web interfaces that users found when they connect to the system. The transition to production has been done applying monitoring to the different services so in the case one of them fails we will receive an alarm. Once tested with users, we can say that the majority of the initial requirements we had at the beginning of the project are fulfilled correctly except in two certain cases: file locking is not supported on this platform and network mapping using the DAV protocol because of the implementation of this protocol in certain operating systems. Finally, we've done many user tests to prove the web interface and some scalability tests to check the status of CPU, memory, and network and see how the system charge is affected.

The LEGaTO project leverages task-based programming models to provide a software ecosystem for Made in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC, balanced with the security and resilience challenges. LEGaTO is an ongoing three-year EU H2020 project started in December 2017., This project has received funding from the European Union Horizon 2020 research and innovation programme under the LEGaTO Project(legato- project.eu), grant agreement No 780681., Peer Reviewed, Postprint (author's final draft)

We present a novel approach to parallelize the SpMV kernel included in LASs (Linear Algebra routines on OmpSs) library, after a deep review and analysis of several well-known approaches. LASs is based on OmpSs, a task-based runtime that extends OpenMP directives, providing more flexibility to apply new strategies. Based on tasking and nesting, with the aim of improving the workload imbalance inherent to the SpMV operation, we present a strategy especially useful for highly imbalanced input matrices. In this approach, the number of created tasks is dynamically decided in order to maximize the use of the resources of the platform. Throughout this paper, SpMV behavior depending on the selected strategy (state of the art and proposed strategies) is deeply analyzed, setting in this way the base for a future auto-tunable code that is able to select the most suitable approach depending on the input matrix. The experiments of this work were carried out for a set of 12 matrices from the Suite Sparse Matrix Collection, all of them with different characteristics regarding their sparsity. The experiments of this work were performed on a node of Marenostrum 4 supercomputer (with two sockets Intel Xeon, 24 cores each) and on a node of Dibona cluster (using one ARM ThunderX2 socket with 32 cores). Our tests show that, for Intel Xeon, the best parallelization strategy reduces the execution time of the reference MKL multi-threaded version up to 67%. On ARM ThunderX2, the reduction is up to 56% with respect to the OmpSs parallel reference., This project has received funding from the Spanish Ministry of Economy and Competitiveness under the project Computación de Altas Prestaciones VII (TIN2015- 65316-P), the Departament d’Innovació, Universitats i Empresa de la Generalitat de Catalunya, under project MPEXPAR: Models de Programació i Entorns d’Execució Parallels (2014-SGR-1051), and the Juan de la Cierva Grant Agreement No IJCI-2017- 33511, and the Spanish Ministry of Science and Innovation under the project Heterogeneidad y especialización en la era post-Moore (RTI2018-093684-BI00). We also acknowledge the funding provided by Fujitsu under the BSC-Fujitsu joint project: Math Libraries Migration and Optimization, Peer Reviewed, Postprint (author's final draft)

© 2019 Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0, In this work we have implemented a novel Linear Algebra Library on top of the task-based runtime OmpSs-2. We have used some of the most advanced OmpSs-2 features; weak dependencies and regions, together with the final clause for the implementation of auto-tunable code for the BLAS-3 trsm routine and the LAPACK routines npgetrf and npgesv. All these implementations are part of the first prototype of sLASs library, a novel library for auto-tunable codes for linear algebra operations based on LASs library. In all these cases, the use of the OmpSs-2 features presents an improvement in terms of execution time against other reference libraries such as, the original LASs library, PLASMA, ATLAS and Intel MKL. These codes are able to reduce the execution time in about 18% on big matrices, by increasing the IPC on gemm and reducing the time of task instantiation. For a few medium matrices, benefits are also seen. For small matrices and a subset of medium matrices, specific optimizations that allow to increase the degree of parallelism in both, gemm and trsm tasks, are applied. This strategy achieves an increment in performance of up to 40%., This project has received funding from the Spanish Ministry of Economy and Competitiveness, Spain under the project Computación de Altas Prestaciones VII (TIN2015- 65316-P), the Departament d’Innovació, Universitats i Empresa de la Generalitat de Catalunya, Spain, under project MPEXPAR: Models de Programació i Entorns d’Execució Parallels (2014-SGR-1051), and the Juan de la Cierva Grant Agreement No IJCI-2017- 33511. We also acknowledge the funding provided by Fujitsu, Japan under the BSC-Fujitsu joint project: Math Libraries Migration and Optimization., Peer Reviewed, Postprint (author's final draft)

OpenMP is a very convenient programming model to parallelize critical real-time applications for several reasons: (1) it provides a powerful tasking model useful for exploiting unstructured and highly dynamic parallelism; (2) the accelerator model allows for offloading computation from the host to an accelerator while hiding the complexities of the target architecture; (3) current studies have shown the tasking model is time predictable; (4) current studies have delimited the functional safe aspects of the specification; and (5) it is widely supported by compiler and chip vendors, providing great portability. Despite all the benefits of OpenMP, there are some aspects of the current runtime implementations that makes them unsuitable for critical environments. These are mainly two: (1) tasks are allocated when they are encountered and, as a result, the runtime system makes an intensive use of dynamically allocated memory in order to efficiently manage the parallel execution; and (2) the total amount of memory used is directly proportional to the amount of on-the-fly tasks. These aspects jeopardize the qualification processes needed to ensure that the integrated software stack is compliant with system requirements. This work tackles the previously mentioned limitations with the aim of reducing the gap between OpenMP implementations and critical real-time requirements. Particularly, it proposes a novel OpenMP framework that statically allocates the data structures needed to efficiently manage the parallel execution of OpenMP tasks. The framework is composed of (1) a compiler phase that captures the environment of the OpenMP tasks instantiated along the parallel execution and bounds the amount of memory needed to fully exploit the parallelism exposed in the applications, and (2) a runtime system implementing a lazy task creation policy that significantly reduces the runtime memory requirements, whilst exploiting parallelism efficiently. Furthermore, this work contributes

The majority of current HPC applications are composed of complex and irregular data structures that involve techniques such as linear algebra, graph algorithms, and resource management, for which new platforms with varying computation-unit capacity and features are required. Platforms using several cores with different performance characteristics make a challenge the selection of the best programming model, based on the corresponding executing algorithm. To make this study, there are approaches in the literature, that go from comparing in isolation the corresponding programming models’ primitives to the evaluation of a complete set of benchmarks. Our study shows that none of them may provide enough information for a HPC application to make a programming model selection. In addition, modern platforms are modifying the memory hierarchy, evolving to larger shared and private caches or NUMA regions making the memory wall an issue to consider depending on the memory access patterns of applications. In this work, we propose a methodology based on Parallel Programming Patterns to consider intra and inter socket communication. In this sense, we analyze MPI, OpenMP and the hybrid solution MPI/OpenMP in shared-memory environments. We demonstrate that the proposed comparison methodology may give more accurate predictions in performance for given HPC applications and consequently a useful tool to select the appropriate parallel programming model., This research was supported by the following grants Spanish Ministry of Science and Innovation (contract TIN2015-65316), the Generalitat de Catalunya (2014- SGR-1051) and the the European Commission through the HiPEAC-3 Network of Excellence (FP7/ICT-217068)., Peer Reviewed, Postprint (author's final draft)

This paper proposes to enhance current task-based programming models by breaking their current master-slave approach between the main processor and its hardware accelerators. As a proof-of-concept, it presents an extension of the OmpSs@FPGA toolchain that allows the tasks offloaded into the FPGA to create and synchronize nested tasks on their own without involving the host. Those FPGA spawned tasks may target the host to execute code not suitable for the FPGA, like system calls or I/O operations; or target other kernel accelerators inside the same FPGA. In addition to the programmability benefits of this new feature, the proposed system presents significant performance improvements and a better productivity over the classical master-slave approach., This work has received funding from EPEEC project (Euro-pean Union’s Horizon 2020 Research and Innovation Pro-gramme, under grant agreement No 801051), from SpanishGovernment (projects SEV-2015-0493 and TIN2015-65316-P,grant BES-2016-078046), and from Generalitat de Catalunya(contracts 2017-SGR-1414 and 2017-SGR-1328)., Peer Reviewed, Postprint (published version)

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works., OmpSs@FPGA is the flavor of OmpSs that allows offloading application functionality to FPGAs. Similarly to OpenMP, it is based on compiler directives. While the OpenMP specification also includes support for heterogeneous execution, we use OmpSs and OmpSs@FPGA as prototype implementation to develop new ideas for OpenMP. OmpSs@FPGA implements the tasking model with runtime support to automatically exploit all SMP and FPGA resources available in the execution platform. In this paper, we present the OmpSs@FPGA ecosystem, based on the Mercurium compiler and the Nanos++ runtime system. We show how the applications are transformed to run on the SMP cores and the FPGA. The application kernels defined as tasks to be accelerated, using the OmpSs directives are: 1) transformed by the compiler into kernels connected with the proper synchronization and communication ports, 2) extracted to intermediate files, 3) compiled through the FPGA vendor HLS tool, and 4) used to configure the FPGA. Our Nanos++ runtime system schedules the application tasks on the platform, being able to use the SMP cores and the FPGA accelerators at the same time. We present the evaluation of the OmpSs@FPGA environment with the Matrix Multiplication, Cholesky and N-Body benchmarks, showing the internal details of the execution, and the performance obtained on a Zynq Ultrascale+ MPSoC (up to 128x). The source code uses OmpSs@FPGA annotations and different Vivado HLS optimization directives are applied for acceleration., This work is partially supported by the European Union H2020 program through the EuroEXA project (grant 754337), and HiPEAC (GA 687698), by the Spanish Government through Programa Severo Ochoa (SEV-2015- 0493), by the Spanish Ministry of Science and Technology (TIN2015-65316-P) and the Departament d’Innovació Universitats i Empresa de la Generalitat de Catalunya, under project MPEXPAR: Models de Programació i Entorns d’Execució Paral·lels (2014-SGR-1051)., Peer Reviewed, Postprint (author's final draft)

Static code analysis tools are designed to aid software developers to build better quality software in less time, by detecting defects early in the software development life cycle. Even the most experienced developer regularly introduces coding defects. Identifying, mitigating and resolving defects is an essential part of the software development process, but frequently defects can go undetected. One defect can lead to a minor malfunction or cause serious security and safety issues. This is magnified in the development of the complex parallel software required to exploit modern heterogeneous multicore hardware. Thus, there is an urgent need for new static code analysis tools to help in building better concurrent and parallel software. The paper reports preliminary results about the use of Appentra’s Parallelware technology to address this problem from the following three perspectives: finding concurrency issues in the code, discovering new opportunities for parallelization in the code, and generating parallel-equivalent codes that enable tasks to run faster. The paper also presents experimental results using well-known scientific codes and POWER systems., This work has been partly funded from the Spanish Ministry of Science and Technology (TIN2015-65316-P), the Departament d’Innovació, Universitats i Empresa de la Generalitat de Catalunya (MPEXPAR: Models de Programació i Entorns d’Execució Parallels, 2014-SGR-1051), and the European Union’s Horizon 2020 research and innovation program throughgrant agreements MAESTRO (801101) and EPEEC (801051)., Peer Reviewed, Postprint (author's final draft)

In this paper we propose a set of optimizations for the BLAS-3 routines of LASs library (Linear Algebra routines on OmpSs) and perform a detailed analysis of the impact of the proposed changes in terms of performance and execution time. OmpSs allows to use regions in the dependences of the tasks. This helps not only in the programming of the algorithmic optimizations, but also in the reduction of the execution time achieved by such optimizations. Different strategies are implemented in order to reduce the amount of tasks created (when there is enough parallelism) during the execution of BLAS-3 operations in the original LASs. Also a better IPC is obtained thanks to a better memory hierarchy exploitation. More specifically, we increase the performance, in particular on big matrices, about 12% for TRSM, and 17% for GEMM with respect to the original version of LASs, even using less cores in the case of GEMM/SYMM. Moreover, when LASs is compared to the OpenMP reference dense linear algebra library PLASMA, performance is increased up to 12.5% for GEMM/SYMM, while for TRSM/TRMM this value raises to 15%., This project has received funding from the Spanish Ministry of Economy and Competitiveness under the project Computacion de Altas Prestaciones VII (TIN2015-65316-P), the Departament d’Innovacio, Universitats i Empresa de la Generalitat de Catalunya, under project MPEXPAR: Models de Programacio i Entorns d’Execució Parallels (2014-SGR-1051), and the Juan de la Cierva Grant Agreement No IJCI2017-33511. We also acknowledge the funding provided by Fujitsu under the BSC-Fujitsu joint project: Math Libraries Migration and Optimization., Peer Reviewed, Postprint (author's final draft)

La computació heterogènia amb FPGAs és una alternativa de baix consum a altres sistemes usats freqüentment, com la computació amb CPU multi-nucli i la computació heterogènia amb GPUs. No obstant, degut a que les FPGAs funcionen d'una manera totalment diferent a altres dispositius fets servir en computació, són bastant difícils de comparar. La Rodinia Benchmark Suite està formada per aplicacions que poden usar-se per comparar sistemes de computació heterogenis. La suite ha adaptat les aplicacions per computació amb CPU multi-nucli i computació amb GPU (fent servir les llibreries OpenMP, Cuda, OpenCL). L'objectiu del projecte és adaptar un cert nombre d'aquestes aplicacions per OmpSs@FPGA, un sistema de computació heterogeni amb dispositius FPGA de Xilinx. Algunes d'aquestes aplicacions també seran optimitzades fent servir eines de OmpSs i de Xilinx (Vivado HLS). Tot i que al principi la idea era adaptar i provar les aplicacions en el dispositiu FPGA físic, la absència del hardware durant la primera part de la fase d'adaptació va incentivar el desenvolupament d'un entorn de simulació de dispositius FPGA. Tal cosa va implicar modificar el runtime per fer que es comuniqués amb un programa software enlloc d'intentar accedir al hardware real. Aquesta tasca va afegir una càrrega de treball considerable en el projecte que no estava prevista. Tot i així, degut a que aquest entorn de simulació va fer molt més ràpida l'adaptació de les aplicacions, la quantitat d'hores amb les que es va desenvolupar l'entorn i es van adaptar les aplicacions va coincidir amb les hores previstes inicialment només per l'adaptació. Es van adaptar un total de 7 aplicacions, 6 de les quals es van optimitzar fins a cert punt. També es van analitzar totes les optimitzacions parcials acumulatives fent servir traces d'execució visualitzades amb el software Paraver. Un cop fets els anàlisis, es va fer un informe de sostenibilitat per avaluar l'impacte del projecte en els aspectes ambiental, econòmic i so, FPGA computing is a low power alternative to the vastly used multi-core CPU and GPU computing systems. However, due to FPGA devices being completely different in terms of architecture, they are quite complex to compare to other forms of computing. Rodinia Benchmark Suite consists of a number of applications that can be used to benchmark heterogeneous computing systems. The suite has currently adapted the applications for multi-core CPU and GPU computing (using OpenMP, Cuda and OpenCL libraries). The objective of this project is to port some of the applications from the Rodinia Benchmark Suite to OmpSs@FPGA, a heterogeneous FPGA computing environment based on Xilinx FPGA devices. A portion of these applications will also be optimized using both OmpSs features and Xilinx tools (Vivado HLS). While the original intentions were to port and test the applications with a physical FPGA device, the lack of access to the hardware during the initial porting phase encouraged the development of a simulated FPGA environment. This implied modifying the runtime to communicate with a software block running as an executable instead of trying to access the real hardware. Even though it added a significant workload to the project that was not intended at first, it ended up making the porting of the applications much faster than with the real hardware. Ultimately, the expected number of hours from the initial planning matched the hours it took to both develop the simulated environment and the applications. A total of 7 applications were ported to the OmpSs@FPGA environment, 6 of which were optimized to a certain extent. Furthermore, each of the accumulated optimization stages for every optimized application was analyzed and explained using Paraver traces. After that, a sustainability report was made in order to evaluate the impact of the project environmentally, economically and socially wise. In the final conclusions, it is stated that the original objective of the project has been fulf

In this thesis, the OmpSs@FPGA tool chain has been extended to try to reduce the overall communication time due to copies of data when it is possible to reuse data already in the BRAM of the accelerators.

© <2018>. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0, The emergence of heterogeneous systems has been very notable recently. The nodes of the most powerful computers integrate several compute accelerators, like GPUs. Profiting from such node configurations is not a trivial endeavour. OmpSs is a framework for task based parallel applications, that allows the execution of OpenCl kernels on different compute devices. However, it does not support the co-execution of a single kernel on several devices. This paper presents an extension of OmpSs that rises to this challenge, and presents Auto-Tune, a load balancing algorithm that automatically adjusts its internal parameters to suit the hardware capabilities and application behavior. The extension allows programmers to take full advantage of the computing devices with negligible impact on the code. It takes care of two main issues. First, the automatic distribution of datasets and the management of device memory address spaces. Second, the implementation of a set of load balancing algorithms to adapt to the particularities of applications and systems. Experimental results reveal that the co-execution of single kernels on all the devices in the node is beneficial in terms of performance and energy consumption, and that Auto-Tune gives the best overall results., Peer Reviewed, Preprint

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works., The AXIOM project aims at providing an environment for Cyber-Physical Systems. Smart Video Surveillance targets public environments, involving real-time face detection in crowds. Smart Home Living targets home environments and access control. These applications are used as experimental usecases for the AXIOM platform, currently based on the Xilinx Zynq-7000 SoCs. We have integrated the Xilinx Vivado HLS tool for the FPGA support within the OmpSs programming model, to enable OpenMP-like programming in the FPGA. This paper presents the programming environment, and the evaluation of the most computationally expensive parts of the target applications., Peer Reviewed, Postprint (author's final draft)

Utilitat via línea de comandes que genera un sistema automàtic per a la integració contínua i l'entrega contínua amb Jenkins., A command line utility that creates a continuous integration and continuous delivery system with Jenkins.