140 results on '"Martino, J.A."'
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2. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications
3. Gate dielectric material influence on DC behavior of MO(I)SHEMT devices operating up to 150 °C
4. Optimization of a nanoribbon charge-based biosensor using gateless BESOI pMOSFET structure
5. An enzymatic glucose biosensor using the BESOI MOSFET
6. Tradeoff between the transistor reconfigurable technology and the zero-temperature-coefficient (ZTC) bias point on BESOI MOSFET
7. Experimental analysis and improvement of the DC method for self-heating estimation
8. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs
9. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs
10. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics
11. Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications
12. GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics
13. Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation
14. Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs
15. Cryogenic operation of FinFETs aiming at analog applications
16. Harmonic distortion of unstrained and strained FinFETs operating in saturation
17. Low temperature influence on the uniaxially strained FD SOI nMOSFETs behavior
18. Evaluation of triple-gate FinFETs with SiO 2–HfO 2–TiN gate stack under analog operation
19. The low-frequency noise behaviour of graded-channel SOI nMOSFETs
20. 50 nm Gate Length FinFET Biosensor & the Outlook for Single-Molecule Detection
21. The temperature mobility degradation influence on the zero temperature coefficient of partially and fully depleted SOI MOSFETs
22. Investigation of back gate interface states by drain current hysteresis in PD-SOI n-MOSFETs
23. Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs
24. Transient effects in accumulation mode p-channel SOI MOSFET's operating at 77 K
25. Thin Si channel Back Enhanced (BE) SOI pMOSFET Photodetector under different bias conditions
26. Performance evaluation of Tunnel-FET basic amplifier circuits
27. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices
28. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs
29. Extraction of the lightly doped drain concentration of fully depleted SOI NMOSFETs using the back gate bias effect
30. A Tunnel-FET device model based on Verilog-A applied to circuit simulation
31. Back Enhanced (BE) SOI MOSFET under non-conventional bias conditions
32. The Smaller the Noisier? Low Frequency Noise Diagnostics of Advanced Semiconductor Devices
33. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
34. Body factor scaling in UTBB SOI with supercoupling effect
35. Low-Frequency Noise in High-K and SiO2 UTBOX SOI nMOSFETS
36. Low frequency noise assessment in advanced UTBOX SOI n-channel MOSFETs
37. Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs
38. Detailed analysis of transport properties of FinFETs through Y-Function method: Effects of substrate orientation and strain
39. The smaller the noisier? Low frequency noise diagnostics of advanced semiconductor devices
40. Magnetoresistance technique for mobility extraction in triple gate FinFETs at low temperature
41. Indigenous and introduced species of the Bemisia tabaci complex in sweet potato crops from Argentina
42. Detailed analysis of transport properties of FinFETs through Y-Function method: Effects of substrate orientation and strain.
43. The smaller the noisier? Low frequency noise diagnostics of advanced semiconductor devices.
44. Impact of temperature reduction and channel engineering on the linearity of FD SOI nMOSFETs
45. Potential and limitations of UTBB SOI for advanced CMOS technologies
46. Low-frequency noise behavior of graded-channel SOI n-MOSFETs
47. Analysis on the improved analog performance on double gate transistors by using the graded-channel architecture in a wide temperature range
48. Reliability performance characterization of SOI FinFETs
49. Impact of TiN metal gate thickness and the HfSiO nitridation on MuGFETs electrical performance
50. Modelling of the leakage drain current in accumulation-mode SOI pMOSFETs for high-temperature applications
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