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We present gas sensor devices based on nanocrystalline SnO 2 films, which are integrated on CMOS fabricated micro-hotplate (μhp) chips. Bimetallic nanoparticles (NPs) such as PdAu, PtAu, and PdPt have been synthesized for optimizing the sensing performance of these sensors. We demonstrate that proper functionalization with PdAu-NPs leads to a strongly improved sensitivity to the toxic gas carbon monoxide while the cross sensitivity to humidity and carbon dioxide is almost completely suppressed, which is of high importance for real life environmental conditions. We also present μhp chips employing Through-Silicon-Via (TSV) technology, which are capable for flexible 3D-integration of different types of gas sensors to a multi-parameter nanosensor system. Such CMOS integrated systems are promising candidates for realizing smart sensor devices for consumer market applications.

One of the main issues for the simulation of MOS transistors is the correct prediction of threshold voltages that depend on the active doping profiles in the channel under the gate oxide. Simulating a power MOS process we encountered a situation in which Sentaurus Process with default models failed to predict threshold voltages by as much as 3 V. An in-depth investigation revealed that the threshold voltage in our pMOS devices is determined by a very special distribution of the doping in the channel that involves both n-type and p-type doping which nearly compensate each other. As threshold voltages were found in the simulations to be particularly sensitive to boron segregation, silicon samples were implanted with boron and oxidized in several atmospheres for a variety of process times. The profiles were studied by advanced SIMS methods. Because of the limitations of the SIMS depth resolution, they had to be complemented by electrical measurements on MOS transistors. This combination finally allowed finding a new calibration for the segregation models which allows predicting the electrical characteristics of the transistors in a wide range of experimental conditions. Since the threshold voltage in our transistors turned out to be extremely sensitive to the boron segregation parameters, in contrast to technologies in which only one dopant type prevails, the newly achieved calibration should be superior to previous work. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Key end user applications, such as Internet of Things (IoT), automotive, mobile internet and wearable devices, require smaller, denser and more complex packages with increased performance, all at a low power usage. Innovative front end technologies enabling transistor downscaling towards 10 nm pave the way for small pitch components with an increased I/O count, thus leading to a packaging technology revolution from simple wire bond assembly over BGA/flip chip applications towards stacked 3D-structures with through silicon vias (TSVs), micro bumps and thin dies. 3D die to wafer (D2W) stacking therefore becomes an essential and cost effective option in order to further optimize the form factor. Moreover, by stacking components onto each other instead of placing them next to each other, performance increases can be obtained due to shorter signal paths and higher possible frequencies. The work described in this paper elaborates flip chip stacking processes in combination with TSV technology for More-than-Moore (MtM) heterogeneous 3D-Wafer-Level-Chip-Scale-Package (WLCSP) integration, targeting applications in harsh environments with high demands on product reliability. The major objective comprises the proof of manufacturability at competitive costs. In addition the devices were tested against harsh automotive conditions that are present near the alternator, featuring high temperatures up to 200 °C.

We present H 2 S gas sensor devices based on tungsten oxide nanowire networks, which are integrated on CMOS fabricated microhotplate chips. Such CMOS integrated systems are promising candidates for realizing smart sensor devices for consumer market applications. The CMOS tungsten oxide gas sensors were prepared by the deposition of nanowire networks onto interdigitated electrodes on CMOS microhotplates via drop-coating. Drop-coating of a nanowire suspension represents a simple and cost-effective technique for mass production of tungsten oxide nanowire network gas sensors. Utilizing this tungsten oxide nanowire network as gas sensing material we could obtain extraordinary sensitivity to H 2 S: concentrations down to 100 ppb have been detected at different humidity levels. An optimum operating temperature could be determined, where the different humidity levels do not affect the sensor performance.

Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded non-volatile memory. In this work we propose a new 0.35 µm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 µm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 °C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM/Flash technology is shown. We also provide first verification results of the scalability of the proposed 0.35 µm HVCMOS technology to 0.18 µm and beyond as well as to currents of up to 8 A.

We present gas sensor devices based on ultrathin SnO2 films, which are integrated on CMOS fabricated micro- hotplate (µhp) chips. Bimetallic nanoparticles (NPs) such as PdAu, PtAu, and PdPt have been synthesized for optimizing the sensing performance of these sensors. We demonstrate that functionalization of nanocrystalline SnO2 gas sensing films with PdAu-NPs leads to a strongly improved sensitivity to the toxic gas carbon monoxide (CO) while the cross sensitivity to humidity is almost completely suppressed. We conclude that specific functionalization of CMOS integrated SnO2 thin film gas sensors with different types of NPs is a powerful strategy towards sensor arrays capable for distinguishing several target gases. Such CMOS integrated arrays are highly promising candidates for realizing smart multi-parameter sensing devices for the consumer market.

3D integration of functions such as sensors and circuit elements enables miniaturized and cost-effective smart systems. Wirebonds are replaced by Through Silicon Vias (TSVs) and Wafer Level Packaging (WLP) for shorter conductive paths and reduced form factor. This paper reviews prior art and presents a comprehensive set of data from volume manufacturing of 3D integrated optical sensors and circuits using a “via last” manufacturing flow. 3D specific yield detracting processes such as patterning of open TSVs, wafer bonding, and etching are analyzed and discussed. Functional test yields equivalent to standard CMOS process yields can be achieved.

We present performance results of SnO 2 and CuO nanowire gas sensor devices, where single and multi-nanowire device configurations have been employed in order to optimize sensor design. In particular the response to the target gases CO, H 2 , and H 2 S has been measured in dry and humid air; both the SnO 2 and CuO nanowire sensors are able to detect CO in the low ppm concentration range, which is important for environmental monitoring. The CuO multi-nanowire devices show an extraordinary high response to H 2 S with sensitivity in the low ppb concentration. We present our developments of CMOS technology based micro-hotplates, which are employed as platform for gas sensitive thin films and nanowires. Potential heterogeneous integration of nanowires on the micro-hotplate chips as well as an approach towards gas sensor arrays is discussed. We conclude that CMOS integrated multi-nanowire gas sensors are highly promising candidates for the practical realization of multi-parameter sensor devices for indoor and outdoor environmental monitoring.

For competitive high-voltage (HV) integrated circuit (IC) products an excellent trade-off between specific on-resistance Ron,sp and breakdown voltage BV of a HV lateral DMOS (LDMOS) transistor, while keeping low fabrication cost, is mandatory. This paper presents a review of the HVIC technology trend with special emphasis on cost effective 0.35 μm and 0.18 μm HV-CMOS technologies. Through optimized process setup and device engineering a very competitive Ron,sp-BV trade-off of a HV LDMOS transistor without degrading the low-voltage (LV) CMOS performance has been achieved. A 0.35μm HV-CMOS technology with LDMOS transistor operating voltages from 20V to 120V is reported. Only two mask level adders on top of standard CMOS are required to provide the full set of 3.3V, 5V and 20V-120V HV devices. This is the result of taking advantage of predictive TCAD which enables early optimization of device layouts and dopant concentrations. In addition, HV and LV process integration issues of a 0.18 μm HV-CMOS technology, which play a key role to efficiently implement a HV module into a deep submicron CMOS process, are described. Key issues of p-channel LDMOS transistors are reviewed. The hot-carrier (HC) behaviour of a 50 V p-channel LDMOS transistor is presented too.

This work shows for the first time the presence of erratic phenomena in p-channel floating gate memories using Fowler Nordheim tunneling for both program and erase operations. A specific p-channel EEPROM architecture is investigated and found to be intrinsically robust against erratic behaviors. A comparison between the p-channel device and a conventional n-channel Flash is discussed and physical interpretations are suggested.

A highly reliable and scalable non-volatile embedded memory cell and technology is described. This embedded technology operates at very low power, and has minimal impact on the analog and digital components used in the SoC design. The main objective of this technology development was to achieve high reliability and high data retention for automotive applications over the extended temperature range from -40/spl deg/ to 150/spl deg/ C. A wider range, from -55/spl deg/ to 180/spl deg/ C, has been achieved in manufacturing. Full cell, and memory module functionality, and data retention of over 30 years for the automotive temperature range have been achieved. Write cycling of over 200K writes (tested up to 180/spl deg/C) over the design temperature range has also been achieved. The memory cell and the technology are optimized to operate at very low voltage and consume very low power. The applications requiring high data retention (>50 years), over the industrial or automotive temperature range can be well served with this technology. The data confirms that this technology is a highly manufacturability and a reliable technology for the embedded non-volatile memory applications. The data presented is based on a 0.35/spl mu/m CMOS technology implementation.

This paper presents one of the first fully functional FlexRay transceivers manufactured in a 0.35 mum CMOS high-voltage technology, which provides high voltage MOS devices together with standard 3.3 V gates. The circuit operates as interface between a generic controller and the copper wire FlexRay physical bus, to be used in fault tolerant and fail safe applications. In particular, the transceiver meets the operating requirements of the automotive environment. The design was validated by means of simulations and experimental measurements on fabricated prototypes

With the continuing scaling of metal–oxide–semiconductor (MOS) devices, the hot-carrier (HC)-induced device degradation has become a major reliabiliy concern in sub- and deep-submicrometre MOS field-effect transistors (MOSFETs) and lateral double-diffused MOSFETs (LDMOSFETs). It is believed that the degradation is mainly due to the effects of the generated oxide-trapped charges and interface traps at the Si/SiO2 interface. In general, the large electric field is strongly localised in a well-defined region; therefore carrier injection and interface-trap creation are similarly concentrated. The strongly inharmonious characters of HC injection and resulting damage present a considerable challenge to both experimental and modelling efforts.The HC degradation behaviour of an n-channel LDMOS transistor is investigated under various stress conditions. By applying variable base charge pumping experiments, a consistent picture of the degradation mechanism can be depicted. HC-induced interface traps are generated in the channel region of the device, in the drift region below the thick field oxide and at the bird's beak edge. The latter is shown to dominate the degradation of Idlin, which is the most critical parameter concerning HC lifetime in this specific device.