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Near InfraRed (NIR) photon emission is observed from filaments in HfO2 Resistive Random Access Memories (ReRAMs). This technique is non-destructive and offers rapid localization of filaments, enabling statistical analysis of their spatial distribution. We show that the emission is electric-field driven. We also report direct experimental evidence of ${i}$ ) completely random spatial distribution of filaments across multiple devices and ii ) formation of multiple filaments inside a single large device.

In this paper, we discuss the use of spontaneous photon emission microscopy (PEM) for observing filaments formed in HfO2 resistive random access memory (ReRAM) cells. The setup employs a CCD and an InGaAs camera, revealing photon emissions in both forward (set) and reverse (reset) bias conditions. Photon emission intensity is modeled using an electric-field equation and inter-filament distance and density are determined assuming a uniform spatial distribution. The paper also discusses the use of high frame rate and prolonged photon emission measurements to assess lifetime and reliability and explains how single filament fluctuations and multiple filaments in a single cell were observed for the first time.

We consider existing and emerging neural workloads, and what hardware accelerators might be best suited for said workloads. We begin with a discussion of analog crossbar arrays, which are known to be well-suited for matrix-vector multiplication operations that are commonplace in existing neural network models such as convolutional neural networks (CNNs). We highlight candidate crosspoint devices, what device and materials challenges must be overcome for a given device to be employed in a crossbar array for a computationally interesting neural workload, and how circuit and algorithmic optimizations may be employed to mitigate undesirable characteristics from devices/materials. We then discuss two emerging neural workloads. We first consider machine learning models for one- and few-shot learning tasks (i.e., where a network can be trained with just one or a few, representative examples of a given class). Notably crossbar-based architectures can be used to accelerate said models. Hardware solutions based on content addressable memory arrays will also be discussed. We then consider machine learning models for recommendation systems. Recommendation models, an emerging class of machine learning models, employ distinct neural network architectures that operate of continuous and categorical input features which make hardware acceleration challenging. We will discuss the open research challenges and opportunities within this space.

Specialized hardware for deep learning using analog memory devices has the potential to outperform conventional GPUs by a large margin. At the core of such hardware are arrays of non-volatile-memory (NVM) devices that can perform the simple matrix operations needed for deep learning in parallel and in constant time. Several implementations can be found in the literature that use different materials as memory elements, including phase-change-memory (PCM), resistive-random-access-memory (RRAM), electrochemical-random-access-memory (ECRAM), and ferroelectric devices. While the current focus is to demonstrate functionality, there is an increasing concern about the reliability margins of this emerging technology. In this paper we will briefly describe operation and device requirements, and then focus on possible reliability exposure in terms of variability, stability and drift, retention and durability.

We report InGaAs gate-all-around nanosheet NFETs on Si substrate using template-assisted-selective-epitaxy (TASE) and a gate-last process with thermal budget advantages. Compared to our early report of the TASE process, in this paper we demonstrate that TASE can be scaled to a channel thickness of ∼10 nm, which enables short gate devices without significant leakage. The defects and composition of the fabricated nanosheet FETs are also investigated. Enabled by this VLSI compatible process and a novel high-pressure deuterium annealing process, our 39 nm- $L_{g}$ device shows a peak $g_{m}$ of $1.37 \ \text{mS}/\mu \mathrm{m}$ , a subthreshold slope in saturation of 72 mV/decade, and an $I_{on}$ of $355 \ \mu \mathrm{A}/\mu \mathrm{m}$ at 0.5 V $V_{gs}$ , the highest among reported sub-50 nm- $L_{g}$ III-V FETs on Si.

Crystalline phase identification for hafnium-based ferroelectrics by diffraction techniques has been elusive. We use density-functional-theory (DFT)-assisted extended X-ray absorption fine-structure spectroscopy (EXAFS) to determine the crystal symmetry of thin hafnium zirconium oxide (Hf0.46Zr0.54O2) films grown by atomic layer deposition. Ferroelectric switching in TiN/Hf0.46Zr0.54O2/TiN metal–insulator–metal capacitors is verified. Grazing-incidence fluorescence-yield mode Hf L3 and Zr K absorption edge EXAFS data are compared with reference data calculated from DFT-based atomic coordinates for various structural phases of Hf0.5Zr0.5O2. Via EXAFS multiphase fitting, we confirm that the frequently invoked polar orthorhombic Pca21 phase is present in ferroelectric hafnium zirconium oxide, along with an equal amount of the nonpolar monoclinic P21/c phase. For comparison, we verify that paraelectric HfO2 films exhibit the P21/c phase.

We demonstrate a thermally stable titanium silicide/titanium nitride (TiSi x /TiN) full metal gate (FMG) for dual-channel gate-first high- $k$ /metal gate complementary metal–oxide–semiconductor technology. Unlike prior tungsten-based FMG, the simple TiSi x /TiN gate electrode does not require any additional barrier layer preventing oxygen down-diffusion during high-temperature processing, as the TiSi x itself blocks oxygen. With HfO2-based gate dielectrics and without any oxygen scavenging scheme, we thus demonstrate a capacitance-equivalent thickness in inversion ( $T_{\mathrm {inv}})$ of 1.11 nm, corresponding to an equivalent oxide thickness of $\sim 0.7$ nm. Silicon channel nFET and silicon germanium channel pFET parametrics are similar to those of control devices utilizing a conventional a-Si/TiN metal-inserted poly-Si stack (MIPS) gate, while providing superior gate sheet resistance. By supplanting MIPS with such an FMG, we anticipate that contacted gate pitch can be scaled aggressively via reduced gate height and borderless source/drain contacts.

Using devices with well passivated interfaces and reduced electron trapping, it is demonstrated that significant interface-state generation occurs during PBTI stress in InGaAs MOS capacitors with Al 2 O 3 /HfO 2 /TiN gate stacks. These observations on capacitors imply that the impact of interface-state generation on mobility and subthreshold-degradation need to be monitored in III-V nFET in addition to electron trapping in the gate stack.

Ultrascaled transistors based on single-walled carbon nanotubes are identified as one of the top candidates for future microprocessor chips as they provide significantly better device performance and scaling properties than conventional silicon technologies. From the perspective of the chip performance, the device variability is as important as the device performance for practical applications. This paper presents a systematic investigation on the origins and characteristics of the threshold voltage (VT) variability of scaled quasiballistic nanotube transistors. Analysis of experimental results from variable-temperature measurement as well as gate oxide thickness scaling studies shows that the random variation from fixed charges present on the oxide surface close to nanotubes dominates the VT variability of nanotube transistors. The VT variability of single-tube transistors has a figure of merit that is quantitatively comparable with that of current silicon devices; and it could be reduced with the adoption of improved device passivation schemes, which might be necessary for practical devices incorporating multiple nanotubes, whose area normalized VT variability becomes worse due to the synergic effects from the limited surface coverage of nanotubes and the nonlinearity of the device off-state leakage current, as predicted by the Monte Carlo simulation.

We demonstrate self-aligned fully-depleted 20-nm-thick In 0.53 Ga 0.47 As-channel MOSFETs using CMOS-compatible device structures and manufacturable process flows. These devices consist of self-aligned source/drain extensions and self-aligned raised source/drain with low sheet resistance of 360 and 115 Ω/sq, respectively. We demonstrate short-channel MOSFETs with gate lengths L G down to 30 nm, low series resistance R EXT = 375 Ω·μm, and high peak saturation transconductance G MSAT = 1275 μS/μm at L G = 50 nm and drain bias V DS = 0.5 V. We obtain long-channel capacitive inversion thickness TINV = 2.3 nm and effective mobility μ EFF = 650 cm 2 /Vs at sheet carrier density N S = 5 × 10 12 cm -2 . Finally, using a calibrated quasi-ballistic FET model, we argue that for L G ≤ 20 nm, μ EFF ≈ 1000 cm 2 /Vs will lead to short-channel MOSFETs operating within 10% of the ballistic limit. Thus, our III-V processes and device structures are well-suited for future generations of high-performance CMOS applications at short gate lengths and tight gate pitches.

High-k gate dielectrics such as HfO2 and metal gate electrodes such as TiN have been deployed across a wide range of CMOS logic products in both the low-power (e.g., mobile) and the high-performance (e.g., server) space. Available device geometries include planar field-effect transistors on bulk Si, on partially depleted silicon-on-insulator (PDSOI), and on fully depleted SOI (FDSOI), as well as FinFETs. During the decade-long effort leading up to successful high-k/metal gate (HKMG) implementation, much has been learnt about the fundamental materials science underlying such gate stacks. Yet, research continues in order to ensure continued circuit density and performance scaling. After reviewing the gate-first and gate-last (or replacement gate) approaches to HKMG implementation, I will discuss device challenges that can be resolved by materials engineering on the atomic scale. A prime example is the threshold voltage (Vt) challenge, which is caused by charged oxygen vacancies in hafnium-based gate dielectrics formed at elevated temperatures, thus increasing pFET Vt. These vacancies can be filled by lateral or top-down oxidation. As an alternative, additional Vt-setting techniques can be employed, such as metal oxide capping layers (e.g., Al2O3 or La2O3 for pFET and nFET, respectively) that form permanent electrical dipoles, or SiGe channels (cSiGe) which modulate the band offsets while additionally providing a welcome hole mobility boost. A second example is continued equivalent oxide thickness (EOT) scaling. We have developed the approach of metal-gate-induced remote oxygen scavenging, which results in a thinning of the SiO2 layer at the high-k/channel interface. In this way, EOT of 0.4-0.5 nm can be reached for both nFET and pFET. I will in particular discuss our recent results on aggressive cSiGe pFET scaling (Fig. 1), including the dependence of hole mobility (Fig. 2) and of negative bias temperature instability (NBTI) reliability on EOT and thus on interfacial SiO2thickness [1]. In the second part of my talk, I will show that HKMG not only provides the well-known gate-length scaling benefit through improved electrostatics, but it can also directly enable aggressive device pitch and density scaling through borderless (semi-self-aligned) source-drain (S/D) contacts [2]. Conventional gate-first high-k/metal gate (HKMG) CMOS technologies employ metal-inserted poly-Si stacks (MIPS) such as a-Si/TiN, where the amorphous Si serves as a precursor for low-sheet-resistance (Rs) self-aligned NiSi on the gates and as an oxygen barrier preventing high-k/Si interfacial SiO2 growth. A full metal gate (FMG, Fig. 3), instead containing a deposited low-Rs metal layer, can be encapsulated in a dielectric resistant to the S/D contact etch, resulting in borderless contacts. We have developed two FMG electrodes based on TiSix/TiN and W/TaMN/TiN (M = oxygen scavenging metal). With both FMG on Hf-based gate dielectrics, Si channel nFET and SiGe channel pFET parametrics and reliability similar to those of poly-Si/TiN control devices are achieved, with good EOT scalability [3,4]. Finally, I will provide an outlook on high-k gate dielectrics for high-mobility III-V channel materials. Specifically, I will compare three interface approaches to InGaAs channel nFET gate stack formation. The first is based on direct high-k deposition onto InGaAs, while the other two approaches rely on the insertion of an amorphous Si or an epitaxial InP capping layer to passivate the InGaAs. The impact of such caps on interface trap density and scalability will be discussed. [1] M.M. Frank et al., ECS Solid State Lett. 2, N8 (2013). [2] S.-C. Seo, et al., VLSI, p. 36 (2011). [3] M. M. Frank et al., as discussed at SISC 2011. [4] M. M. Frank et al., as discussed at SISC 2013. .

Epitaxial growth of SrTiO₃ on silicon by molecular beam epitaxy has opened up the route to the integration of functional complex oxides on a silicon platform. Chief among them is ferroelectric functionality using perovskite oxides such as BaTiO₃. However, it has remained a challenge to achieve ferroelectricity in epitaxial BaTiO₃ films with a polarization pointing perpendicular to the silicon substrate without a conducting bottom electrode. Here, we demonstrate ferroelectricity in such stacks. Synchrotron X-ray diffraction and high-resolution scanning transmission electron microscopy reveal the presence of crystalline domains with the long axis of the tetragonal structure oriented perpendicular to the substrate. Using piezoforce microscopy, polar domains can be written and read and are reversibly switched with a phase change of 180°. Open, saturated hysteresis loops are recorded. Thus, ferroelectric switching of 8- to 40-nm-thick BaTiO₃ films in metal-ferroelectric-semiconductor structures is realized, and field-effect devices using this epitaxial oxide stack can be envisaged.

Traditionally, the reliability of gate oxides is mostly evaluated using a Constant Voltage Stress, CVS, based stress-and-sense methodology, in which a constant stress voltage is interrupted to quantify the degradation. In this paper, we discuss the use of a Voltage-Ramp Stress, VRS, based stress-and-sense method in which the stress voltage is ramped at a constant rate and degradation is quantified by interrupting the VRS at increasingly higher stress voltages. The two methods are used and compared for dielectric breakdown and bias temperature instability measurements using high-k/metal gate stacks. It is shown that the two methods can be used interchangeably, producing very similar reliability assessments. It is shown that the VRS method, however, has distinct advantages over a CVS approach. It is fast and 'foolproof', providing reliable information on the voltage acceleration without any prior knowledge on the dynamics of the degradation. The use of a VRS is therefore well suited for monitoring reliability parameters during gate stack and process development, and during device optimization, where large variations in the reliability parameters are common.

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO"2 formation and silicidation and equivalent oxide thickness (EOT) of 5A is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO"2-SiO"2 intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6A with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.

We demonstrate a novel remote interfacial layer (IL) scavenging technique yielding a record-setting equivalent oxide thickness (EOT) of 0.42 nm using a HfO2-based high-k gate dielectric. The remote IL scavenging shows advantages in carrier mobility and gate leakage current over conventional IL scaling schemes. Moreover, this method enables intrinsic EOT scaling without introducing additional charges and interface degradation. It is shown that the mobility degradation observed for a La-containing high-k is not due to the La-induced dipole but due to the intrinsic IL scaling effect, whereas an Al-induced dipole brings about additional mobility degradation. This unique nature of the La-induced dipole in conjunction with the IL scaling enables aggressive EOT scaling toward the end of the road map.

We discuss options for metal-oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity ('high-k') gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO"2 can be scaled to capacitance equivalent thickness in inversion (T"i"n"v) of 10A and equivalent oxide thickness (EOT) of 6A by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si"3N"4 and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based 'higher-k' dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO"2 as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO"2 at the poly-Si contact. We further address the performance of Si"3N"4 and HfO"2 as oxygen barrier layers.

Wet processes are gaining renewed interest for the removal of post-etch photoresist on porous dielectrics in semiconductor manufacturing. However, specifications on material loss and k-value integrity considerably reduce formulation space for a purely wet-chemical clean. Hence characterization of photoresist degradation by etch is needed to support the selection of wet cleaning chemistries. In this work, the degradation of a DUV (deep ultra-violet) photoresist by a dielectric etch plasma is characterized by spectroscopic as well as by polymer science characterization techniques. Results show that degradation of the DUV photoresist under study does not follow the mechanisms previously proposed for etched DUV photoresist films, but is rather comparable to the degradation of PMMA under low energy radiation. Degradation is more intense in the photoresist top layer, forming a cross-linked crust that is insoluble in organic solvents. Based on FTIR and H-1 NMR analysis of isolated crust samples, a cross-linking mechanism is proposed that is based on the reaction between intra-chain radicals and/or between intra-chain radicals and end-chain propagating radicals. Implications for the wet removal of photoresist layers are discussed. (C) 2008 Elsevier B.V. All rights reserved.

We review the impact of oxide-semiconductor interface chemistry and precursor choice on the quality of novel field-effect transistor gate dielectrics grown by atomic layer deposition (ALD). Focus is on hafnium- and aluminum-based high-permittivity ('high-k') gate dielectrics on silicon and on high carrier mobility (germanium, gallium arsenide) channels. We shed light on the ways processing parameters (choice of materials; surface preparation; high-k dielectric deposition process) determine stack structure (continuity of the high-k layer; interfacial oxide thickness; detrimental channel-dielectric interactions) and hence electrical quality. Trends are rationalized based on thermodynamic properties of the semiconductors, dielectrics, and metal-organic precursors involved. This may serve as a basic guideline for ALD precursor selection.

A combination of wet chemistry and high-velocity solid CO2 aerosol pre-treatment was used to remove ion-implanted resist from patterned Si structures. The top resist surface is modified by heavy ion-implantation forming a crust ~100nm thick. The aerosol treatment, which is aimed at breaking and partially removing the crusted top layer of implanted resist, produces circular openings in this surface, with diameters on the order of tens to hundreds of micrometers. No resist is detected by either optical microscopy or localized SEM inspection, after immersion in hot SPM mixture, on aerosol-pre-treated wafer fragments. In contrast, resist residue is still observed on similarly pre-treated specimens, after immersion in either N-methyl pyrrolidone or Microstrip2001{trade mark, serif}, even under ultrasonic agitation. Overall, the aerosol pre-treatment is a key step in reducing the amount of resist residue, for both aqueous-based and solvent-based wet cleaning. Full-wafer defect-count results, post aerosol treatment, are reported for poly-Si line widths down to 40 nm.

The performance of aggressively scaled (1.4nm

The paper reviews our recent progress and current challenges in implementing advanced gate stacks composed of high-κ dielectric materials and metal gates in mainstream Si CMOS technology. In particular, we address stacks of doped polySi gate electrodes on ultrathin layers of high-κ dielectrics, dual-workfunction metal-gate technology, and fully silicided gates. Materials and device characterization, processing, and integration issues are discussed.

This paper reviews progress and current critical issues with respect to the integration of germanium (Ge) surface-channel MOSFET devices as well as strained-Ge buried-channel MOSFET structures. The device design and scalability of strained-Ge buried-channel MOSFETs are discussed on the basis of our recent results. CMOS-compatible integration approaches of Ge channel devices are presented.

We demonstrate high-performance self-aligned In 0.53 Ga 0.47 As-channel MOSFETs with effective channel length L EFF down to 20 nm, peak transconductance G MSAT over 2200 µS/µm at L EFF = 30 nm and supply voltage V DD = 0.5 V, thin inversion oxide thickness T INV = 1.8 nm, and low series resistance R EXT = 270 Ω.µm. These MOSFETs operate within 20% of the ballistic limit for L EFF ≤ 30 nm and are among the best In 0.53 Ga 0.47 As FETs in literature. We investigate the effects of channel/barrier doping on FET performance and show that increase in mobility beyond ∼ 500 cm2/Vs has progressively smaller impact as L EFF is scaled down. Our self-aligned MOSFETs were fabricated using a CMOS-compatible process flow that includes gate and spacer formation using RIE, source/drain extension (SDE) implantation, and in-situ-doped raised source/drain (RSD) epitaxy. This process flow is manufacturable and easily extendable to non-planar architectures.

To identify the nature and the local structure of the surface of supported catalyst nanoparticles, we have performed a detailed comparative study of CO adsorption on two categories of oxide-supported Palladium catalysts: (1) polycrystalline MgO and γ-Al2O3 supported Pd metal catalysts prepared by impregnation techniques and characterized by different degrees of regularity and perfection and (2) single-crystal based Pd model catalysts prepared under ultrahigh vacuum (UHV) conditions. The assignment of the CO vibrational frequencies to different types of sites on these systems has allowed a detailed structural characterization. For the Pd model catalyst, at low CO coverage, the infrared (IR) reflection absorption spectra closely resemble the expected behavior for terminations by a majority of (111) facets and a minority of (100) facets. The spectral features are indicative of defect sites such as particle steps and edges. Occupation of the defect sites can be affected by surface contaminations such as atom...

Alumina-supported Pd model catalysts were prepared by Pd evaporation onto a thin alumina film grown on a NiAl(110) substrate. Adsorption and co-adsorption of ethene, CO and hydrogen on Pd/Al2O3/NiAl(110) covered by carbon species, formed by ethene dehydrogenation at ∼550 K, was studied by temperature programmed desorption (TPD). TPD results show that carbon deposits do not prevent adsorption but inhibit dehydrogenation of di-σ bonded ethene. Carbon species suppress CO adsorption in the highly coordinated sites and also suppress the formation of hydrogen ad-atoms on the surface. The ethene hydrogenation reaction performed by co-adsorption of hydrogen and ethene is inhibited by the presence of carbon deposits. The inhibition is independent of particle size studied (1-3 nm). The effects are rationalized in terms of a site-blocking behavior of carbon species occupying highly coordinated sites on the Pd surface.

International audience; It has recently been suggested that ferroelectric (FE) negative capacitance effects can be used to achieve steep subthreshold slope field-effect transistors, which are greatly desired for reducing energy consumption in modern digital electronics. Here, we propose that this concept can be improved by the introduction of a very thin metal or metal-like layer (a quantum metal) between the FE and the semiconductor channel. We show how to design this layer so that it attenuates the polarization charge of the FE, applying an appropriate charge to the semiconductor, while at the same time presenting a relatively constant capacitance to the FE layer, as is needed to stabilize the negative capacitance regime. For homogeneous polarization, we estimate that this device (a QMFeFET) can have extremely steep subthreshold characteristics (2 mV/decade over 11 decades) and that its energy and delay performance are advantageous.

Supported metal particles may exhibit properties fundamentally different from the corresponding bulk materials.To gain insight into principles underlying size- and structure-dependent phenomena, a structural characterizationof small aggregates at the atomic level is crucial, while far from straightforward. A long-standing questionin the study of supported clusters and metal-oxide interfaces concerns the extent of metal-oxide charge transfer.We show that infrared spectroscopy, utilizing carbon monoxide as a probe molecule, may provide valuableinformation on both structure and charge of ultrasmall metal aggregates and single metal atoms. To createsupported particles containing only few atoms or even a single atom, submonolayer amounts of the transitionmetals palladium, rhodium, and iridium were vapor-deposited onto a thin, well-ordered alumina film at lowsubstrate temperatures. Scanning tunneling microscopy served to characterize nucleation behavior and averageparticle size. Sharp, discrete features in the infrared spectra of adsorbed CO are due to uniform metal (M)carbonyls, most notably the mono- and dicarbonyl species MCO and M(CO)

Schottky source/drain (S/D) MOSFETs hold the promise for low series resistance and extremely abrupt junctions, providing a path for device scaling in conjunction with a low Schottky barrier height (SBH). A S/D junction SBH approaching zero is also needed to achieve a competitive current drive. In this letter, we demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal (500°C-600°C). These devices have high-κ/metal gate and fully depleted extremely thin SOI with sub-30-nm gate length.

We demonstrate self-aligned fully-depleted III-V MOSFETs using CMOS-compatible device structures and manufacturable process flows. Processes with good manufacturability and scalability, such as, gate definition and spacer formation using RIE, and formation of self-aligned source/drain extensions (SDE) and self-aligned raised source/drain (RSD), have been established on III-Vs. We demonstrate short-channel devices down to gate length LG = 30 nm. Our best short-channel devices exhibit peak saturation transconductance GMSAT = 1140 μS/μm at LG = 60 nm and supply voltage VDD = 0.5 V.

We have studied the growth of various metals (Pd, Rh, Co and Ir) on a thin well-ordered alumina film in order to elucidate the influence of film structure and deposition conditions on nucleation and growth behaviour. All metals exhibit a three-dimensional growth mode in agreement with thermodynamic considerations. The nucleation is, however, dominated by the defects of the substrate. At a deposition temperature of 90 K, point defects are the primary nucleation centres. At 300 K, the situation is different for some metals (such as Pd and Rh) since decoration of steps and film domain boundaries is favoured under these conditions. This temperature dependence points to a stronger interaction of the diffusing metal atoms with the line defects which, however, can only play a role if the thermal energy is sufficiently high to reach them. Metals which are expected to interact more strongly with the support (such as Ir and Co) do not show such a diversity with respect to their nucleation behaviour.

Ultra-small rhodium, palladium and iridium particles with minimum average sizes of five atoms have been grown on a thin, well-ordered alumina film at temperatures of 90 K and below. Scanning tunneling microscopy (STM ) served to characterize the morphology of these deposits. In the infrared spectra of adsorbed carbon monoxide, characteristic features were observed by infrared reflection absorption spectroscopy (IRAS). These originate from CO adsorbed on single metal atoms and extremely small aggregates, most likely dimers or trimers. In this way, we have detected the atomic nuclei of heterogeneous rhodium nucleation at 90 K. Located at oxide point defects, these atoms form rhodium dicarbonyl species with a symmetric stretch frequency of 2117 cm’1, while for iridium dicarbonyl species a frequency of 2107 cm’1 was found. At 60 K, rhodium aggregates also grow elsewhere on the oxide film. Comparing the nucleation behaviour at low temperatures, we find an increasing metal‐oxide interaction strength in the order Pd

The properties of metal clusters and nanoparticles are attracting more and more attention in fundamental and applied research. The application of such structures in heterogeneous catalysis is a particularly important area. Nevertheless, there is only limited fundamental knowledge about the dependence of adsorption behaviour and catalytic activity on particle size. In this article, we describe an approach to tackle such questions on the basis of model systems which are prepared by metal vapour deposition under ultrahigh vacuum conditions. A thin alumina film grown on a metal substrate is used as support. This has the advantage that scanning tunneling microscopy and photoelectron spectroscopy can be applied without any charging problems. Firstly, structural data covering palladium, rhodium and iridium deposits demonstrate that a wide spectrum of particle sizes and morphologies may be obtained by taking advantage of kinetically controlled nucleation and growth processes. Subsequently, we discuss the adsorption of simple molecules on the particles, such as CO and ethene. These studies, which have been carried out using infrared and photoemission spectroscopy, illustrate possible variations in the adsorption and reaction behaviour as a function of particle size. Aspects which will be considered include: adsorption at facets and defects, size-dependent variation of adsorption sites, formation of surface complexes, decomposition of molecules as well as co-adsorption phenomena.