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There is a scarcity of long-term groundwater hydrographs from sub-Saharan Africa to investigate groundwater sustainability, processes and controls. This paper presents an analysis of 21 hydrographs from semi-arid South Africa. Hydrographs from 1980 to 2000 were converted to standardised groundwater level indices and rationalised into four types (C1–C4) using hierarchical cluster analysis. Mean hydrographs for each type were cross-correlated with standardised precipitation and streamflow indices. Relationships with the El Niño–Southern Oscillation (ENSO) were also investigated. The four hydrograph types show a transition of autocorrelation over increasing timescales and increasingly subdued responses to rainfall. Type C1 strongly relates to rainfall, responding in most years, whereas C4 notably responds to only a single extreme event in 2000 and has limited relationship with rainfall. Types C2, C3 and C4 have stronger statistical relationships with standardised streamflow than standardised rainfall. C3 and C4 changes are significantly (p

We present (i) a novel, thermally stable Atomic Layer Deposition (ALD) high-k dielectric stack that, for the first time, has the potential to meet all gate stack requirements for both n- and p-channel Ge FETs, (ii) record low contact resistivity for n-Ge/metal contacts using an implant-free contact scheme with successful implementation into a single nanowire (NW) Ge nFET baseline, (iii) single NW Ge pFETs with short-channel effect (SCE) immunity down to 24 nm physical gate length, of which electrical data show excellent agreement with calibrated models and (iv) demonstration of Ge-channel vertically stacked lateral NW FETs using a 300 mm VLSI compatible platform.

We report the first demonstration of InAs FinFETs with fin width $\textrm {W}_{{\mathrm{fin}}}$ in the range 25–35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height $\textrm {H}_{{\mathrm{fin}}}=20$ nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length $\textrm {L}_{{{\textrm {g}}}}=1~\mu \text{m}$ , peak transconductance $\textrm {g}_{{{\textrm {m},{\mathrm{ peak}}}}}=1430~\mu \text{S}/\mu \text{m}$ is measured at $\textrm {V}_{{\textrm {d}}}=0.5$ V demonstrating that electron transport in InAs fins can match planar devices.

We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high- $\kappa $ dielectric engineering improves the device performance; with an optimized gate stack having an EOT of 1.0 nm, the sub-threshold swing ${S}$ is 76.8 mV/dec., and the peak transconductance ${g} _{\mathrm{ m}}$ is 1.65 mS/ ${\mu }\text{m}$ , at ${V} _{\mathrm{ ds}}$ of 0.5 V, for a gate-all-around nanowire MOSFET having a gate length ${L} _{\mathrm{ g}}$ of 90 nm, a nanowire height ${H} _{\mathrm{ NW}}$ of 25 nm, and a nanowire width ${W} _{\mathrm{ NW}}$ of 20 nm, resulting in ${Q}~\equiv ~{g} _{\mathrm{ m}}/{S} \,\, = \,\, 21.5$ , a record for InAs on silicon. Furthermore, we report a source/drain resistance ${R} _{\mathrm{ sd}}$ of 160– $200~\Omega \cdot {\mu }\text{m}$ , amongst the lowest values reported for III-V MOSFETs. Our VLSI-compatible process provides high device yield, which enables statistically reliable extraction of electron transport parameters, such as unidirectional thermal velocity ${v} _{\mathrm{ tx}}$ of 3– $4\times 10^{7}$ cm/s and back-scattering coefficient ${r} _{\mathrm{ c}}$ as a function of gate length.

Al x In 1− x As y Sb 1− y quaternary alloys lattice-matched to InAs were successfully grown by molecular beam epitaxy (MBE) for use as buffer layers for substrate isolation in InAs channel devices. The use of In-containing quaternary buffer layers with 5% In was found to dramatically improve the heterointerface between the buffer and a surface InAs channel layer. The composition of these alloys and the extent of lattice matching were accurately determined by double crystal X-ray measurements. A simple model was used to estimate the variation of critical thickness with lattice mismatch for AlInAsSb epitaxially grown on an InAs substrate. Layers with high Al content and low As mole fraction were grown by modulated MBE technique which was found to significantly improve the surface morphology and the composition control of the alloys. In contrast, quaternary alloys with low Al content were grown by conventional MBE and had an rms roughness of less than 0.2 nm.

Frequency (100 ${\rm Hz}\le f \le 1$ MHz) and temperature ( $- 50 \le T \le 20^{\circ }\text{C}$ ) characteristics of low interface state density $D_{\rm {it}}$ high- $\kappa $ gate-stacks on n-InAs have been investigated. Capacitance–voltage ( $C$ – $V$ ) curves exhibit typical accumulation/depletion/inversion behavior with midgap $D_{\rm {it}}$ of $2\times 10^{11}$ and $4\times 10^{11}$ cm $^{-2}$ eV $^{-1}$ at −50 °C and 20 °C, respectively. Asymmetry of low-frequency s $C$ – $V$ curves and $C$ – $T$ dependence for negative voltage showing a sharp transition of $\cong -20$ dB/decade between low- and high-frequency behavior indicate surface inversion. An inversion carrier activation energy and an InAs hole lifetime of 0.32 eV and 2 ns have been extracted, respectively. Surface channel nMOSFETs with gate length $L_{g} =$ 1 $\mu \text{m}$ , channel thickness = 10 nm, and equivalent oxide thickness (EOT) $1 \le {\rm EOT} \le 1.6$ nm have been fabricated. For ${\rm EOT} = 1$ nm, a subthreshold swing $S = 65$ mV/decade, transconductance $g_{m} =1.6$ mS/ $\mu \text{m}$ , and ON-current $I_{{\mathrm{{\scriptscriptstyle ON}}}} =$ 426 $\mu \text{A}/\mu \text{m}$ at an OFF-current $I_{{\mathrm{{\scriptscriptstyle OFF}}}} =100$ nA/ $\mu \text{m}$ (supply voltage $V_{\rm {dd}} =$ 0.5 V) have been measured. Peak electron field-effect mobilities of 6000–7000 cm $^{2}$ /Vs at sheet electron densities of 2– $3\times 10^{12}$ cm $^{-2}$ were obtained for EOT as small as 1 nm.

The integration of III-V semiconductors on silicon (Si) substrate has been an active field of research for more than 30 years. Various approaches have been investigated, including growth of buffer layers to accommodate the lattice mismatch between the Si substrate and the III-V layer, Si- or Ge-on-insulator, epitaxial transfer methods, epitaxial lateral overgrowth, aspect-ratio-trapping techniques, and interfacial misfit array formation. However, manufacturing standards have not been met and significant levels of remaining defectivity, high cost, and complex integration schemes have hampered large scale commercial impact. Here we report on low cost, relaxed, atomically smooth, and surface undulation free lattice mismatched III-V epitaxial films grown in wide-fields of micrometer size on 300 mm Si(100) and (111) substrates. The crystallographic quality of the epitaxial film beyond a few atomic layers from the Si substrate is accomplished by formation of an interfacial misfit array. This development may enable future platforms of integrated low-power logic, power amplifiers, voltage controllers, and optoelectronics components.

The growth of heterostructures lattice matched to InAs(100) substrates for high mobility electronic devices has been investigated. The oxide removal process and homoepitaxial nucleation depends on the deposition parameters to avoid the formation of surface defects that can propagate through the structure during growth which can result in degraded device performance. The growth parameters for InAs homoepitaxy were found to be within an extremely narrow range when using As 4 with a slight increase using As 2 . High structural quality lattice matched AlAs x Sb 1− x buffer layer was grown on InAs(100) substrates using a digital growth technique with the AlAs mole fraction adjusted by varying the incident As flux. Using the AlAs x Sb 1− x buffer layer, the transport properties of thin InAs channel layers were determined on conducting native substrates.

We demonstrate MOVPE-growth of InAs/AlAs0.16Sb0.84/GaSb and InAs/AlAs0.16Sb0.84/InAs heterostructures of excellent quality as observed by transmission electron microscopy and x-ray diffraction 2-theta-omega and rocking curve scans with full width at half maximum routinely below 100 arcsec. Key points regarding interface control for heteroepitaxial nucleation are reviewed and the choice of suitable precursors to minimize the incorporation of C and O are discussed.

We present detailed design, fabrication and characterization of In 0.23 Ga 0.77 As-based planar Gunn diodes in this paper. The devices have AlGaAs/InGaAs/AlGaAs heterojunctions that were grown on a semi-insulating GaAs wafer using molecular beam epitaxy technology. Electron beam lithography was used to define anode and cathode terminal patterns. Devices with various anode–cathode separations (e.g. 4–1.4 μm) were fabricated on the same chip. Spectrum measurements showed oscillation frequencies between 36 GHz and 118 GHz in the fundamental transit-time mode of operation. These devices show great potential as millimeter wave and sub-millimeter wave signal sources for their small size, MMIC compatibility and lithographically controlled oscillation frequencies.

Electrical interface quality of various high- k dielectrics on GaSb, including Al2O3, HfO2, LaAlO3, GdScO3, and HfO2/Ga2O3 bilayer has been studied and compared with reference low (AlGaSb) and high Dit (native oxide) interfaces using photoluminescence intensity measurements for the first time. Al2O3 and HfO2/Ga2O3 bilayer dielectrics are identified with the lowest interface recombination velocity (S=7×104 cm/s) and consequently Dit integrated across essentially the entire bandgap. However, S for even the best identified high- k dielectrics is elevated by 140× over the low Dit AlGaSb reference indicating the need of further improvements for envisioned use in Sb based MOSFETs.

Kelvin probe force microscopy (KPFM) is a unique technique that can provide two dimensional potential profiles inside a working device. A procedure is described to obtain high-resolution KPFM results on ultra-high vacuum (UHV) cleaved III-V MOSCAPs. Two tip preparation methods: field emission and Cr coating show reproducible high spatial and energy resolution KPFM images. A unique sample design has been developed which is compatible with UHV cross-sectional KPFM (x-KPFM). Key design features are high density of devices on the cleave face, a buried device interface, and a cleavable gate contact. Using x-KPFM, the first UHV cleaved MOSCAP surface potential mapping is demonstrated.

To address issues associated with continual scaling of the International Technology Roadmap for Semiconductors (ITRS) (1) to follow Moore's Law, MOSFETs with high mobility channel materials are now being seriously considered. As a result, there has been a significant expansion in research into III-V MOSFETs as a potential n-channel device solution. A wide range of high electron mobility channel materials, device architectures and gate oxides are currently being considered, and in this review, key performance metrics of III-V MOSFETs will be compared.

In this paper a quantitative determination of the elemental distributions across a ~10nm Ga"2O"3/GdGaO layer with a Pt metal gate cap on top of an InGaAs/AlGaAs/GaAs substrate is presented. Some effects of annealing on the elemental distribution across the Ga"2O"3/GdGaO oxide layer are described. The paper also discusses the analysis of the interface GaAs/Ga"2O"3/GGO at a sub-nm level by high-resolution HAADF STEM imaging.

Ga"2O"3/GdGaO dielectric stacks have been grown on GaAs for MOSFETs. This paper highlights variations in the characteristics of GdGaO as the Gd flux, Ga"2O flux and substrate temperature are changed. The growth rate, composition, crystallinity are discussed and the sheet resistance of final MOSFET structures are presented. The Gd compositional variation with depth is examined using Rutherford back scattering (RBS) and electron energy loss spectroscopy (EELS).

The ability to control spins in semiconductors is important in a variety of fields including spintronics and quantum information processing. Due to the potentially fast dephasing times of spins in the solid state [1-3], spin control operating on the picosecond or faster timescale may be necessary. Such speeds, which are not possible to attain with standard electron spin resonance (ESR) techniques based on microwave sources, can be attained with broadband optical pulses. One promising ultrafast technique utilizes single broadband pulses detuned from resonance in a three-level Lambda system [4]. This attractive technique is robust against optical pulse imperfections and does not require a fixed optical reference phase. Here we demonstrate the principle of coherent manipulation of spins theoretically and experimentally. Using this technique, donor-bound electron spin rotations with single-pulse areas exceeding pi/4 and two-pulses areas exceeding pi/2 are demonstrated. We believe the maximum pulse areas attained do not reflect a fundamental limit of the technique and larger pulse areas could be achieved in other material systems. This technique has applications from basic solid-state ESR spectroscopy to arbitrary single-qubit rotations [4, 5] and bang-bang control[6] for quantum computation., 15 pages, 4 figures, submitted 12/2008. Since the submission of this work we have become aware of related work: J. Berezovsky, M. H. Mikkelsen, N. G. Stoltz, L. A. Coldren, and D. D. Awschalom, Science 320: 349-352 (2008)

This paper reviews some of the recent work at the Nanoelectronics Research Centre at the University of Glasgow on the optimisation of 50 nm metamorphic GaAs and InP HEMTs. Typical DC and RF figures of merit obtained from 50 nm metamorphic GaAs HEMTs include I dss of 800 mA/mm, g m of 1100 mS/mm, threshold voltage standard deviation of 5 mV across a 25 mm × 25 mm area, f T of 440 GHz and f max of 400 GHz, all at a drain bias of 1.0 V. To our knowledge, these are the highest operating frequency GaAs-based transistors to date. At V d = 0.8 V and V g = − 0.6 V, a NF min and G ass of 0.7 dB and 13 dB respectively at 26 GHz have been demonstrated. For similar geometry InP HEMTs, DC and RF figures of merit are the following: I dss of 900 mA/mm, g m of 1600 mS/mm, f T of 550 GHz, f max of 440 GHz, and NF min and G ass of 0.9 dB and 14 dB respectively at 26 GHz. The highest performance 50 nm HEMTs reported to date. Using these technologies, single stage MMMICs with gain of at least 7 dB and a return loss of better than − 5 dB across a 24 GHz bandwidth from 71 GHz to 95 GHz have been realised. Noise figure of 2.5 dB and associated gain of 7.3 dB at 90 GHz have been achieved with a DC power consumption of 20 mW.

This paper investigates reactive ion etching (RIE) of sputtered tungsten films, a suitable candidate for gate metallization in compound semiconductor based high mobility channel devices, with the aim of developing a detailed understanding of the effects of etching parameters vital to reducing etch-induced damage and improving etching performance, yield, uniformity and repeatability. An Oxford Instruments PlasmaLab System 100 RIE etch tool and SF"6 based chemistry in combination with various functional gases, such as N"2, O"2 and CHF"3 was used in this study. To evaluate plasma-induced damage caused by the RIE process, GaAs based HEMT (high electron mobility transistor) type layer structures with channels buried 18nm from the surface were grown by molecular beam epitaxy (MBE). Subsequently, Van der Pauw structures were fabricated on this material and used to assess the effects of the RIE process on sheet resistivity, carrier concentration and mobility in the device channel. Etched tungsten line widths down to 25nm were obtained by electron beam lithography with Sumitomo NEB31 resist as an etch mask. The effects of etching gases of SF"6+N"2, SF"6+O"2, and SF"6+CHF"3, RF power, and etching temperature on etching profile and etching-induced damage were investigated.

Measurements of the electron transport properties in Inx Ga1−xAs (x = 0.2 and x = 0.3) channel heterostructures have consistently shown the transport mobility to be higher in the [01&1macr;] direction compared to [011] on a (100) wafer. Low temperature (1.6 K) measurements of these materials show that the mobility difference can be as large as 30% whilst the differences in carrier concentrations for the two directions are negligible in comparison. The mobility anisotropy decreases to below 5% at room temperature as the effects of phonon scattering, which is isotropic, begin to dominate. The anisotropy in the quantum mobility is much less pronounced than that in the transport mobility. This suggests that the low mobility in the [011] direction is primarily a result of large angle scattering. Transmission electron microscopy (TEM) analysis was performed on cross-sections of material in the two directions. Thickness fluctuations in the channel were observed whilst traversing the channel of a (01&1macr;) section in the [011] direction where as none were observed in (011) sections along the [01&1macr;] direction. The length scale of the fluctuations was variable but typically around 50–100 nm. Transport simulations reveal that a 1-dimensional potential modulation with a wavelength similar to that of the fluctuations produces a mobility anisotropy with the observed sign. Therefore it is likely that the thickness variations, possibly combined with synchronous fluctuations in the indium concentration along the [011] direction, are responsible for the reduced mobility in [011] transport. Although to the best of our knowledge these thickness fluctuations are reported here for the first time, similar growth anisotropies are well known for Inx Ga1−xAs layers deposited on InP. (© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Whilst high performance p-channel Ge MOSFETs have been demonstrated [1–4], Ge n-channel MOSFET drive current has been lagging behind mainly hampered by high access resistance and poor gate stack passivation [5–9]. In this work, we address these issues on a module level and demonstrate Ge enhancement mode nMOS FinFETs fabricated on 300mm Si wafers implementing optimized gate stack (D it 1×1020 cm−3) and metallization (ρ c = 1×10−7 Ωcm2) modules. L G ∼ 40 nm devices achieved I on = 50 µA/µm at I off = 100 nA/um, S ∼ 124 mV/dec, at V DD = 0.5V. The same gate stack and contacts were deployed on planar devices for reference. Both FinFET and planar devices in this work achieved the highest reported g m /S sat at 0.5 V to date for Ge nMOS enhancement mode transistors to the best of our knowledge at shortest gate lengths.

A model that simulates the behaviour of group III atoms of various migration lengths is presented. The program operates under As rich conditions typical for MBE, so a group V atom will be placed immediately above a group III atom once that group III atom has bonded into the crystal. The model has no information about bond angles. Growth is controlled by the interaction of the group III atoms through their migration length and a requirement to migrate to a position to increase the number of their nearest neighbours.

Planar Gunn diodes operating above 100 GHz fabricated in GaAs/AlGaAs heterojunction structures with single and double δ-doping layers on each side of GaAs channel are numerically studied and experimentally demonstrated. The results show enhanced RF power and oscillation frequency when double δ-doping technique was used. By using a two-dimensional numerical simulation tool, the conduction band profile, electron concentration in the epitaxy layers and current-voltage characteristics are investigated. Simulation results indicate that extra δ-doping layers increase electron confinement in the conducting channel, therefore higher current levels are obtained. Simulated current-voltage characteristics in both cases agree well with experimental results. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26071

In this letter, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface and buried-channel In0.53Ga0.47As devices employing an atomic layer-deposited Al2O3 gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm2/V · s and 6600 cm2/V · s at a carrier density of 3 × 1012 cm-2 were determined for the surfaceand buried-channel structures, respectively. In contrast to similarly scaled inversion-channel devices, we find that the mobility in surface channel flatband structures does not drop rapidly with the electron density, but rather high mobility is maintained up to carrier concentrations around 4 × 1012 cm-2 before slowly dropping to around 2000 cm2/V · s at 1 × 1013 cm-2. We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for the future low-power highly scaled CMOS.

Fermi-edge singularities (FESs) have been found in the photoluminescence (PL) spectra of n-type doped GaAs quantum wires produced by strain-confinement. This is in contrast to the PL from the original heterojunction where no such features were observed. The FES dominates the spectrum of the quantum wires at low magnetic field. On increasing the magnetic field, the intensity of the FES falls sharply as the Fermi energy drops to the lowest one-dimensional subband. This behaviour of the FESs is in qualitative agreement with theory [Phys. Rev. B 49 (1994) 16781].

Contacts to planar Gunn devices on the semiconductor surface suffer from high electric field stress and current crowding leading to premature burn out. We have developed a new composite contact design using a Schottky extension of the conventional Ohmic contact. The composite contact structures have been fabricated and tested to mitigate the effects of high concentrations of charge and high electric fields at the anode edge of the planar Gunn diode. Monte Carlo simulations confirm these experimental results in composite contacts. These results suggest a mechanism of increased lifetime when using composite contacts as compared to conventional Ohmic contacts. This is of significant importance for planar Gunn device operation at millimetre wave and terahertz frequencies where high doping density (∼1017cm- 3) and short cathode to anode separation (1µm or less) is required. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

An ultra-low-power monolithic amplifier using 50-nm gate-length GaAs metamorphic high-electron-mobility transistor (MHEMT) has been designed and fabricated by a coplanar waveguide monolithic microwave integrated circuit process. A double (5-doped In0.52Al0.48As/In0.53Ga0.47As MHEMT technology with optimal doping profiles was used to achieve both ultra-low dc power consumption and good dynamic-range performance. The single-stage amplifier operates in the 24-GHz band and shows typical gain of 7.2 dB, ±0.5 dB bandwidth of 1.2 GHz, return losses better than 9 dB, and input IP3 (IIP3) of +3 dBm while consuming only 0.9 mW of dc power. These experimental results demonstrate the outstanding potential of MHEMT technology for ultra-low-power applications such as wireless sensor networks.

This paper investigates the reactive ion etching (RIE) of Ga"xGd"yO"z, a device quality [email protected] gate oxide for a low resistance ohmic contact realisation in fabricating III-V metal-oxide semiconductor field-effect-transistors (MOSFETs) based on high mobility channel device layer structures. The etching of Ga"xGd"yO"z (GGO) was performed in an Oxford Instrument PlasmaLab System 100 RIE etcher with a SiCl"4 based chemistry. The GGO [email protected] gate stacks for GaAs MOSFETs were grown by Molecular Beam Epitaxy (MBE) in a dual-chamber system. Etching profile was characterised by AFM, SEM and TEM methods. The effects of usual etching conditions, such as RF power and chamber pressure on etch process were investigated. Based on the etching process, a low resistance ohmic contact has been realised as well, which has successfully been used in the fabrication of GaAs MOSFETs.

Record setting III-V MOSFETs are reported. For the first time performance better than state-of-the-art HEMTs is demonstrated. For a MOSFET with 10 nm unstrained InAs surface channel and Lg = 130 nm operating at 0.5 V, on-current as high as Ion = 601 μA/μm (at fixed Ioff = 100 nA/μm) is achieved. This record performance is enabled by gm, ext = 2.72 mS/μm and S = 85 mV/dec, DIBL = 40 mV/V, resulting from breakthroughs in epitaxy and III-V/dielectric interface engineering. Measured mobility is 7100 cm2/V.s at ns = 6.7×1012 cm-2. Device simulations further elucidate the performance potential of III-V N-MOSFETs.

We demonstrate scaled, replacement gate high-k/metal gate p-channel Ge FinFETs integrated onto 300mm Si wafers for which the best device shows record peak gm, ext=2.7mS/μm (gm, int=3.3mS/μm), Q (≡gm, ext/SSsat) = 32.4 and Ion= 497μA/μm at Ioff = 100nA/μm, all at Vds= -0.5V. The high performance is a result of successful integration of oriented, highly scaled Ge fins on silicon substrates and of a low Dit gate stack with capacitance equivalent thickness=8Å. This optimized gate stack supports the highest hole mobility ever reported at sub-10Å CET. Furthermore, Ge FinFETs in the present work outperform any other reported Ge devices by more than ~2.5× (gm/SS metric) and ~2× (Ion/Ioff metric) at shortest gate lengths (down to 20nm) to the best of our knowledge.

In this paper, a subnanometer characterization of the Ga"2O"3/GdGaO dielectric gate stack grown on top of InGaAs lattice matched to n^+ InP substrate is presented. The paper shows the analysis of two samples grown using different substrate temperature. This clearly affects the electrical characteristics as well as the photoluminescence properties. The paper also describes how the growth conditions of oxide stack affect the elemental distribution across the interface region.

We have measured the magnitude of the potential modulation below gated one-dimensional lateral surface superlattices fabricated with periods between 60 and 600 nm on a range of GaAs/AlGaAs heterostructures. The magnitude of the modulation was obtained by studying the amplitude of the commensurability oscillations in magnetoresistance, and confirmed by analysis of the low field positive magnetoresistance step. Without gate bias applied, the modulation is generated by strain in the gates, coupled piezoelectrically to the two-dimensional electron gas. Both magnitude and harmonic content of the potential are in reasonable agreement with a recent theoretical calculation of this coupling, over the full range of periods and for all the structures studied. Away from zero gate bias electrostatic modulation adds to the piezoelectric component. This differs according to the sign of the applied bias. In depletion it increases roughly linearly with bias and is in good agreement with theoretical estimates, whereas in positive bias it tends to saturate as strong screening in the donor layers develops.

Electron scattering in the pseudomorphic InGaAs channel of an InGaAs-AlGaAs heterostructure grown by molecular beam epitaxy has been studied at low temperatures to optimize the layer structure for use at 300 K in high-frequency transistors (p-HEMTs). (C) 1999 Elsevier Science B.V. All rights reserved. Journal of Crystal Growth

The equilibration length between spin-polarized edge states in the Quantum Hall regime is measured as a function of a gate voltage applied to an electrode on top of the edge channels. Reproducible fluctuations in the coupling are observed and interpreted as a mesoscopic fingerprint of single spin-flip scatterers which are turned on and off. A model to analyze macroscopic edge state coupling in terms of individual scatterers is developed, and characteristic values for these scatterers in our samples are extracted. For all samples investigated, the distance between spin-flip scatterers lies between the Drude and the quantum scattering length., 4 pages, 2 figures

We have fabricated a novel type of lateral surface superlattice device comprising parallel, stressed ribs of In0.2Ga0.8As on a GaAs/Al0.3Ga0.7As heterostructure containing a high mobility two-dimensional electron gas (2DEG). Magnetotransport measurements were used to deduce the form and magnitude of the potential modulation. These experiments, supported by our calculations, indicate the importance of both piezoelectric coupling of stress to the electrons and the repulsive potential induced in the 2DEG by the removal of layers from the surface to define the superlattice.

We have investigated magnetically-induced charge redistribution within a delta modulation-doped GaAs-AlxGa1-xAs heterojunction structure by studying the photoluminescence due to electrons from the two-dimensional(2D) electron system recombining with photoexcited holes. At well defined values of magnetic field, charge transfer occurs between this 2D electron system and the V-shaped potential well formed in the AlxGa1-xAs by Si delta modulation-doping. This redistribution of charge is observed as discontinuities in the photoluminescence energies. From these measurements we have derived the characteristic transfer time for electrons to move between these two wells.

We show the experimental realization of a 108-GHz planar Gunn diode structure fabricated in GaAs/AlGaAs. There is a considerable interest in such devices since they lend themselves to integration into millimeter-wave and terahertz integrated circuits. The material used was grown by molecular beam epitaxy, and devices were made using electron beam lithography. Since the frequency of oscillation is defined by the lithographically controlled anode-cathode distance, the technology shows great promise in fabricating single chip terahertz sources.

Zero-dimensional electron gases have been fabricated by the strain-patterning of a GaAs/AlAs heterojunction using amorphous carbon stressors. We have used steady-state, time-resolved and temperature-dependent photoluminescence measurements to probe the occupied density of states of the electron gases. We observe a novel lateral confinement mechanism and efficient transfer of modulation-doped electrons from the regions between the stressors to the quantum dots. In finite magnetic fields we have mapped the evolution of the electron states from which we estimate the number of electrons per dot to be 15.

Magnetoresistance measurements and theoretical calculations for two-dimensional electron systems under a perpendicular magnetic field are presented which illuminate transport effects due to a periodic electrostatic potential modulation. We focus on features arising from the resolution of the magnetic miniband structure which are beyond the perturbative regime governed by the dispersion of Landau bands. Our non-perturbative quantum-mechanical calculations reveal that the dispersion of individual minibands is responsible for the complicated behaviour of the magnetoresistance in the regime of intermediate modulation strength. In particular, the interplay between miniband and scattering contributions to the conductivity leads to an almost structureless magnetoresistance in this regime followed by the formation of antidot peaks due to the miniband conductivity.

This paper investigates high resolution, low damage dry etching of tungsten, a suitable candidate for gate metallization in compound semiconductor based high mobility channel device, by using a Surface Technology Systems Ltd. (STS) inductively coupled plasma (ICP) etching system with SF"6 and C"4F"8 process gases. Low stress tungsten films with thicknesses in the range 100-200nm were deposited on GaAs substrates for the etching tests using a Plassys MP900S sputter coater. To evaluate the plasma-induced damage in the ICP etching process, GaAs based high electron mobility transistor (HEMT) type layer structures with channels buried less than 20nm from the surface, were grown by molecular beam epitaxy (MBE). Subsequently, Van der Pauw (VdP) structures were fabricated to enable determination of the impact of the etching on room temperature sheet resistivity, carrier concentration and electron mobility. The investigation of the effect of various etching parameters on the profile, minimum feature size and electrical damage has led to a low damage ICP etching process with minimum feature size of 25nm, which is suitable for the fabrication of compound semiconductor based high mobility channel devices.

Using magnetocapacitance data, we directly determine the chemical potential jump at low temperatures of about 25 mK when the filling factor traverses the spin gap at $\ensuremath{\nu}\phantom{\rule{0ex}{0ex}}=\phantom{\rule{0ex}{0ex}}1$ and the cyclotron gap at $\ensuremath{\nu}\phantom{\rule{0ex}{0ex}}=\phantom{\rule{0ex}{0ex}}2$. The chemical potential jump for the cyclotron gap is found to increase proportionally to the magnetic field with a slope that is determined by an effective mass ${0.071m}_{0}$. The data yield a spin gap that also increases proportionally with magnetic field and is described by an enhanced Land\'e factor $g\ensuremath{\approx}5.2$. This result has not been explained by existing theoretical models.

New dry-etch processes, such as low-power reactive-ion etching (RIE) and electron cyclotron resonance, offer very low levels of residual lattice damage. These levels are below the resolution limits of traditional characterisation methods like Raman, photoluminescence, Schottky diode, etc. We show that the single-electron charging of a quantum dot fabricated using dry etching offers a very sensitive method of damage detection. For SiCl 4 SiF 4 RIE of GaAs we find a defect density of around 1015 cm−3, which is at the level of the background impurity concentration in the as-grown material.

We study the capacitance of single electron wires in high quantizing magnetic fields. The capacitance spectra obtained on 300 nm wide electron channels are interpreted with a simple model considering the geometry of the incompressible stripes in the electron channel as function of filling factor. The capacitance spectra directly reflect the potential form of the wire edge. This is experimentally demonstrated by the dependence on the confinement potential as well as by a clear asymmetry of the capacitance minimum at filling factor v=2 that can be well explained with the model. For comparison we present capacitance spectra obtained on very narrow, but otherwise similar quantum wires, in which quantization into one-dimensional subbands dominates the behavior.

Photoluminescence spectroscopy has been used to probe the occupied electron states below the Fermi energy of zero-dimensional electron systems (0DESs) in both zero and finite magnetic fields. The arrays of modulation-doped quantum dots investigated were fabricated by both reactive-ion etching and strain-confining GaAs heterojunctions with a δ-layer of Be present in the GaAs, in order to improve luminescence efficiency. For the etched quantum dots we show that the low magnetic field dispersion (B

GaAs-based transistors with the highest f/sub T/ and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show f/sub T/ of 440 GHz, f/sub max/ of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and g/sub m/ of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies.

We have performed an experiment in the quantum Hall regime using a geometry that has connectivity between two and three depending on the applied gate voltage. The measurements may be interpreted in terms of either bulk or edge transport. However, the variable connectivity reveals fundamental differences in the current flow through the gated region in the two pictures. In the edge picture this current does not link the measurement contacts and is dissipationless; in the bulk picture it links the contacts and requires dissipation to flow. This extends previous results on the equivalence of the two pictures in simply connected geometries. \textcopyright{} 1996 The American Physical Society.

The capacitance of a single-electron wire at high quantizing magnetic fields is studied. We demonstrate that the capacitance spectroscopy allows us to study the formation of compressible and incompressible stripes directly. The electron wire is field induced in a metal insulator semiconductor heterostructure beneath a center gate. The electrostatic potential defining the wire edge is controlled by a tuning-fork-shaped electrode that encloses the center gate. It is found that the capacitance spectra are very sensitive to the wire edge potential and show a clear asymmetry of the capacitance minimum at filling factor n52. The experimental results are well described by a simple model considering the contribution of compressible and incompressible stripes in the electron channel, to the capacitance signal. The capacitance minima are thus determined in our experiments by the geometry of the compressible and incompressible stripes in the channel and not by the defect-induced density of states. @S0163-1829~96!02143-1#

Magnetoresistance studies on two-dimensional electron systems in GaAs - AlGaAs heterojunctions exposed to voltage-tunable square lateral superlattices with periods in the 100 nm range reveal at low temperatures a characteristic splitting of individual Landau bands. Around magnetic field values at which p/q flux quanta penetrate the unit cell of the superlattice, with p and q being small integers, p subbands can be observed. A discussion of which conditions have to be met to reveal such Hofstadter-type splitting of Landau bands illuminates the experimental difficulties that have to be overcome in chasing the Hofstadter butterfly.

We have studied a GaAs/AlAs periodic quantum dot array using reciprocal space mapping around the (0 0 4) and ( 1 1 3 ) reciprocal lattice points. Both the coherently and the diffusely scattered X-ray intensities were analyzed by performing two-dimensional model calculations. From the distribution of the diffracted intensities we deduced the average strain status in the dots. From the numerical simulations it is evident that random elastic strain fields are present, which extend through almost the entire volume of the quantum dot. The simulations of the X-ray measurements revealed that the crystalline part of the dots is considerably smaller as scanning electron micrographs would indicate.