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Safety-critical and mission-critical systems, such as airplanes or (semi-)autonomous cars, are relying on an ever-increasing number of embedded integrated circuits. Consequently, there is a need for complete defect coverage during the testing of these circuits to guarantee their functionality in the field. In this context, reducing the escape rate of defects during production testing is crucial, and significant progress has been made to this end. However, production testing using automatic test equipment is subject to various measurement parasitic variations, which may have a negative impact on the testing procedure and therefore limit the final defect coverage. To tackle this issue, this article proposes an improved test flow targeting increased analog defect coverage, both at the system and block levels, by analyzing and improving the coverage of typical functional and structural tests under these measurement variations. To illustrate the flow, the technique of inserting a pseudo-random signal at available circuit nodes and applying machine learning techniques to its response is presented. A DC-DC converter, derived from an industrial product, is used as a case study to validate the flow. In short, results show that system-level tests for the converter suffer strongly from the measurement variations and are limited to just under 80% coverage, even when applying the proposed test flow. Block-level testing, however, can achieve only 70% fault coverage without improvements but is able to consistently achieve 98% of fault coverage at a cost of at most 2% yield loss with the proposed machine learning–based boosting technique.

With tightening automotive IC production test requirements, test escape rates need to decrease down to the 10 PPB level. To achieve this for mixed-signal ICs, advanced multivariate statistical techniques are needed, as the defects in the test escapes become increasingly more difficult to detect. Therefore, this paper proposes applying a cascade of advanced statistical techniques to identify measurements that can be used as predictors to flag future potential failures at test time with minimal misclassification of good devices. The approach uses measurement data from the ATE wafer probe tests and is also able to identify the likely location of the defect using only these measurements. The cascade has four steps: 1) remove bias and spatial patterns within the data, 2) divide the different tests into relevant groups, 3) reduce the dimensionality of each group, and 4) perform multiple regression to find the predictor values and use these values to compute an outlier score for each chip under test. As there is a risk of overfitting the outlier score, the number of predictors used is kept to a minimum. The effectiveness of the proposed methodology is demonstrated using test data from an industrial production chip with eight field-return cases. Predictors have been found that retroactively allowed the identification of these chips, with an average of 5% false classification of good devices, i.e. devices not returned from the field. In addition, the selected predictors corresponded to where the defects are located according to failure analysis of the field returns.

A versatile, low power and energy efficient Capacitance-to-Digital Converter (CDC) for Internet-of-Things (IoT) is presented, based on an all-dynamic architecture with adaptable speed, resolution and range. Sampling rates from 1S/s up to 100kS/s are supported and capacitances from 1.23 to 24.59pF can be digitized while the power scales inherently from 0.1nW to 1μW. This makes the design versatile to efficiently deal with a variety of sensors with different speed requirements and different capacitance values. The 0.1nW lowest absolute power is >20x smaller than prior-art, and the Figure-of-Merit (FoM) from 18 to 59fJ/conv-step is also the lowest among prior designs. As example, by connecting a MEMS pressure sensor, this chip can measure environmental pressure with only 0.8nW at a speed of 100S/s.

© 2018 IEEE. Over the past few years, several self-calibration methodologies have proven their efficiency to calibrate analog and radio-frequency circuits against process variations. Specifically, statistical techniques based on machine-learning have been proposed to recover yield loss and even enhance circuit performances. In addition, these techniques enable to calibrate circuits after a single performance test, i.e. in one-shot. However, towards fully-integrated calibration techniques, the inference part of the machine learning algorithm needs to be performed as energy-efficiently as possible to reduce calibration cost to a minimum. Following the path of resource-efficient machine learning, this work explores an alternative to state-of-the-art Neural Network based statistical techniques. Specifically, we investigate the opportunities of using Bayesian Networks for resource-efficient on-chip statistical calibration of analog/RF circuits. Results will show that several improvements can be achieved using Bayesian Networks: (a) provide a comprehensive calibration framework with explicit relationships between parameters (b) demonstrate similar prediction accuracies that neural networks (c) optimize across several performance parameters with a single network and in a single query and (d) enable a more energy-efficient hardware implementation. The proposed self-calibration algorithm is applied to a low-noise amplifier fabricated with IBM's 130nm CMOS process, leading to a significant reduction in the number of operations required to obtain the best tuning knob setting. ispartof: 2018 IEEE INTERNATIONAL TEST CONFERENCE (ITC) vol:2018-October ispartof: 49th IEEE International Test Conference (ITC) location:AZ, Phoenix date:29 Oct - 1 Nov 2018 status: published

© 2018 IEEE. The numerous variations that affect analog and RF circuits are becoming a limiting factor in the design of these circuits in deeply scaled CMOS technologies. An emerging idea to counteract these effects is to let the circuit compensate for these variations itself, referred to as self-healing. Over the last decade, a wide variety of off- and on-chip techniques for compensating these variations have been researched. This paper targets to give an overview of the state-of-the-art, and organize the proposed techniques in a common taxonomy. This allows to determine remaining open issues and research challenges. In particular, the SotA lacks efficient solutions for fully-integrated, short time-scale self-adaptation. The paper ends by giving an outlook towards promising research directions to enable such self-adaptation in mWatt power budgets for Internet of things applications, focusing on embedded machine-learning techniques. ispartof: pages:131-134 ispartof: 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018 pages:131-134 ispartof: 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) location:SPAIN, Platja d Aro date:2 Jul - 4 Jul 2018 status: published

© 2018 IEEE. Recently, there has been an increasing demand for advanced classification capabilities embedded on wearable battery constrained devices, such as smartphones or watches. Achieving such functionality with a tight power and energy budget has proven a real challenge, specifically for large-scale neural network-based applications. Previously, cascaded systems have been proposed to minimize energy consumption for such applications, either through using a single wake-up stage, or by using a linear-or tree based cascade of consecutive classifiers that allow early termination. In this paper, we expand upon these concepts by generalizing cascades to hierarchical cascaded processing, where a hierarchy of increasingly complex classifiers, each designed and trained for a specific subtask is used. This hierarchical approach significantly outperforms the wake-up based approach by up to 2 orders of magnitude in energy consumption at iso-accuracy, specifically in systems with sparse input data such as speech recognition and visual object detection. This paper presents a general design framework for such systems and illustrates how to optimize them toward minimum energy consumption. The text further proposes a roofline model for cascaded systems, derives system level trade-offs and proves the approaches validity through a visual classification case-study. ispartof: IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS vol:8 issue:4 pages:884-894 status: published

A versatile resistive temperature sensor for Internet-of-Things is presented, based on an all-dynamic architecture. This allows efficient scaling of power with conversion rate, enables optional oversampling for an adaptable resolution, and provides efficient adaptability to different resistor values. A new double-sided measurement mode is proposed to compensate for offset, 1/f noise and nonidealities at system level. The sensor achieves a minimum power consumption of 174 pW at 1 S/s measurement rate, which scales up to 488.3 nW at 100 kS/s. It offers a nominal rms resolution of 0.61 °C and a resolution FoM as low as 1.82 pJ·°C2. ispartof: IEEE solid-state circuit letters vol:1 issue:3 pages:70-74 status: published

© 2017 ACM. Advancement in miniaturization of autonomous sensory agents can play a profound role in many applications such as the exploration of unknown environments, however, due to their miniature size, power limitations poses a severe challenge. In this paper, and inspired from biological instinctive behaviour, we introduce an instinct-driven dynamic hardware reconfiguration design scheme using evolutionary algorithms on behaviour trees. Moreover, this scheme is projected on an application scenario of autonomous sensory agents exploring an inaccessible dynamic environment. In this scenario, agent's compression behaviour-introduced as an instinct-is critical due to the limited energy available on the agents. This emphasises the role of optimization of agents resources through dynamic hardware reconfiguration. In that regard, the presented approach is demonstrated using two compression techniques: Zeroorder hold and Wavelet compression. Behavioural and hardwarebased power models of these techniques, integrated with behaviour trees (BT), are implemented to facilitate off-line learning of the optimum on-line behaviour, thus, facilitating dynamic reconfiguration of agents hardware. ispartof: pages:1727-1734 ispartof: Proceedings of the Genetic and Evolutionary Computation Conference GECCO pages:1727-1734 ispartof: GECCO location:Berlin date:15 Jul - 19 Jul 2017 status: published

The Phoenix project aims to develop a new approach to explore unknown environments, based on multiple measurement campaigns carried out by extremely tiny devices, called agents, that gather data from multiple sensors. These low power and low resource agents are configured specifically for each measurement campaign to achieve the exploration goal in the smallest number of iterations. Thus, the main design challenge is to build agents as much reconfigurable as possible. This paper introduces the Phoenix project in more details and presents first developments in the agent design. ispartof: pages:290-293 ispartof: Proceedings of Design Automation and Test conference 2017 pages:290-293 ispartof: Design Automation and Test in Europe (DATE) location:EPFL Campus, Lausanne, SWITZERLAND date:27 Mar - 31 Mar 2017 status: published

A calibration mechanism is often desired in analog/RF circuits that are designed in advance process nodes which exhibit large process variation, so as to recover yield loss and obtain the best possible trade-off between performances. In this paper, we present a calibration approach based on embedded sensors that has several appealing attributes. Specifically, it is virtually applicable to any circuit, the calibration mechanism is totally non-intrusive and, thereby, it does not degrade the performances of the circuit, and the calibration is performed in one-shot requiring a single test step, thus the calibration time is kept at a minimum. The proposed calibration approach is demonstrated experimentally on a 65 nm RF power amplifier based on fabricated chips from two corner wafers and a typical wafer.

Deep sub-micrometer CMOS technologies drive a large proportion of innovation in many industries, including transport, communications, biological sensors, and medical systems. The trend nowadays is to integrate analog/RF circuits together on the same die with the digital processor and memory in advance process nodes. A major challenge is that the amount of process variation becomes particularly pronounced, causing measurable and predictable variance in the output performance especially in the case of analog/RF circuits.

Testing the RF functions of mixed-signal Systems-on-Chip is responsible for a very large fraction of the overall test cost. In addition, RF circuits, when designed in the most advanced technologies (e.g. 65nm and beyond), typically require some calibration mechanisms so as to guarantee a high yield. Built-in test structures is a promising approach to facilitate test and calibration of RF circuits. However, tapping into RF signal paths may seriously degrade the performances and certainly necessitates co-designing the RF circuit together with the built-in test circuitry to meet the desired performance trade-off. This challenge finds the designers rather reluctant to adopt a built-in test approach. In this work, we develop a non-intrusive built-in test approach based on sensors that are totally transparent to the RF circuit. In particular, we show how performance deviations can be implicitly predicted by sensors that monitor process variations (e.g. Variation-aware sensors) and how defects can be detected by temperature sensors. In addition, we show that the variation-aware sensors can be used for calibrating the RF circuit in one-shot, that is, without requiring a test/calibration loop.

International audience; In the context of mission-critical, safety-critical, and remote-controlled applications, it is required to equip systems with self-adapting capabilities. Adaptation is required in post-manufacturing to correct yield loss and achieve zero defective parts-per-million as well as during normal operation to account for different application scenarios and for varying environmental conditions. A self-adaptive system must be capable of providing the required high performances after manufacturing and throughout its normal operation regardless the application scenario wherein it is deployed and despite the varying environmental conditions. In this paper, we describe a generic post-manufacturing self-adaptation technique for RF circuits as well as concurrent self-adaptation techniques for a safety-critical medical sensor for glaucoma diagnosis and for a NFC system which is very sensitive to the environment in which it operates.

International audience; We propose a post-fabrication calibration technique for RF circuits that is performed during production testing with minimum extra cost. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit. The technique is demonstrated on a 65nm RF power amplifier.

This paper presents an integrated circuit for mechanical energy harvesting applications which detects the electromechanical converter's maximum voltage in a very low power way. This circuit has been designed in AMS 0.35μm CMOS technology and its functionality and its efficiency have been validated with different kinds of converters (piezoelectric and electrostatic) at various mechanical frequencies (from 1 to 200 Hz). The experimental results have shown a power consumption of 150 nW under 3V with a delay of detection lower than 50μs. This circuit appears to be a relevant solution for all Application-Specific Integrated Circuits (ASIC) in which the harvesting methods are based on Synchronized Switch Harvesting techniques (SSH).

A mathematical pharmacodynamic model was developed to describe the bactericidal activity of marbofloxacin against Escherichia coli strains with reduced susceptibility levels (determined using MICs) under optimal and intestinal growth conditions. Model parameters were estimated using nonlinear least-square curve-fitting procedures for each E. coli strain. Parameters related to bactericidal activity were subsequently analyzed using a maximum-effect ( E max ) model adapted to account for a direct and a delayed effect. While net growth rates did not vary significantly with strain susceptibility, culture medium had a major effect. The bactericidal activity of marbofloxacin was closely associated with the concentration and the duration of exposure of the bacteria to the antimicrobial agent. The value of the concentration inducing a half-maximum effect ( C 50 ) was highly correlated with MIC values ( R 2 = 0.87 and R 2 = 0.94 under intestinal and optimal conditions, respectively). Our model reproduced the time-kill kinetics with good accuracy ( R 2 of >0.90) and helped explain observed regrowth.

A versatile, low-power, and energy-efficient capacitance-to-digital converter (CDC) for Internet-of-Things (IoT) is presented, based on an all-dynamic architecture with adaptable speed, resolution, and range. The proposed CDC includes a single-armed capacitive bridge and a differential switched-capacitor 10-b asynchronous successive approximation register (SAR) analog-to-digital-converter (ADC). The bridge output is directly sampled by the ADC through fully passive correlated-double-sampling (CDS) approach, which enables a fully dynamic operation. The design is fabricated in a 65-nm CMOS technology. Thanks to the dynamic nature of the CDC, sampling rates from 1 S/s up to 100 kS/s are supported and capacitances from 1.23 to 24.59 pF can be digitized, while the power scales inherently from 0.1 nW to $1~\mu \text{W}$ . Optionally, the range can be further extended to >100 pF, and oversampling can be used to enhance resolution. This makes the design versatile to efficiently deal with a variety of sensors having different speed and resolution requirements and different capacitance values. The 0.1 nW lowest absolute power is $> 20\times $ smaller than the prior art, and the figure of merit (FoM) from 18 to 59 fJ/conv-step is also the lowest among prior designs. To provide application examples, this chip is further verified with a microelectromechanical (MEMS) pressure sensor and a MEMS accelerometer. It can measure environmental pressure consuming only 0.8 nW at a speed of 100 S/s, and measure acceleration using 1.4 nW at a speed of 200 S/s.

Synthetic bio-systems become increasingly more complex and their development is lengthy and expensive. In the same way, in microelectronics, the design process of very complex circuits has benefited from many years of experience. It is now partly automated through Electronic Design Automation tools. Both areas present analogies that can be used to create a Genetic Design Automation tool inspired from EDA tools used in digital electronics. This tool would allow moving away from a totally manual design of bio-systems to assisted conception. This ambitious project is presented in this paper, with a deep focus on the tool that automatically generates models of bio-systems directly usable in electronic simulators.

Funding Information: This work is supported in part by the Academy of Finland 6Genesis Flagship program (Grant No. 318927), the Ministry of Economic Affairs, Innovation, Digitalisation and Energy of the State of North Rhine-Westphalia (MWIDE NRW) along with the Competence Center 5G.NRW under Grant No. 005-01903-0047, the Deutsche Forschungsgemeinschaft (DFG) within the Collaborative Research Center SFB 876 “Providing Information by Resource-Constrained Analysis”, project A4, European Union’s Horizon 2020 Research and Innovation Program under Grant 732174 (ORCA Project), European Commission through the Next Generation Internet Project “iNGENIOUS: Next-Generation IoT solutions for the universal supply chain” (H2020-ICT-2020-1 call) under Grant 957216, the Scientific and Technological Research Council of Turkey (TUBITAK) under 3501-Career Development Program (CAREER) Grant #118E920, Institute for Information & Communications Technology Promotion (IITP) Grant funded by the Korea government (MSIT) (No. 2020-0-01316, International cooperation and collaborative research on 5G+ technologies for ultra-reliability low latency communications) and the Indonesian Ministry of Finance under the LPDP RISPRO for the Grant under the project of “Prevention and Recovery Networks for Indonesia Natural Disasters Based on the Internet-of-Things (PATRIOT-Net)”. The authors would like to acknowledge the contributions of their colleagues in the project, although the views expressed in this work are those of the authors and do not necessarily represent the project. Publisher Copyright: © 2021, The Author(s). The recently introduced 5G New Radio is the first wireless standard natively designed to support critical and massive machine type communications (MTC). However, it is already becoming evident that some of the more demanding requirements for MTC cannot be fully supported by 5G networks. Alongside, emerging use cases and applications towards 2030 will give rise to new and more stringent requirements on wireless connectivity in general and MTC in particular. Next generation wireless networks, namely 6G, should therefore be an agile and efficient convergent network designed to meet the diverse and challenging requirements anticipated by 2030. This paper explores the main drivers and requirements of MTC towards 6G, and discusses a wide variety of enabling technologies. More specifically, we first explore the emerging key performance indicators for MTC in 6G. Thereafter, we present a vision for an MTC-optimized holistic end-to-end network architecture. Finally, key enablers towards (1) ultra-low power MTC, (2) massively scalable global connectivity, (3) critical and dependable MTC, and (4) security and privacy preserving schemes for MTC are detailed. Our main objective is to present a set of research directions considering different aspects for an MTC-optimized 6G network in the 2030-era.