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This thesis describes a range of experiments performed using a linear Paul trap to investigate the transverse beam dynamics of intense hadron accelerators. Due to the complexity of the dynamics in intense hadron accelerators, it is advantageous to use a scaled experiment to gain insight into these machines. A Paul trap is used to study accelerator dynamics, as the Hamiltonians of the two systems are equivalent. The IBEX Paul trap at the Rutherford Appleton Laboratory, Oxfordshire, has been commissioned. The first trapping of argon ions is observed, and the system is characterised, developing an understanding of the ion creation process, ion lifetime, longitudinal temperature, transverse emittance, and the process of ion extraction from the trap. A Faraday cup and MCP are used as diagnostics for the trap and are calibrated carefully to detect accurately the number of ions confined. Both the IBEX and S-POD (Hiroshima University, Japan) linear Paul traps are used to study space-charge-driven resonances quantitatively for the first time. The particle-in-cell code Warp is used to gain a deeper understanding of the experiment and to assist with the interpretation of results. Values are extracted describing the location of the greatest ion loss in tune space for a given intensity for equal transverse tunes. These values are compared to values predicted both analytically and through simulation. In the second half of this thesis, a design for a novel particle accelerator is considered, using the theory of Nonlinear Integrable Optics (NIO). In NIO, a highly nonlinear magnet is inserted into a linear lattice (known as a T-insert), resulting in regular and bounded particle motion. Detailed studies are undertaken to ascertain whether a simpler version of this theory, Quasi-Integrable nonlinear Optics (QIO), can be tested in a Paul trap. A T-insert lattice is designed to meet the constraints of QIO, as well as the constraints imposed by the IBEX hardware. A number of these lattices are tested on the IBEX trap, confirming that enough ions are confined to study QIO in the presence of space-charge forces and that it is possible to create a T-insert with sufficient precision. To verify that the T-insert lattice created within the Paul trap meets the conditions for QIO, a method to measure the beta function in a Paul trap has been designed and tested. Finally, a series of simulations are presented, showing that with a simple upgrade to the IBEX trap it is possible to create an octupole potential of high-enough quality to test QIO, while also retaining the ability to create a high-quality quadrupole to make the T-insert lattice. The impact of misalignment and scraping within the trap on the dynamic aperture and tune spread is studied using Warp. The resistance of the lattice to resonant excitation is investigated. The experimental and simulation studies described show that QIO can be tested in a Paul trap, and pave the way for a range of studies of this exciting concept.

In recent years it has become increasingly apparent that there is a large demand for resilient electronics that can operate within environments that standard silicon electronics cease to function such as high power and high voltage applications, high temperatures, corrosive atmospheres and environments exposed to radiation. This has become even more essential due to increased demands for sustainable energy production and the reduction in carbon emissions worldwide, which has put a large burden on a wide range of industrial sectors who now have a significant demand for electronics to meet these needs including; military, space, aerospace, automotive, energy and nuclear. In extreme environments, where ambient temperatures may well exceed the physical limit of silicon-based technologies, SiC based technology offers a lower cost and a smaller footprint solution for operation in such environments due to its advantageous electrical properties such as a high breakdown electric field, high thermal conductivity and large saturation velocity. High quality material on large area wafers (150 mm) is now commercially available, allowing the fabrication of reliable high temperature, high frequency and high current power electronic devices, improving the already optimised silicon based structures. An important advantage of SiC is that it is the only wide band gap compound semiconductor that can be thermally oxidised to grow insulating, high quality SiO2 layers, which makes it an ideal candidate to replace silicon technologies for metal-oxide-semiconductor applications, which is the main focus of this research. Although the technology has made a number of major steps forward over recent years and the commercial manufacturing process has advanced significantly, there still remains a number of issues that need to be overcome in order to fully realise the potential of the material for electronic applications. This thesis describes the characterisation of 4H-SiC CMOS structures that were designed for high temperature applications and fabricated with varying gate dielectric treatments and process steps. The influence of process techniques on the characteristics of metal-oxide-semiconductor (MOS) devices has been investigated by means of electrical characterisation and the results have been compared to theoretical models. The C-V and I-V characteristics of both MOS capacitor and MOSFET structures with varying gate dielectrics on both n-type and p-type 4H-SiC have been analysed to explore the benefits of the varying process techniques that have been employed in the design of the devices. The results show that the field effect mobility characteristic of 4H-SiC MOSFETs are dominated at low perpendicular electric fields by Coulomb scattering and at high electric fields by low surface roughness mobility, which is due to the rough SiC-SiO2 interface. The findings also show that a thermally grown SiO2 layer at the semiconductor-dielectric interface is a beneficial process step that enhances the interfacial characteristics and increases the channel mobility of the MOSFETs. In addition to this it is also found that this technique provides the most beneficial characteristics on both n-type and p-type 4H-SiC, which suggests that it would be the most suitable treatment for a monolithic CMOS process. The impact of threshold voltage adjust ion implantation on both the MIS capacitor and MOSFET structures is also presented and shows that the increasing doses of nitrogen that are implanted to adjust the threshold voltage act to improve the device performance by acting to modify the charge at the interface or within the gate oxide and therefore increase the field effect mobility of the studied devices.