91 results on '"Martens, Ewout"'
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2. Interleaved Pipelined SAR ADCs: Combined Power for Efficient Accurate High-Speed Conversion
3. A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET
4. Calibration Techniques for Optimizing Performance of High-Speed ADCs
5. A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration
6. Interleaved Pipelined SAR ADCs: Combined Power for Efficient Accurate High-Speed Conversion
7. A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS
8. A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier
9. A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
10. A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC
11. A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion
12. Asynchronous Event-Driven Clocking and Control in Pipelined ADCs
13. An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC
14. A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm
15. A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC
16. Analyzing continuous-time DELTA SIGMA modulators with generic behavioral models
17. An analytical integration method for the simulation of continuous-time delta-sigma modulators
18. High-Level Modeling and Synthesis of Analog Integrated Systems
19. A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm
20. 16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation
21. A 1.67-GSps TI 10-Bit Ping-Pong SAR ADC With 51-dB SNDR in 16-nm FinFET
22. A Compact Quad-Shank CMOS Neural Probe With 5,120 Addressable Recording Sites and 384 Fully Differential Parallel Channels
23. A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS
24. A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers
25. A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS
26. 3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm
27. 3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion
28. A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with −41.3 DB EVM at 1024 OAM in 28NM CMOS
29. A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
30. A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization
31. A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL
32. A 16nm 69dB SNDR 300MSps ADC with capacitive reference stabilization
33. A single-channel, 600Msps, 12bit, ringamp-based pipelined ADC in 28nm CMOS
34. A 0.7-1.15GHz Complementary Common-Gate LNA in 0.18µm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD Protection
35. A +70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends
36. A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation
37. A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS
38. A 150 kHz–80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS
39. 9.7 a self-calibrated 10mb/s phase modulator with -37.4db evm based on a 10.1-to-12.4ghz, -246.6db-fom, fractional-n subsampling pll
40. A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation
41. A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS
42. A 0.7–1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection
43. A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration
44. IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm
45. RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass $\Delta\Sigma$ Modulator and Polyphase Decimation Filter
46. Automated synthesis of complex analog circuits
47. A 60 dB SNDR 35 MS/s SAR ADC With <?Pub _newline ?>Comparator-Noise-Based Stochastic Residue Estimation.
48. IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm.
49. Conclusions.
50. Top-Down Heterogeneous Optimization.
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