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A novel method for the extraction of the lateral position of border traps in nanoscale MOSFETs is presented. Using technology computer-aided design (TCAD) simulations, we demonstrate that the dependence of the trap-induced threshold voltage shift on the drain bias is more sensitive to the lateral trap position than to the impact of random dopants. Based on this, the lateral defect position can be determined with a precision of several percent of the channel length. To demonstrate the correct functionality of our technique, we apply it to extract the lateral positions of experimentally observed traps. Although the most accurate algorithm is based on time-consuming TCAD simulations, we propose a simplified analytic expression, which allows for the extraction of the lateral trap position directly from the experimental data. While the uncertainty introduced by random dopants is

We propose two different approaches to describe carrier transport in n-laterally diffused MOS (nLDMOS) transistor and use the calculated carrier energy distribution as an input for our physical hot-carrier degradation (HCD) model. The first version relies on the solution of the Boltzmann transport equation using the spherical harmonics expansion method, while the second uses the simpler drift-diffusion (DD) scheme. We compare these two versions of our model and show that both approaches can capture HCD. We, therefore, conclude that in the case of nLDMOS devices, the DD-based variant of the model provides good accuracy and at the same time is computationally less expensive. This makes the DD-based version attractive for predictive HCD simulations of LDMOS transistors.

We present a physics-based hot-carrier degradation (HCD) model and validate it against measurement data on SiON n-channel MOSFETs of various channel lengths, from ultrascaled to long-channel transistors. The HCD model is capable of representing HCD in all these transistors stressed under different conditions using a unique set of model parameters. The degradation is modeled as a dissociation of Si-H bonds induced by two competing processes. It can be triggered by solitary highly energetical charge carriers or by excitation of multiple vibrational modes of the bond. In addition, we show that the influence of electron-electron scattering (EES), the dipole-field interaction, and the dispersion of the Si-H bond energy are crucial for understanding and modeling HCD. All model ingredients are considered on the basis of a deterministic Boltzmann transport equation solver, which serves as the transport kernel of a physics-based HCD model. Using this model, we analyze the role of each ingredient and show that EES may only be neglected in long-channel transistors, but is essential in ultrascaled devices.

We model the main characteristics of metal-insulator-silicon field-effect transistors (MISFETs) with different gate insulators using the carrier energy distribution function calculated with a Spherical Harmonics Expansion method. In addition to standard devices with Silicon Dioxide or Oxynitride we study a hypothetical MISFET with a rather new crystalline dielectric-Calcium Fluoride. The real physical parameters of the $$\hbox {CaF}_{2}$$ CaF 2 /Si tunnel barrier are used in our simulations. The obtained characteristics of the transistors with $$\hbox {CaF}_{2}$$ CaF 2 are, in some details, better than those of the devices with traditional oxides. Being a step forward in the context of the industrial implementation of fluorite, this work opens the possibility of simulating the characteristics of different silicon-based devices with crystalline insulators.

Recently, correlated drain and gate current fluctuations have been observed in nano-scaled MOSFETs, indicating that their occurrence is linked to the same defect. One explanation for this observation can be given by the multi-state defect model, which has been developed to describe the hole capture and emission processes involved in the bias temperature instability (BTI). This model relies on a combination of metastable defect states and nonradiative multi-phonon transitions. Our detailed investigations demonstrate that the observed gate current fluctuations and their correlation with the drain noise can be well reproduced using a TAT mechanism based on the multi-state model.

In this work, we concentrate on extending our optimization method for IGBTs [1] in drives applications by incorporating diode parameters in addition to IGBT parameters. For this purpose, the fabrication process of the diode, including a platinum diffusion and it's parameters for lifetime adjustment [2], was added to the optimization loop. Consequently, the simulation of an IGBT turn-on event in the optimization loop was required.

Many important performance parameters in an IGBT power semiconductor are heavily affected by its field-stop profile, its device thickness and its collector-side p-doping concentration. To find the optimum combination of these design parameters is of high importance for an optimal IGBT design. The optimization criteria include low switching and on-state losses as well as limited maximum overshoot voltage and modest current and voltage rise and fall times. This work focusses on an automated global optimization scheme to solve this issue. The method and definition of a proper target function are briefly explained. Finally, design optimizations found under different constraints are discussed.

We present a physical model for hot-carrier degradation (HCD) which is based on the information provided by the carrier energy distribution function. In the first version of our model the distribution function is obtained as the exact solution of the Boltzmann transport equation, while in the second one we employ the simplified drift-diffusion scheme. Both versions of the model are validated against experimental HCD data in nLDMOS transistors, namely against the change of such device characteristics as the linear and saturation drain currents. We also compare the intermediate results of these two versions, i.e. the distribution function, defect generation rates, and interface state density profiles. Finally, we make a conclusion on the vitality of the drift-diffusion based version of the model.

Channel hot carrier (CHC) stress is observed to result in higher variability of degradation in deeply-scaled nFinFETs than bias temperature instability (BTI) stress. Potential sources of this increased variation are discussed and the intrinsic time-dependent variability component is extracted using a novel methodology based on matched pairs. It is concluded that in deeply-scaled devices, CHC-induced time-dependent distributions will be bimodal, pertaining to bulk charging and to interface defect generation, respectively. The latter, high-impact mode will control circuit failure fractions at high percentiles.

Our physics-based HCD model has been validated using scaled CMOS transistors in our previous work. In this work we apply this model for the first time to a high-voltage nLDMOS device. For the calculation of the degrading behaviour the Boltzmann transport equation solver ViennaSHE is used which also requires high quality adaptive meshing. We discuss the influence of the different model components in the different device regions. Finally we compare the model to experimental degradation results and show that each one gives a significant contribution to the result and that all of them are needed in order to satisfactorily fit the experimental data.

Using our physics-based model for hot-carrier degradation (HCD) we analyze the role of such important processes as the Si-H bond-breakage induced by a solitary hot carrier, bond dissociation triggered by the miltivibrational excitation of the bond, and electron-electron scattering. To check the roles of these mechanisms we use planar CMOS devices with gate lengths varying between 65 and 300 nm as well as a high-voltage nLDMOS transistor. We show that the current HCD paradigm needs to be revised because the aforementioned processes can be crucial even under stress conditions at which they are supposed to be weak.

Although the traditional finite volume scheme based on boxes obtained from the dual Voronoi grid has been employed successfully for classical semiconductor device simulation for decades, certain drawbacks such as the required Delaunay property of the underlying mesh limit its applicability for two-and particularly three-dimensional device simulations on unstructured meshes. We propose a discretization based on mesh cells rather than dual boxes around vertices, which circumvents the Delaunay requirement, yet preserves all the important features of the traditional method such as exact current conservation. The applicability of our method is demonstrated for classical and semiclassical models to tackle current engineering problems: We consider three-dimensional drift-diffusion simulations of geometric variations of the fin in a FinFET and present results from spatially two-dimensional simulations of a high-voltage nLDMOS device based on spherical harmonics expansions for direct solutions of the Boltzmann transport equation.

We present and validate a novel physics-based model for hot-carrier degradation. The model incorporates such essential ingredients as a superposition of the multivibrational bond dissociation process and single-carrier mechanism, dispersion of the bond-breakage energy, interaction of the electric field and the dipole moment of the bond, and electron-electron scattering. The main requirement is that the model has to be able to cover HCD observed in a family of MOSFETs of identical architecture but with different gate lengths under diverse stress conditions using a unique set of parameters.

We present the first physics-based model for hot-carrier degradation which is able to capture degradation in both short- and long-channel SiON nMOSFETs. Degradation is considered to be due to the breaking of Si-H bonds at the SiON/Si interface. Contrary to previous modeling attempts, our approach now correctly considers the intricate superposition of multivibrational bond excitation and bond rupture induced by a solitary hot carrier based on experimentally confirmed distributed activation energies. All processes are treated as competing pathways, leading to bond dissociation from all vibrational levels. These rates are determined by the carrier acceleration integral and by the bond energetics. The acceleration integral is calculated using the carrier energy distribution. Corresponding distribution functions are found by a thorough solution of the Boltzmann transport equation. We demonstrate that electron-electron scattering plays the dominant role. As for the bond energetics, we consider the dispersion of the activation energy as well as its reduction induced by the interaction of the bond dipole moment with the electric field. All the model ingredients are incorporated into the same simulation framework based on the deterministic solver of the Boltzmann transport equation, ViennaSHE.

We propose a new method to determine the lateral position of border traps in MOSFETs. The approach is based on the dependence of the trap-induced threshold voltage shift on the drain bias which is sensitive to the trap position. This follows from the results obtained with both technology computer aided design (TCAD) simulations and with a compact model. Using our novel method we extract the lateral position of a number of experimentally observed traps. We show that even in the presence of random dopants the lateral position of the trap can be determined with a precision of several nanometers. Considering random dopants is one of the key features of our method. The compact model essentially allows to avoid time consuming TCAD simulations without significant loss of accuracy.

We present a novel approach to hot-carrier degradation (HCD) simulation, which for the first time considers and incorporates mechanisms crucial for HCD. First, two main pathways of Si-H bond dissociation, namely bond-breakage triggered by a single hot carrier and induced by multivibrational bond excitation, are combined and considered consistently. Second, we show how drastically electron-electron scattering affects the whole HCD picture. Furthermore, dispersion of the activation energy of bond dissociation substantially changes defect generation rates. Finally, the interaction between the electric field and the dipole moment of the bond leads to interface states created near the source end of the channel. To demonstrate the importance of all these peculiarities we use ultra-scaled n-MOSFETs with a channel gate of 65 nm.

A comprehensive study of correlated gate leakage and drain current fluctuations in nMOS devices using non-equilibrium Green's function calculations has been carried out. A simulation model combining 3D self-consistent electrostatic potentials accounting for random discrete dopants and charged oxide traps with a 1D and 2D transport description of direct-tunneling gate leakage has been developed. The influence of the charge state of the trap on the direct-tunneling current has been investigated. A considerable local change in current density around the trap has been observed. By varying the position of the trap it has been found that oxide defects close to the drain and source regions have a higher impact on the gate leakage. A statistical analysis of nMOSFETs by varying the configuration of the random discrete dopants has been performed. The trap has been positioned close to the drain to achieve a worst-case scenario. The reduction in direct-tunneling current due to charging of a single trap has been calculated for each device. Gate current reductions below one percent have been found. The experimentally measured large gate leakage fluctuations can thus not be accounted for with direct tunneling.

Recently, some experimental groups have observed the occurrence of correlated drain and gate current fluctuations, which indicate that both currents are influenced by the charge state of the same defect. Since the physical reason behind this phenomenon is unclear at the moment, we evaluated two different explanations: The first model assumes that direct tunneling of carriers is affected by the electrostatic field of the charged defect. Interestingly, this model inherently predicts the gate bias and temperature dependences observed in the experiments and is therefore quite promising at a first glance. In the second model, our multi-state defect model is employed to describe trap-assisted tunneling as a combination of two consecutive nonradiative multi-phonon transitions - namely hole capture from the substrate followed by hole emission into the poly-gate. The latter transition is found to be in the weak electron-phonon coupling regime, which requires the consideration of all band states instead of only the band edges. Our investigation shows that the electrostatic model must be discarded since it predicts only small changes in the gate current while the extended variant of the multi-state defect model delivers quite promising results.

We study the impact of individual charged gate oxide defects on the characteristics of nanoscaled pMOSFETs for varying body biases. Both a reduced time-zero variability and a reduced time-dependent variability are observed when a forward body bias is applied. In order to explain these observations, a model based on the modulation of the number of unscreened dopant atoms within the channel depletion region is proposed.

Recent studies have clearly demonstrated that the degradation of MOS transistors due to hot carriers is highly sensitive to the energy distribution of the carriers. These distributions can only be obtained in sufficient detail by the simultaneous solution of the Boltzmann transport equation (BTE) for both carrier types. For predictive simulations, the energy distributions have to be thoroughly resolved by including the fullband structure, impact ionization (II), electron electron scattering (EE), as well as the interaction of minority carriers with the majority carriers. We demonstrate that this challenging problem can be efficiently tackled using a deterministic approach based on the spherical harmonics expansion (SHE) of the BTE.

In nm-sized FET devices with just a few gate oxide defects, the typically measured threshold voltage shifts are not obviously correlated with the device behavior at high gate bias. The largest shifts observed at the threshold voltage after the capture of a single carrier are reduced at higher gate biases. This degradation-mitigating effect is further shown to be amplified at lower channel doping. The understanding gained from 3D numerical simulations is captured in a simple analytic description of a single trapped-charge impact on the FET characteristics in the entire gate bias range. Potential use is illustrated in an improved lifetime projection and in circuit simulations of time-dependent variability.

We study p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs) using the direct-current-current-voltage (DCIV) method before and after bias temperature stress. The stress is varied over a wide range of temperatures using our polyheater technology. The ability of the SRH model and a multistate non-radiative multiphonon (NMP) model to meaningfully reproduce the acquired DCIV data is compared. It is demonstrated that the SRH model cannot capture the detailed features of the data and a more detailed model is required.

Using our physics based model for hot-carrier degradation (HCD) we analyze the importance of the effect of electron–electron scattering (EES) on HCD in transistors with different channel lengths. The model is based on a thorough treatment of carrier transport and is implemented into the deterministic Boltzmann transport equation solver ViennaSHE. Two competing mechanism of Si–H bond-breakage are captured by the model: the one triggered by the multiple vibrational excitation of the bond and another which is due to excitation of one of the bonding electrons to an antibonding state by a solitary hot carrier. These processes are considered self-consistently as competing pathways of the same dissociation reaction. To analyze the importance of the EES process we use a series of nMOSFETs with identical architecture but different gate lengths. The gate length varies in the wide range of 44–300 nm to cover short-channel MOSFETs as well as their longer counterparts. According to previous findings, EES starts to become important at a channel length of 180 nm. This situation is captured in the targeted gate length interval. Our results show that the channel length alone is not a sufficient criterion on the importance of EES and that the applied bias conditions have to be taken into account as well.

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Journal of computational electronics 15(3), 939-958 (2016). doi:10.1007/s10825-016-0828-z, Published by Springer Science + Business Media B.V., Dordrecht