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Ohmic, memristive synaptic weights are fabricated with a back-end-of-line compatible process, based on a 3.5 nm HfZrO4 thin film crystallized in the ferroelectric phase at only 400 degrees C. The current density is increased by three orders of magnitude compared to the state-of-the-art. The use of a metallic oxide interlayer, WOx, allows excellent retention (only 6% decay after 10(6) s) and endurance (10(10) full switching cycles). The On/Off of 7 and the small device-to-device variability (, Advanced Electronic Materials, 8 (6), ISSN:2199-160X

Phase-change materials (PCMs), which are well-established in optical and random-access memories, are increasingly studied for emerging topics such as brain-inspired computing and active photonics. ...

The in-memory computing paradigm aims at overcoming the intrinsic inefficiencies of Von-Neumann computers by reducing the data-transport per arithmetic operation. Crossbar arrays of multilevel memristive devices enable efficient calculations of matrix-vector-multiplications, an operation extensively called on in artificial intelligence (AI) tasks. Resistive random-access memories (ReRAMs) are promising candidate devices for such applications. However, they generally exhibit large stochasticity and device-to-device variability. The integration of a sub-stoichiometric metal-oxide within the ReRAM stack can improve the resistive switching graduality and stochasticity. To this purpose, a conductive TaOx layer is developed and stacked on HfO2 between TiN electrodes, to create a complementary metal-oxide-semiconductor-compatible ReRAM structure. This device shows accumulative conductance updates in both directions, as required for training neural networks. Moreover, by reducing the TaOx thickness and by increasing its resistivity, the device resistive states increase, as required for reduced power consumption. An electric field-driven TaOx oxidation/reduction is responsible for the ReRAM switching. To demonstrate the potential of the optimized TaOx/HfO2 devices, the training of a fully-connected neural network on the Modified National Institute of Standards and Technology database dataset is simulated and benchmarked against a full precision digital implementation., Advanced Electronic Materials, 8 (10), ISSN:2199-160X

III-V semiconductors are ideal for light sources due to their tunable and direct band gap in the telecommunication band [1] , [2] , but their monolithic integration on Si is challenging, because of the significant thermal, polarity and lattice mismatch. At IBM Research we developed template-assisted selective epitaxy (TASE) [3] , [4] , where III-Vs nucleate at a confined Si seed and grow within an empty predefined oxide template. Using TASE, InP whispering gallery mode (WGM) lasers on Si emitting at ~840nm with comparable performance to wafer bonded devices were demonstrated [5] . To fully leverage the potential of integrated photonics, operation beyond the Si absorption edge is desired. Here, we extend TASE to the growth of InGaAs WGM cavities and demonstrate evidence of lasing at 300 K and 1530 nm. We subsequently compare the devices with previously reported InP WGM lasers.

III–V materials, such as InGaAs and InP, are highly attractive for high-performance electronics and optoelectronics owning to their high carrier mobilities and potential for bandgap engineering. Integration on silicon substrates, however, is a key requirement to enable widespread adoption of these materials. In this work, direct wafer bonding (DWB) of III–V materials is explored as a low-temperature enabling technology for Si integration. For high-performance logic and RF electronics, DWB is compared to competing integration technologies and is shown to exhibit higher device performance due to its relatively low process complexity and thermal impact (~300 °C). Due to the low thermal impact of DWB, it is also uniquely suitable for 3-D integration, i.e., vertical stacking of multiple functional layers. III–V optoelectronics are attractive in such 3-D stacks, where they can enable high-efficiency tunable lasers together with Si photonics integrated circuits. DWB is here compared to selective epitaxy as an integration route for InP-on-Si microdisk lasers. Plasmonics are explored as well, allowing scaling of integrated III–V photonic devices beyond the diffraction limit of light. The results of this work show that DWB is a highly promising integration route for III–V materials for both electronics and optoelectronics applications.

A key component for optical on-chip communication is an efficient light source. However, to enable low energy per bit communication and local integration with Si CMOS, devices need to be further scaled down. In this work, we fabricate micro- and nanolasers of different shapes in InP by direct wafer bonding on Si. Metal-clad cavities have been proposed as means to scale dimensions beyond the diffraction limit of light by exploiting hybrid photonic-plasmonic modes. Here, we explore the size scalability of whispering-gallery mode light sources by cladding the sidewalls of the device with Au. The metal clad cavities demonstrate room temperature lasing upon optical excitation for Au-clad devices with InP diameters down to 300 nm, while the purely photonic counterparts show lasing only down to 500 nm. Numerical thermal simulations support the experimental findings and confirm an improved heat-sinking capability of the Au-clad devices, suggesting a reduction in device temperature of 473 K for the metal-clad InP nanodisk laser, compared to the one without Au. This would provide substantial performance benefits even in the absence of a hybrid photonic-plasmonic mode. These results give us insight into the benefits of metal-clad designs to downscale integrated lasers on Si., 15 pages, 7 figures

Integration of high-quality semiconductor-superconductor devices into scalable and complementary metal-oxide-semiconductor compatible architectures remains an outstanding challenge, currently hindering their practical implementation. Here, we demonstrate growth of InAs nanowires monolithically integrated on Si inside lateral cavities containing superconducting TiN elements. This technique allows growth of hybrid devices characterized by sharp semiconductor-superconductor interfaces and with alignment along arbitrary crystallographic directions. Electrical characterization at low temperature reveals proximity induced superconductivity in InAs via a transparent interface.

The seamless integration of III-V nanostructures on silicon is a long-standing goal and an important step towards integrated optical links. In the present work, we demonstrate scaled and waveguide coupled III-V photodiodes monolithically integrated on Si, implemented as InP/In0.5Ga0.5As/InP p-i-n heterostructures. The waveguide coupled devices show a dark current down to 0.048 A/cm2 at -1 V and a responsivity up to 0.2 A/W at -2 V. Using grating couplers centered around 1320 nm, we demonstrate high-speed detection with a cutoff frequency f3dB exceeding 70 GHz and data reception at 50 GBd with OOK and 4PAM. When operated in forward bias as a light emitting diode, the devices emit light centered at 1550 nm. Furthermore, we also investigate the self-heating of the devices using scanning thermal microscopy and find a temperature increase of only ~15 K during the device operation as emitter, in accordance with thermal simulation results., Nature Communications, 13, ISSN:2041-1723

III–V semiconductors, such as indium-rich InGaAs, are promising as replacements for the Si channel in CMOS technology. In this work, we demonstrate a scaled III–V FinFET technology, integrated on Si substrates using a direct wafer bonding technique. Logic performance down to physical gate lengths of 20 nm and fin widths of 15 nm is explored. Narrow-bandgap materials such as these are susceptible to band-to-band tunneling in the off-state, which enhances the parasitic bipolar effect (an accumulation of holes in the channel region). We here examine the use of source and drain spacers to mitigate this effect, showing a two orders of magnitude improvement in the off-state characteristics of scaled III–V FETs. The parasitic bipolar effect can also be beneficial in enabling a memory effect in the FET. In the second part of the work, we explore this effect towards capacitorless 1 T DRAM cells. We show that the use of a quantum well in these devices can enhance retention times and lead to a significant reduction of the power density.

In this work we will discuss the use of Template-Assisted Selective Epitaxy (TASE) for the monolithic in-plane integration of active III-V photonic devices on silicon. We will show the use for highspeed InGaAs detectors, as well as for hybrid III-V/Si photonic crystal structures.

The thermoelectric properties of a nanoscale germanium segment connected by aluminium nanowires are studied using scanning thermal microscopy. The germanium segment of 168 nm length features atomically sharp interfaces to the aluminium wires and is surrounded by an Al2O3 shell. The temperature distribution along the self-heated nanowire is measured as a function of the applied electrical current, for both Joule and Peltier effects. An analysis is developed that is able to extract the thermal and thermoelectric properties including thermal conductivity, the thermal boundary resistance to the substrate and the Peltier coefficient from a single measurement. Our investigations demonstrate the potential of quantitative measurements of temperature around self-heated devices and structures down to the scattering length of heat carriers.

The thermoelectric properties of a nanoscale germanium segment connected by aluminium nanowires are studied using scanning thermal microscopy. The germanium segment of 168 nm length features atomically sharp interfaces to the aluminium wires and is surrounded by an Al2O3shell. The temperature distribution along the self-heated nanowire is measured as a function of the applied electrical current, for both Joule and Peltier effects. An analysis is developed that is able to extract the thermal and thermoelectric properties including thermal conductivity, the thermal boundary resistance to the substrate and the Peltier coefficient from a single measurement. Our investigations demonstrate the potential of quantitative measurements of temperature around self-heated devices and structures down to the scattering length of heat carriers.

Photonic crystal (PhC) cavities are promising candidates for Si photonics integrated circuits due to their ultrahigh quality (Q)-factors and small mode volumes. Here, we demonstrate a novel concept of a one-dimensional hybrid III-V/Si PhC cavity which exploits a combination of standard silicon-on-insulator technology and active III-V materials. Using template-assisted selective epitaxy, the central part of a Si PhC lattice is locally replaced with III-V gain material. The III-V material is placed to overlap with the maximum of the cavity mode field profile, while keeping the major part of the PhC in Si. The selective epitaxy process enables growth parallel to the substrate and hence, in-plane integration with Si, and in-situ in-plane homo- and heterojunctions. The fabricated hybrid III-V/Si PhCs show emission over the entire telecommunication band from 1.2 {\mu}m to 1.6 {\mu}m at room temperature validating the device concept and its potential towards fully integrated light sources on silicon., Comment: 10 pages, 5 figures

In the present talk we discuss the development of the epitaxial technique Template-Assisted Selective Epitaxy (TASE)and its application for the monolithic integration of scaled III - V active photonic devices on silicon. A unique advantage of TASE for silicon photonics applications is that it enables a truly local integration of III-V material at precisely defined positions, it is therefore particularly suited for densely Integrated nanophotonic devices. Here we will discuss our work on InP-based microdisk lasers fabricated by either direct TASE growth or via the use of micro-substrates. Optical mode simulations using Lumerical are used to explore the design space. Notably, we are exploring the use of metal-clad cavities for further light confinement. The metal-clad cavities enable scaling of the laser diameter beyond what is achievable with a pure photonic cavity. Thermal simulations are used to explore the impact of the metal-cladding as a heat sink as opposed to plasmonic operation. We also evaluate the potential for electrical actuation and will show first results on monolithic photodetectors, using Sentaurus simulations to improve our understanding of device performance.

In this paper, we demonstrate InGaAs FinFETs 3-D sequentially (3DS) integrated on top of a fully depleted silicon-on-insulator CMOS. Top layer III–V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. We demonstrate that the low thermal budget of the top layer process does not affect the lower level FETs performance. An on-current of $200~\mu \text{A}/\mu \text{m}$ (at $I_{\mathrm{ OFF}} = 100$ nA/ $\mu \text{m}$ and $V_{\mathrm{ DD}} = 0.5$ V) is achieved, representing the highest reported for 3DS integrated III–V FETs on silicon, showing a 50% improvement in $R_{\mathrm{ ON}}$ compared to previous work. The achieved improved performance can be attributed to the introduction of spacers, doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.

In the present talk we discuss the application of Template-Assisted Selective Epitaxy (TASE) for the monolithic integration of III-V active photonic devices on silicon. The main concept of TASE relies on the guided growth of III-Vs within a confined oxide template. At one extremity of the template there is access to silicon to start the nucleation, and subsequently it is the template which guides the growth progression. This decoupling of the resulting geometry from the growth mode and substrate orientation, results in a larger processing window as we no longer rely on the growth conditions to tune the geometry, as well as a number of other advantages. A further unique advantage of TASE for silicon photonics applications is that it allows for the truly local integration of III-V material at precisely defined positions, since the location of the III-V may be defined with nm-scale precision in the same lithographic step as silicon passives. TASE was originally developed for electronics, but in recent years we have expanded it to enable several photonic devices. In the present talk, I will discuss our work on GaAs and InP microdisk lasers fabricated by either direct growth or via the use of micro-substrates. These devices show lasing at room temperature around 870 nm with thresholds of about 10 pJ/pulse. We also explore the use of metal-clad cavities for further light confinement.

In this work, we review progress in III-V transistor technologies. Key approaches for silicon integration are described, with a distinction being made between large area layer transfer and selective growth techniques. We show how the integration approach must be tailored for the intended application to maximize performance, functionality and minimize cost. We also highlight performance boosters such as heterostructure channel stacks, which offer increased carrier mobility towards improved RF and RF-CMOS performance. Recent progress in tunneling field-effect transistors (TFETs) have enabled the TFET architecture as a process module, allowing for dense integration with MOSFETs on the same chip towards an extremely low-power CMOS technology. Finally, we highlight emerging applications for III-V devices at cryogenic temperatures, where there is a rising need for low-power electronics to support the scaling of quantum computers. The unique properties of III-V, their high mobility and band gap engineering make them highly suitable for this application.

High-resolution lithography often involves thin resist layers which pose a challenge for pattern characterization. Direct evidence that the pattern was well-defined and can be used for device fabrication is provided if a successful pattern transfer is demonstrated. In the case of thermal scanning probe lithography (t-SPL), highest resolutions are achieved for shallow patterns. In this work, we study the transfer reliability and the achievable resolution as a function of applied temperature and force. Pattern transfer was reliable if a pattern depth of more than 3 nm was reached and the walls between the patterned lines were slightly elevated. Using this geometry as a benchmark, we studied the formation of 10-20 nm half-pitch dense lines as a function of the applied force and temperature. We found that the best pattern geometry is obtained at a heater temperature of ∼600 °C, which is below or close to the transition from mechanical indentation to thermal evaporation. At this temperature, there still is considerable plastic deformation of the resist, which leads to a reduction of the pattern depth at tight pitch and therefore limits the achievable resolution. By optimizing patterning conditions, we achieved 11 nm half-pitch dense lines in the HM8006 transfer layer and 14 nm half-pitch dense lines and L-lines in silicon. For the 14 nm half-pitch lines in silicon, we measured a line edge roughness of 2.6 nm (3σ) and a feature size of the patterned walls of 7 nm.

Neuromorphic computing architectures enable the dense co-location of memory and processing elements within a single circuit. This co-location removes the communication bottleneck of transferring data between separate memory and computing units as in standard von Neuman architectures for data-critical applications including machine learning. The essential building blocks of neuromorphic systems are non-volatile synaptic elements such as memristors. Key memristor properties include a suitable non-volatile resistance range, continuous linear resistance modulation and symmetric switching. In this work, we demonstrate voltage-controlled, symmetric and analog potentiation and depression of a ferroelectric Hf$_{57}$Zr$_{43}$O$_{2}$ (HZO) field effect transistor (FeFET) with good linearity. Our FeFET operates with a low writing energy (fJ) and fast programming time (40 ns). Retention measurements have been done over 4-bits depth with low noise (1%) in the tungsten oxide (WO$_{x}$) read out channel. By adjusting the channel thickness from 15nm to 8nm, the on/off ratio of the FeFET can be engineered from 1% to 200% with an on-resistance ideally >100 kOhm, depending on the channel geometry. The device concept is using earth-abundant materials, and is compatible with a back end of line (BEOL) integration into complementary metal-oxidesemiconductor (CMOS) processes. It has therefore a great potential for the fabrication of high density, large-scale integrated arrays of artificial analog synapses., 14 pages, 5 figures, supplementary information available, submitted to ACS Applied Materials & Interfaces