Search

Anticipation of failures caused by resin flow during chip encapsulation can be studied and effectively prevented during manufacturing through accurate process modeling. To achieve this degree of accuracy, experimental data are fitted with preexisting material models that can describe the main physicals phenomenon. These models are employed in numerical simulations to assess filling issues, such as voids and welding lines, while also wires deformation during the encapsulation process. The simulation results are confirmed as well by comparison with experimental trials and data, such as filling short shots and wire sweeping experiments. The real-life results are in good agreement with the simulation one.

The process of microchip encapsulation by epoxy resin injection is simulated by employing moldflow modeling. In this work, the use of modeling allows to reproduce the unbalanced flow behavior of the resin within the mold cavity during the filling stage which leads to the formation of voids in the molded package. Simulation results are compared to experimental findings, in which the molding process is interrupted at designed points in time. Comparison shows good agreement between numerical outputs and experimental data and demonstrates the effectiveness of the model. After modeling is validated, the numerical methodology is applied to optimized package design in order to minimize the risk of issues caused by the filling stage. As a result, geometric variations show a significant effect on filling front progression avoiding the generation of structural defects during molding process.

Vertical power devices require thin dice to reach high electrical performance especially for automotive market. Beside their several advantages, thin power devices reveal issues related to assembly processes. Die bonding process step typically generates solder voids which can lead to thermal-induced fails. The paper deals with die thickness optimization in order to reduce the risk of failures due to the presence of voids by considering manufacturing limitations. For this purpose, electro-thermal modeling is employed to calculate the temperature at which fail occurs. Further, it allows to estimate the impact of die thickness and solder void size on the device temperature distribution during operating life.

Controlling warpage in backend manufacturing is a challenge that needs to be tackled in early design stage. Failure to do so may result in later manufacturability or reliability issues. This is of particular importance in BGA automotive packages where warpage could influence not only backend workability but also later thermal cycling reliability performance of the package mounted on board. Previous study has dealt separately with post Post Mold Curing (PMC) and post reflow processes. Experimental trials have been performed followed by material characterization tests and Finite Element Method (FEM) methodology development. This paper deals with a complete explanation of BGA warpage behavior in backend and provides a reliable guideline for new design bill of material selection with the intention to design for manufacturability and reliability at an early stage. In doing so design cycles can be significantly reduced as will be the need for exhaustive design of experiment.

The mechanical reliability of thin plastic packages during soldering reflow process on circuit board and thermal cycle becomes one of the most critical aspect in device mounting and operation. When a package is subjected to thermal loadings, deformation and deviation from an ideal uniform planar flatness usually result. Package warpage leads to thermo-mechanical issues at those sites of weak adhesion in the structure. The estimation of warpage is necessary for increasing package reliability. This paper deals with in-situ characterization of temperature-induced package warpage by adopting fringe pattern projection principle. The experimental analysis allows to evaluate real-time dynamic warpage at different target temperatures. In addition, numerical modeling is employed to identify the most critical material interface when a package is subjected to thermal loads. Simulation results are in good agreement with standard reliability trials on packages mounted on board.

Understanding and predicting warpage behavior during backend process is key to avoiding workability issues during manufacturing and later reliability issues during testing or during the device operational lifetime. To achieve this several challenges are encountered amongst which are the various temperature loadings that the material has to go through during processing. These temperature loadings can have different effects on warpage. This paper deals with understanding how different assembly processes can effect warpage with particular focus on the ball attach reflow assembly process.

When a plastic package is subjected to reflow, deformation and deviation from an ideal uniform planar flatness usually results. In the case of ball grid array (BGA) packages, warpage is caused by the thermal expansion mismatch between an organic substrate and other components constituting the package assembly. Substrate stack-up is mainly constituted of copper and core material. An accurate estimation of the coefficient of thermal expansion (CTE) of substrate materials becomes necessary for increasing package reliability during soldering reflow. This paper deals with in-situ characterization of in-plane deformation by adopting a methodology based on the digital image correlation (DIC) principle. First, the CTE measurement by DIC is validated by analysing copper laminates and comparing results with literature values. Then, the evaluation is performed for different components of the BGA substrate stack-up. The analysis allows to determine the CTE of these materials at various temperatures encountered during ball attach reflow process. Experimental results help to investigate the impact of the different components on the thermo-mechanical properties of organic substrates. In particular, it is found that copper has a major contribution during the heating-up stage of the soldering process, while core material behaviour becomes prominent during cooling-down.

Open through silicon vias are direct vertical connections between different integration levels of a chip which provide higher performances per unit area in three-dimensional integrated circuits. The reliability of such structures in integrated circuits constitutes an important issue in microelectronics. This paper deals with electromigration reliability and lifetime evaluation of open copper through silicon vias. The model for electromigration induced voiding is proposed to describe the resistance change with time during the reliabilityanalysis. The model is derived by considering two distinctive failure phases, namely void initiation and void evolution, and their contributions on the complete interconnect lifetime estimation. Numerical calculations are carried out to reproduce the physical phenomenon. The resistance trace shows the typical initial flat constant part followed by non-linear time increase. Therefore, simulation results provide a good description of the time resistance change and, consequently, the electromigration lifetime evaluation in open copper through silicon vias.

Open Through Silicon Vias (TSVs) are interconnections in three dimensional technologies. The tungsten material is usually employed as conductor line and it has high value of tensile intrinsic stress. The stress generated during the deposition process needs to be studied in order to avoid the mechanical failure of the TSV. We simulated the tungsten Volmer-Weber growth for a full plate sample. Subsequently, the sidewall area of the Open TSV was investigated. Due to the etch process, a formation of a surface roughness along the sidewall, called scallops, characterizes the Open TSVs. This particular structure lead to a different stress distribution in the tungsten layer. We reproduced the tungsten growth process on a scallops surface demonstrating an important decrease of the film stress compared to the full plate sample. The simulations of the Volmer-Weber growth can be an important tool for the design optimization of TSV.

Electromigration (EM) degradation and failure in modern interconnect structures are result of several physical phenomena acting together. In order to increase reliability thoroughly understanding of these phenomena and their interplay is necessary. In the case of dual-damascene technology both geometry and microstructure of the interconnect play an important role, determining the development of EM degradation. In this paper we use a state-of-the-art EM modeling and simulation for a comparative study of EM performance of standard straight interconnect structure and a structure with a right angle. It has been shown that by applying a detailed model of EM driven vacancy dynamics in the presence of grain boundaries, current crowding due to right angle of the interconnect geometry has a less impact than microstructure.

Through silicon vias (TSVs) are innovative interconnects which provide wider functionality and higher performance per unit area in three-dimensional (3D) integrated circuits. The reliability of TSVs in integrated circuits constitutes an important issue in microelectronics. One of the most relevant degradation mechanisms in interconnects is electromigration (EM). Therefore, the prediction of the EM failure behavior is a crucial necessity. Traditionally, Black's equation has been used from the early times of EM investigations for the estimation of the time to failure (TTF) for a wide spectrum of different interconnects. In this work we investigate the applicability of Black's equation for the estimation of the EM failure time in open copper TSV technologies. The EM void nucleation model has been solved by numerical calculations. Simulations have been carried out for different current densities. The results are in good agreement with Black's equation.

Recently, Through Silicon Vias (TSVs) have attracted much attention in three-dimensional (3D) integration technology due to their function as vertical connections of the different stacked semiconductor dies. Since electromigration (EM) will continue to be a key reliability issue in modern structures, the prediction of the EM failure behavior is a crucial necessity. Traditionally, Black's equation has been used from the early times of EM investigations for the estimation of the interconnect time to failure. In this work we investigate the applicability of Black's equation to open copper TSV structures using TCAD. TCAD can significantly contribute to the comprehension of EM failure mechanisms, in particular for the understanding of the early failure mode dominated by the void nucleation mechanism. The simulation procedure is applied to an open copper TSV technology in order to find the sites where void formation is most likely to occur. The time to failure is determined as the time needed to reach the stress threshold for void nucleation. Simulations are carried out for different current densities and successfully fitted to Black's equation. In this way, we have shown that failure development in studied TSV structures obeys Black's equation.

The mechanical and electrical properties of solder bumps influence the overall reliability of 3D ICs. A characteristic of solder bumps is that during technology processing and usage their material composition changes. This compositional transformation is enhanced by electromigration and leads to the formation of voids which can cause a complete failure of a solder bump. In this paper we present a compact model for prediction of the mean-time-to-failure of solder bumps under the influence of electromigration.