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A linear front-end electronic system based on a high-speed charge sensitive amplifier and a tunable shaping amplifier suitable for silicon detectors has been presented. The designed charge sensitive amplifier features simplicity and compactness. It is based on the combination of a low-noise field-effect transistor input device and a current feedback opamp ensuring high frequency and small rise time. The circuit provides both an energy signal and a timing signal. The shaping amplifier is a fifth-order complex filter based on an opamp- RC topology providing a nearly Gaussian response. The shaper also includes a pole-zero cancellation circuit and a base line restorer to preclude the pileup of subsequent input signals. A control system has been developed to adjust the main parameters of the channel. The designed readout channel has been optimized for a medium energy range up to 50 MeV coupled to silicon detectors up to 100 pF. Its feasibility for nuclear physics applications has been experimentally validated.

A new digital countermeasure against attacks related to the clock frequency is presented. This countermeasure, known as frequency sensor, consists of a local oscillator, a transition detector, a measurement element and an output block. The countermeasure has been designed using a full-custom technique implemented in an Application-Specific Integrated Circuit (ASIC), and the implementation has been verified and characterized with an integrated design using a 0.35 μm standard Complementary Metal Oxide Semiconductor (CMOS) technology (Very Large Scale Implementation—VLSI implementation). The proposed solution is configurable in resolution time and allowed range of period, achieving a minimum resolution time of only 1.91 ns and an initialization time of 5.84 ns. The proposed VLSI implementation shows better results than other solutions, such as digital ones based on semi-custom techniques and analog ones based on band pass filters, all design parameters considered. Finally, a counter has been used to verify the good performance of the countermeasure in avoiding the success of an attack., This work has been supported by the Spanish Ministry of Science and Innovation, and FEDER funds under grant FPA2010-22131-C02-02, and by the Andalusian Innovation, Science and Enterprise Council, under grant P10-TIC-6311.

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 μm CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 μA/V to 165 μA/V) and a total harmonic distortion of −67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.