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This paper presents a novel discrete-time and fully programmable cellular neural network (CNN) suitable for processing one-dimensional (1-D) signals. As 1-D signals are typically very long sequences, the system consists of a linear analog shift register for data I/O coupled to a 1×n CNN array. In addition to the 1-D CNN architecture, a unique feature of our implementation is that the number of multipliers needed to implement both CNN templates has been minimized. This is conceivable because the multipliers are multiplexed between the A*y and B*u products during alternating phases of the controlling clock. The CNN system has been implemented in current mode based on the S2I technique using MOSIS Orbit 2 µm CMOS technology. The paper presents a thorough behavioral analysis of the new architecture, circuit-level implementations, and corresponding measured experimental results

The analysis, design, and implementation of a two-step current-sampling switched-current (S2I) multiplier is presented. The S2I technique has been employed to compensate analog errors due to charge injection as well as those arising from the finite output impedance. A thorough circuit analysis investigating the offset sources of the S2I cell and of the multiplier's nonlinearities sets up the platform to effectively design the multiplier and to avoid the use of feedback, or cascode techniques, to deal with channel modulation effects. The multiplier has been implemented using a 2-µm n-well MOSIS CMOS technology. Experimental results are in agreement with the theoretical findings. The following are brief highlights of the measurement results: (1) 0.425 millions of multiplications per second; (2) 1.7% total harmonic distortion for a sinusoidal of 35-µA (50 Hz); (3) 206 kHz of bandwidth; (4) 50 dB of SNR; and (5) 0.3-mW zero input power consumption for a ±3-V power supply. A complete set of detailed experimental results is provided in the paper

While VLSI of CNNs has seen significant progress in two-dimensional signal processing little has been done for one-dimensional applications such as audio signal processing and 1-D filtering. The paper presents a discrete-time programmable cellular neural network suitable for these kind of applications. The proposed VLSI implementation is based on the well-known S2I technique that among other properties minimizes clock feedthrough effects. This feature renders an accurate signal processing unit. The system's main building blocks are an analog shift register and a switched current multiplier. Yet, the system architecture is novel by itself. Namely, the number of multipliers has been minimized by sharing the multipliers between the A*y and B*u products during the various phases of the controlling clock. The paper presents detailed simulation results of the system architecture

In this paper a new approach for the realization of the DNA computing paradigm is presented. It exploits the natural richness of chaotic dynamics to efficiently generate and process coded binary sequences following the DNA computing framework introduced by Adleman (1994). The new method is discussed and some simulation results regarding the Directed Hamiltonian Path problem are presented