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Thermally-induced transitions between bistable magnetic states of magnetic tunnel junctions (MTJ) are of interest for generating random bitstreams and for applications in stochastic computing. An applied field transverse to the easy axis of a perpendicularly magnetized MTJ (pMTJ) can lower the energy barrier (Eb) to these transitions leading to faster fluctuations. In this study, we present analytical and numerical calculations of Eb considering both coherent (macrospin) reversal and non-uniform wall-mediated magnetization reversal for a selection of nanodisk diameters and applied fields. Non-uniform reversal processes dominate for larger diameters, and our numerical calculations of Eb using the String method show that the transition state has a sigmoidal magnetization profile. The latter can be described with an analytical expression that depends on only one spatial dimension, parallel to the applied field, which is also the preferred direction of profile motion during reversal. Our results provide nanodisk energy barriers as a function of the transverse field, nanodisk diameter, and material characteristics, which are useful for designing stochastic bitstreams., Under review process in Physical Review Applied by the American Physical Society

Perpendicular magnetic tunneling junctions(pMTJs) as true random number generators (TRNGs) have been investigated by means of high-temperature micromagnetic simulations using MuMax3. An in-plane applied field, which lowers the energy barrier for thermally activated reversal, can be used to control and increase the bitrates. We study the attempt rate and the energy barrier for 10 and 40 nm diameter devices in various applied magnetic fields. At room temperature, the presence of the field leads to orders of magnitude increase in the bitrate, up to ∼ 100 MHz., QC 20230920

Spin-Hall nano-oscillators are a promising class of microwave spintronic devices with potential applications in RF/microwave communication and neuromorphic computing. The nano-constriction spin-Hall nano-oscillators (NC-SHNO) have relatively high power, narrow linewidth, and low drive current. Several synchronization schemes e.g. arrays of spin-wave coupled oscillators have been proposed for more stable operation and higher output power. For such arrays, it is crucial to have good oscillator stability and small device-to-device variability. Here, a micromagnetic simulation technique is proposed that includes realistic material properties and hence enables variability and modal stability to be investigated. It is demonstrated, using both measurements and simulation, that the presence of physical grains in the free magnetic layer can induce multiple oscillation modes or frequency sidebands. Our investigation could help in the development of more stable NC-SHNOs that would enable oscillator arrays with stronger synchronization., QC 20220329

This study investigates the citation practices of electrical engineering (EE) and computer science (CS) bachelor students. A citation category based coding scheme for content analysis was developed to study the academic writing genre, represented by final year thesis reports. The academic writing skill-set displayed by CS and EE bachelor students was gauged by interpretative content analysis of a corpus of full-text theses, retrieved from a university repository. Two research questions were addressed: 1) what are the citation practices, employed by two cohorts of final year bachelor students, in electrical engineering and computer science? 2) what use of academic writing genre conventions can be quantified through interpretative content analysis? The intention of the study was to categorize the purposes behind citation use in bachelor level theses. Both student cohorts displayed an exaggerated use of citations, deviating from fully mature academic writing practices in the CS and EE fields. Many factual statements of a general nature were supported by multiple and weakly motivated instances of citations to a limited set of sources. An apparent genre convention was to cite sources mainly in text segments of introductory or survey character. Hence the investigated bachelor level theses made little use of citations to support the choice of research question, method or in critical discussion of results., Part of ISBN 9781665491174QC 20230823

Herein, results from noise and dark current density studies on InAs/GaSb type-II superlattice IR detectors are presented. The activation energy of the dark current density is used to identify the dominating dark current mechanisms (generation–recombination (GR), tunneling, or diffusion dark current) as a function of temperature and bias. The bias evolution of the power spectral density (PSD) is measured in dark conditions for several temperatures. At the operating bias of the detectors, the arrays show a white noise–dominated spectrum up to 100 K with a minor 1/f contribution (corner frequency around 10 Hz), while for higher temperatures the spectra are 1/f dominated. The 1/f noise component is compared to the dominating dark current mechanism in the same temperature and bias regimes. A strong correlation between the 1/f noise component and the dominating dark current (I) is found, with the PSD proportional to I for tunneling currents and I2 for GR and diffusion currents. Very low noise coefficients of αGR = 4.8 × 10−9 Hz−1, αdiff = 1.9 × 10−10 Hz−1, and αtun = 2.1 × 10−16 A Hz−1 are observed for these detectors. © 2020 Wiley-VCH GmbH, QC 20201202

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects,defects at the SiO2/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development.

An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art., QC 20200325

A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta (β) and collector current (IC) variation of SiC devices as temperature increases. The PDK-based complex digital ICsdesign flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications., QC 20190410

Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation is further aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, an alternative small-signal, S-parameter based design method can be employed directly without going into complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 °C) was accessed by on-wafer probing and connected by RF-cables to the rest of circuit passives, which were kept at room temperature (RT)., QC 20191104

Digital electronics in SiC find use in high-temperature applications. The objective of this study was to fabricate SiC CMOS without using ion implantation. In this letter, we present a recessed channel CMOS process. Selective doping is achieved by etching epitaxial layers into mesas. A deposited SiO2-film, post-annealed at lowtemperature and re-oxidized in pyrogenic steam, is used as the gate oxide to produce a conformal gate oxide over the non-planar topography. PMOS, NMOS, inverters, and ring oscillators are characterized at 200 °C. The PMOS requires reduced threshold voltage in order to enable long term reliability. This result demonstrates that it is possible to fabricate SiC CMOS without ion implantation and by low-temperature processing., QC 20190428

This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW., QC 20190311

Background and purpose Since the first level (bachelor) thesis was introduced at KTH in the degree programs students are exposed to scientific writing at an early stage in their education. A key element of scientific writing is an efficient use of citations i.e. references to published work in the area. From a teacher perspective many first level thesis reports showed poor quality in this respect. In order to be able to study this observation, from a quantitative or empirical point of view, development a well-defined scientific method was highly motivated. Work done In my work a method, based on so called content analysis, was proposed and used to study student behavior in first level thesis reports, regarding their use of citations. The objective was to look at categories of in-text citations and to find evidence, supporting a hypothesis, that student use of citations show distinct patterns. These patterns could reflect that they rely too much on facts and show too little evidence of learning, regarding synthesis from reliable and valid scientific sources, in their respective technical domain. The citation category method, proposed by me, starts from an a priori set of “use cases” or “in-text citation categories”. Based on these categories all citations could be coded for further statistical analysis. Observations The empirical results were based on nine first level (BS) reports. These were selected to represent programs at the different schools at KTH. A full search was done in DiVA for the time span June 2013- June 2015 and the selected reports are a random sampling of the 1300 reports, found in the in the database. The results clearly points towards a use of citations, where “presenting a fact” is emphasized over most other use cases. The use of a citation to “introduce or discuss contrasting views” or “in support of an argument” is seldom observed. On the other hand, the bulk of the in-text citations are used to shape the background survey. In extre, QC 20190412

A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices., QC 20211004

A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices., QC 20180611

This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C., QC 20180601

This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW., QC 20180509

Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation isfurther aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, analternative small-signal, S-parameter based design method can be employed directly without goinginto complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 0C) was accessed by on-wafer probing and connectedby RF-cables to the rest of circuit passives, which were kept at room temperature (RT)., Accepted for publication in Materials Science Forum.QC 20190507

Silicon carbide (SiC) integrated circuits have been suggested for extreme environment operation. The challenge of a new technology is to develop process flow, circuit models and circuit designs for a wide temperature range. A bipolar technology was chosen to avoid the gate dielectric weakness and low mobility drawback of SiC MOSFETs. Higher operation temperatures and better radiation hardness have been demonstrated for bipolar integrated circuits. Both digital and analog circuits have been demonstrated in the range from room temperature to 500 degrees C. Future steps are to demonstrate some mixed signal circuits of greater complexity. There are remaining challenges in contacting, metallization, packaging and reliability.

In Part I, we have established a wafer-scale, CMOS compatible graphene transfer for the back end of the line integration. In Part II of this paper, we analyze statistical data of device properties and draw conclusions about possible causes of device failure. Statistical analysis is performed for device mobility and compared with the yield analysis. To complement this analysis, detailed Raman spectra are employed to analyze strain. In addition, device models developed in Part I are examined and provide further insight. From the analysis, it appears that compressive strain introduced during the graphene transfer process is may be the primary source for device failure. Moreover, we speculate based on the device statistics that the mitigation of compressive strain will improve device mobility, carrier density, and reduce variability. In addition, the presence of residues, tears, and cracks in the graphene may result in some device failure., QC 20170918

Wafer-scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing., QC 20170918

Spin torque nano-oscillators (STNO) represent a unique class of nano-scale microwave signal generators and offer a combination of intriguing properties, such as nano sized footprint, ultrafast modulation rates, and highly tunable microwave frequencies from 100 MHz to close to 100 GHz. However, their low output power and relatively high threshold current still limit their applicability and must be improved. In this study, we investigate the influence of the bottom Cu electrode thickness (t(Cu)) in nano-contact STNOs based on Co/Cu/NiFe GMR stacks and with nano-contact diameters ranging from 60 to 500 nm. Increasing t(Cu) from 10 to 70 nm results in a 40% reduction of the threshold current, an order of magnitude higher microwave output power, and close to two orders of magnitude better power conversion efficiency. Numerical simulations of the current distribution suggest that these dramatic improvements originate from a strongly reduced lateral current spread in the magneto-dynamically active region., QC 20170601

Spin torque nano-oscillators [1,2] (STNO) represent a unique class of nano-scale microwave signal generators where spin transfer torque [3-5] (STT) from a direct spin-polarized current drives and controls the auto-oscillation of the local free layer magnetization, which through its oscillating magnetoresistance transforms the direct current into a tunable microwave voltage., QC 20180226

QC 20170201

Silicon Carbide (SiC) bipolar integrated circuits are a promising technology for extreme environment applications. SiC bipolar technology shows stable operation over a wide range of temperature. However, the current gain of the devices is suffering from high surface recombination, due to poor oxide passivation. In this paper we propose a gated base structure that offers improved current gain control. A polysilicon gate is formed on the passivation oxide on top of the base-link region. We investigate the current gain as a function of gate bias and temperature. A negative gate bias improves the gain at low collector current by more than 30% by suppressing the surface recombination. Measurements are presented at temperatures ranging from 300 K to 550 K and the gain is consistently improved. The proposed structure is also useful as a process monitor for the passivation oxide quality., QC 20171123

QC 20181213

This paper reviews the state of the art in spin-torque and spin-Hall-effect-driven nano-oscillators. After a brief introduction to the underlying physics, the authors discuss different implementations of these oscillators, their functional properties in terms of frequency range, output power, phase noise, and modulation rates, and their inherent propensity for mutual synchronization. Finally, the potential for these oscillators in a wide range of applications, from microwave signal sources and detectors to neuromorphic computation elements, is discussed together with the specific electronic circuitry that has so far been designed to harness this potential., QC 20161111

The rapid development of the magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology demands an analytical model to enable building MTJ STO-based circuits and systems so as to evaluate and utilize MTJ STOs in various applications. In Part I of this paper, an analytical model based on the macrospin approximation has been introduced and verified by comparing it with the measurements of three different MTJ STOs. In Part II, the full Verilog-A implementation of the proposed model is presented. To achieve a reliable model, an approach to reproducing the phase noise generated by the MTJ STO has been proposed and successfully employed. The implemented model yields a time domain signal, which retains the characteristics of operating frequency, linewidth, oscillation amplitude, and DC operating point, with respect to the magnetic field and applied DC current. The Verilog-A implementation is verified against the analytical model, providing equivalent device characteristics for the full range of biasing conditions. Furthermore, a system that includes an MTJ STO and CMOS RF circuits is simulated to validate the proposed model for system-and circuit-level designs. The simulation results demonstrate that the proposed model opens the possibility to explore STO technology in a wide range of applications., QC 20150408

Magnetic tunnel junction (MTJ) spin torque oscillators (STOs) have shown the potential to be used in a wide range of microwave and sensing applications. To evaluate the potential uses of MTJ STO technology in various applications, an analytical model that can capture MTJ STO's characteristics, while enabling system-and circuit-level designs, is of great importance. An analytical model based on macrospin approximation is necessary for these designs since it allows implementation in hardware description languages. This paper presents a new macrospin-based, comprehensive, and compact MTJ STO model, which can be used for various MTJ STOs to estimate the performance of MTJ STOs together with their application-specific integrated circuits. To adequately present the complete model, this paper is divided into two parts. In Part I, the analytical model is introduced and verified by comparing it against measured data of three different MTJ STOs, varying the angle and magnitude of the magnetic field, as well as the DC biasing current. The proposed analytical model is suitable for being implemented in Verilog-A and used for efficient simulations at device, circuit, and system levels. In Part II, the full Verilog-A implementation of the analytical model with accurate phase noise generation is presented and verified by simulations., QC 20150408

QC 20150512