Search

The increasing utility of specialized circuits and growing applications of optimization call for the development of efficient hardware accelerator for solving optimization problems. Hopfield neural network is a promising approach for solving combinatorial optimization problems due to the recent demonstrations of efficient mixed-signal implementation based on emerging non-volatile memory devices. Such mixed-signal accelerators also enable very efficient implementation of various annealing techniques, which are essential for finding optimal solutions. Here we propose a “weight annealing” approach, whose main idea is to ease convergence to the global minima by keeping the network close to its ground state. This is achieved by initially setting all synaptic weights to zero, thus ensuring a quick transition of the Hopfield network to its trivial global minima state and then gradually introducing weights during the annealing process. The extensive numerical simulations show that our approach leads to a better, on average, solutions for several representative combinatorial problems compared to prior Hopfield neural network solvers with chaotic or stochastic annealing. As a proof of concept, a 13-node graph partitioning problem and a 7-node maximum-weight independent set problem are solved experimentally using mixed-signal circuits based on, correspondingly, a 20 × 20 analog-grade TiO2 memristive crossbar and a 12 × 10 eFlash memory array. [ABSTRACT FROM AUTHOR]

We present a lightweight, suitable for Internet of Things (IoT) devices, integrated design of physically unclonable function (PUF) and true random number generator (TRNG) based on embedded flash memory in 55-nm CMOS. In the proposed approach, the randomness in nonlinear I - V characteristics and temporal current fluctuations of embedded flash memories are exploited to generate the dynamic and static entropies. Shared silicon in designing PUF and TRNG results in a very compact and energy-efficient topology. Experimental and simulation results demonstrate >10200 key space, 0.58-pJ/b energy efficiency for < 5% controllable bit error rate at 80 °C, up to 192.3-Mbps throughput, high Shannon entropy, and resiliency toward machine learning attacks. Accelerated aging measurements indicate stable physical unclonable function response after 900 min of baking at 85 °C. [ABSTRACT FROM AUTHOR]

This article provides a comprehensive review of experimental work on security primitives based on emerging and mature nonvolatile memories (NVMs). The focus is on physically unclonable functions (PUFs) that exploit process-induced variations to generate a die-specific random response. We identify two main types of the proposed designs and discuss their advantages and main challenges. Endurance and reliability are serious concerns in PUFs relying on large-signal stochastic switching properties of NVMs in the verification phase. Such designs do not seem to be appealing in terms of energy, throughput, and security. On the other hand, circuit primitives that exploit sneak-path current and device nonlinearity are genuinely more suitable for building strong PUFs, but they are susceptible to environmental variations. Achieving high reliability in such PUFs is the main challenge, and finding a practical holistic solution with integrated optimum security and performance characteristics is an important research direction. We further note that many PUF works have been performed on a single memory cell level. The proposed implementations and their performance projected based on experimental data show a low bit error rate, however, at the cost of poor resilience to modeling attacks. Without further justification, these approaches can be only classified for now as weak PUFs, and moreover, more work would be needed to verify their physical unclonability. This article is concluded by outlining the most urgent experimental and modeling future work and the exciting prospects for NVM-based PUFs. [ABSTRACT FROM AUTHOR]