36 results on '"Mahatme, N."'
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2. Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology
3. A critical re-examination of body-bias on the soft error rate and single-event latch-up in automotive SRAMs
4. Effects of Total-Ionizing-Dose Irradiation on SEU- and SET-Induced Soft Errors in Bulk 40-nm Sequential Circuits
5. Effects of Temperature and Supply Voltage on SEU- and SET-Induced Errors in Bulk 40-nm Sequential Circuits
6. Effects of temperature and supply voltage on SEU- and SET-induced single-event errors in bulk 40-nm sequential circuits
7. Analysis of temporal masking effect on single-event upset rates for sequential circuits
8. Exploiting low power circuit topologies for soft error mitigation
9. Hardware based empirical model for predicting logic soft error cross-section
10. Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology
11. Influence of Voltage and Particle LET on Timing Vulnerability Factors of Circuits
12. Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology
13. The Contribution of Low-Energy Protons to the Total On-Orbit SEU Rate
14. An SEU-Tolerant DICE Latch Design With Feedback Transistors
15. Terrestrial SER characterization for nanoscale technologies: A comparative study
16. Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors
17. Impact of Technology Scaling on SRAM Soft Error Rates
18. Geometry Dependence of Total-Dose Effects in Bulk FinFETs
19. Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits.
20. Soft error rate comparison of various hardened and non-hardened flip-flops at 28-nm node
21. Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits
22. Scalability of Capacitive Hardening for Flip-Flops in Advanced Technology Nodes
23. Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation
24. Experimental Estimation of the Window of Vulnerability for Logic Circuits
25. Estimating the frequency threshold for logic soft errors
26. Impact of Back-Gate Bias and Device Geometry on the Total Ionizing Dose Response of 1-Transistor Floating Body RAMs
27. Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology
28. Radiation hardness aspects of advanced FinFET and UTBOX devices
29. Total ionizing dose effects on ultra thin buried oxide floating body memories
30. Temperature dependence of soft error rate in flip-flop designs
31. Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process
32. Impact of strained-Si PMOS transistors on SRAM soft error rates
33. Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies
34. Impact of technology scaling on the combinational logic soft error rate.
35. Analysis of multiple cell upsets due to neutrons in SRAMs for a Deep-N-well process.
36. Prevalence of depressive disorders among head-and-neck cancer patients: A hospital-based, cross-sectional study.
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