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3. New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses

4. Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective

5. Statistical Power Estimation of Behavioral Descriptions

6. Channel-wise Mixed-precision Assignment for DNN Inference on Constrained Edge Nodes

12. Thermal-aware clock tree design to increase timing reliability of embedded SoCs

13. Architectural leakage power minimization of scratchpad memories by application-driven subbanking

17. CONTREX : Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties

19. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits

24. Middleware services for network interoperability in smart energy efficient buildings

48. SMAC: Smart Systems Co-design

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