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The super-KEKB B factory, currently under construction at the KEK High Energy Accelerator Research Organization in Japan, has a goal of producing 50 ab^-1 of integrated luminosity, thus allowing the Belle II experiment to study rare decays of B mesons, D mesons, and \tau leptons. Such large statistics on these decays provide an experimental probe of physics beyond the Standard Model. An online trigger system is indispensable to Belle II to reduce the number of beam background events associated with high electron and positron beam currents, as well as to enhance physics-oriented events. For this purpose, we have designed the Belle II online trigger system with two kinds of primary Level 1 trigger components: a track trigger and an energy trigger. The track trigger is composed of 2-dimensional and 3-dimensional tracking algorithms, and the energy trigger implements algorithms based on total energy, isolated clusters, and identification of Bhabha events. In addition, precise event trigger timing and muon tagging information are provided by the time-of-propagation detector and iron flux return muon detector, respectively. [ABSTRACT FROM PUBLISHER]

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processor. [ABSTRACT FROM AUTHOR]

The size of future high-performance SoC is such that the time-of-flight of wires connecting distant pins in the layout can be much higher than the clock period. In order to keep the frequency as high as possible, the wires may be pipelined. However, the insertion of flip-flops may alter the throughput of the system due to the presence of loops in the logic netlist. In this paper, we address the problem of floorplanning a large design where long interconnects are pipelined by inserting the throughput in the cost function of a tool based on simulated annealing. The results obtained on a series of benchmarks are then validated using a simple router that breaks long interconnects by suitably placing flip-flops along the wires. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel, high throughput field-programmable gate array (FPGA) architecture, PITIA, which combines the high-performance of application specific integrated circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. The new architecture, which targets datapath circuits, uses the concepts of wave steering and pipelined interconnects. We discuss the FPGA architecture and show results for performance, power consumption, clock network performance, and routability. Results for some commonly used datapath designs are encouraging with throughputs in the neighborhood of 625 MHz in 0.25-µm 2.5-V CMOS technology. Results for random benchmark circuits are also shown. We characterize designs according to their Rent's exponents and argue that designs with predominantly local interconnects are the best fit in PITIA. We also show that as technology scales down toward deep submicron, PITIA shows an increasing throughput performance. [ABSTRACT FROM AUTHOR]

Proposes an algorithm for the automatic partitioning of on-chip SRAM into multiple banks. Reduction of energy of the embedded system; Integration of the partitioning algorithm with the physical design phase of layout information; Average energy savings.

This paper targets the acceleration of complex stochastic simulations of biochemical systems by a dedicated hardware architecture on configurable devices (FPGA). Existing approaches are discussed and compared with the proposed one, and experimental data is introduced to support the feasibility of the system. Retargetable hardware description can be automatically generated for any suitable simulation problem, and preliminary results show very high performance - 100 million time steps per second for large models (1000 reactions).

An accurate Field Programmable Gate Array (FPGA) based ECG Analysis system is described in this paper. The design, based on a popular software based QRS detection algorithm, calculates the threshold value for the next peak detection cycle, from the median of eight previously detected peaks. The hardware design has accuracy in excess of 96% in detecting the beats correctly when tested with a subset of five 30 minute data records obtained from the MIT-BIH Arrhythmia database. The design, implemented using a proprietary design tool (System Generator), is an extension of our previous work and uses 76% resources available in a small-sized FPGA device (Xilinx Spartan xc3s500), has a higher detection accuracy as compared to our previous design and takes almost half the analysis time in comparison to software based approach.