8,790 results on '"MOTHERBOARDS"'
Search Results
2. Buck converter with switched capacitor charge compensation for fast transient response.
- Author
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Zhou, Wanxin, Song, Kezhu, Wu, Chuan, Zhu, Chengyang, and Xie, Dongyi
- Subjects
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CAPACITOR switching , *VOLTAGE regulators , *CAPACITORS , *MICROPROCESSORS , *MOTHERBOARDS - Abstract
As microprocessor currents exceed 500 A and slew rate reaches 1000 A/µs, increasing the decoupling capacitance on the motherboard to ensure normal operation of the microprocessor is inevitable because of the limited response capability of the voltage regulator. However, the area of the motherboard used for capacitors is usually narrow. To reduce the required capacitance, a novel buck converter with an auxiliary circuit for charge compensation using switched capacitors is proposed. The auxiliary circuit is not activated during the steady state. When the load current changes rapidly, the switched capacitors can quickly absorb or release charge to suppress voltage fluctuations. A 12 V–0.9 V buck converter has been built and tested under a 480 A load current step and a 960 A/µs current slew rate. The proposed scheme with 9.964 mF capacitance has an overshoot of 115 mV and an undershoot of 89 mV. Compared with the conventional PID scheme, the proposed scheme can save 58.4% of the capacitance for the same voltage fluctuations or suppress 39.5% of overshoot and 37.3% of undershoot with the same capacitance. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
3. The ATLAS experiment software on ARM.
- Author
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Elmsheuser, Johannes, Barreiro Megino, Fernando, De Salvo, Alessandro, De Silva, Asoka, Hauser, Reiner, Konstantinov, Dmitri, Krasznahorkay, Attila, Lassnig, Mario, Sailer, Andre, and Snyder, Scott
- Subjects
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CENTRAL processing units , *MOTHERBOARDS , *ARCHITECTURE , *ERGONOMICS - Abstract
With an increased dataset obtained during the Run 3 of the LHC at CERN and the even larger expected increase of the dataset by more than one order of magnitude for the HL-LHC, the ATLAS experiment is reaching the limits of the current data processing model in terms of traditional CPU resources based on x86_64 architectures and an extensive program for software upgrades towards the HL-LHC has been set up. The ARM architecture is becoming a competitive and energy efficient alternative. Some surveys indicate its increased presence in HPCs and commercial clouds, and some WLCG sites have expressed their interest. Chip makers are also developing their next generation solutions on ARM architectures, sometimes combining ARM and GPU processors in the same chip. Consequently it is important that the ATLAS software embraces the change and is able to successfully exploit this architecture. We report on the successful porting to ARM of the Athena software framework, which is used by ATLAS for both online and offline computing operations. Furthermore we report on the successful validation of simulation workflows running on ARM resources. For this we have set up an ATLAS Grid site using ARM compatible middleware and containers on Amazon Web Services (AWS) ARM resources. The ARM version of Athena is fully integrated in the regular software build system and distributed in the same way as other software releases. In addition, the workflows have been integrated into the HEPscore benchmark suite which is the planned WLCG wide replacement of the HepSpec06 benchmark used for Grid site pledges. In the overall porting process we have used resources on AWS, Google Cloud Platform (GCP) and CERN. A performance comparison of different architectures and resources will be discussed. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
4. Ranking-based neural network for ambiguity resolution in ACTS.
- Author
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Allaire, Corentin, Bouvet, Françoise, Grasland, Hadrien, and Rousseau, David
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- *
NEURAL circuitry , *INSTITUTIONAL repositories , *MOTHERBOARDS , *ALGORITHMS , *ALGEBRA - Abstract
The reconstruction of particle trajectories is a key challenge of particle physics experiments, as it directly impacts particle identification and physics performances while also representing one of the main CPU consumers of many high-energy physics experiments. As the luminosity of particle colliders increases, this reconstruction will become more challenging and resourceintensive. New algorithms are thus needed to address these challenges efficiently. One potential step of track reconstruction is ambiguity resolution. In this step, performed at the end of the tracking chain, we select which tracks candidates should be kept and which must be discarded. The speed of this algorithm is directly driven by the number of track candidates, which can be reduced at the cost of some physics performance. Since this problem is fundamentally an issue of comparison and classification, we propose to use a machine learning-based approach to the Ambiguity Resolution. Using a shared-hits-based clustering algorithm, we can efficiently determine which candidates belong to the same truth particle. Afterwards, we can apply a Neural Network (NN) to compare those tracks and decide which ones are duplicates and which ones should be kept. This approach is implemented within A Common Tracking Software (ACTS) framework and tested on the Open Data Detector (ODD), a realistic virtual detector similar to a future ATLAS one. This new approach was shown to be 15 times faster than the default ACTS algorithm while removing 32 times more duplicates down to less than one duplicated track per event. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
5. Federated Access from DOE Labs to Distributed Storage in the EIC Era of Computing.
- Author
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Poat, M.D., Lauret, J., and Rao, T.
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ELECTRONS , *COMPUTING platforms , *METHODOLOGY , *MOTHERBOARDS - Abstract
The Electron Ion Collider (EIC) collaboration and future experiment is a unique scientific ecosystem within Nuclear Physics as the experiment starts right off as a crosscollaboration between Brookhaven National Lab (BNL) & Jefferson Lab (JLab). As a result, this muti-lab computing model tries at best to provide services accessible from anywhere by anyone who is part of the collaboration. While the computing model for the EIC is not finalized, it is anticipated that the computational and storage resources will be made accessible to a wide range of collaborators across the world. The use of federated ID seems to be a critical element to the strategy of providing such services, allowing seamless access to each lab site computing resources. However, providing Federated access to a Federated storage is not a trivial matter and has its share of technical challenges. In this contribution, we focus on the steps we took towards the deployment of a distributed object storage system that integrates with Amazon S3 and Federated ID. We will first cover for and explain the first stage storage solutions provided to the EIC during the detector design phase. Our initial test deployment consisted of Lustre storage using MinIO, hence providing an S3 interface. High Availability load balancers were added later to provide the initial scalability it lacked. Performance of that system will be shown. While this embryonic solution worked well, it had many limitations. Looking ahead, the Ceph object storage is considered a top-of-the-line solution in the storage community - since the Ceph Object Gateway is compatible with the Amazon S3 API out of the box, our next phase will use a native S3 storage. Our Ceph deployment will consist of erasure coded storage nodes to maximize storage potential along with multiple Ceph Object Gateways for redundant access. We will compare performance of our next stage implementations. Finally, we will present how to leverage OpenID Connect with the Ceph Object Gateway's to enable Federated ID access. We hope this contribution will serve the community needs as we move forward with cross-lab collaborations and the need for Federated ID access to distributed compute facilities. [ABSTRACT FROM AUTHOR]
- Published
- 2024
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6. Dynamic scheduling using CPU oversubscription in the ALICE Grid.
- Author
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Bertran Ferrer, Marta, Grigoras, Costin, and Badia, Rosa M.
- Subjects
- *
MOTHERBOARDS , *COMPUTER input-output equipment , *ROCKET payloads , *METHODOLOGY , *MONTE Carlo method - Abstract
The ALICE Grid is designed to perform a realtime comprehensive monitoring of both jobs and execution nodes in order to maintain a continuous and consistent status of the Grid infrastructure. An extensive database of historical data is available and is periodically analyzed to tune the workflows and data management to optimal performance levels. This data, when evaluated in real time, has the power to trigger decisions for efficient resource management of the currently running payloads, for example to enable the execution of a higher volume of work per unit of time. In this article, we consider scenarios in which, through constant interaction with the monitoring agents, a dynamic adaptation of the running workflows is performed. The target resources are memory and CPU with the objective of using them in their entirety and ensuring optimal utilization fairness between executing jobs. Grid resources are heterogeneous and of different generations, which means that some of them have better hardware characteristics than the minimum required to execute ALICE jobs. Our middleware, JAliEn, works on the basis of having at least 2 GB of RAM allocated per core (allowing up to 8 GB of virtual memory when including swap). Many of the worker nodes have higher memory per core ratios than these basic limits and in terms of available memory they therefore have free resources to accommodate extra jobs. The running jobs may have different behaviors and unequal resource usages depending on their nature. For example, analysis tasks are I/O bound while Monte-Carlo tasks are CPU intensive. Running additional jobs with complementary resource usage patterns on a worker node has a great potential to increase its total efficiency. This paper presents the methodology to exploit the different resource usage profiles by oversubscribing the worker nodes with extra jobs taking into account their CPU resource usage levels and memory capacity. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
7. Multicore workflow characterisation methodology for payloads running in the ALICE Grid.
- Author
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Bertran Ferrer, Marta, Grigoras, Costin, and Badia, Rosa M.
- Subjects
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WORKFLOW , *METHODOLOGY , *MOTHERBOARDS , *ROCKET payloads , *MONTE Carlo method - Abstract
For LHC Run3 the ALICE experiment software stack has been completely refactored, incorporating support for multicore job execution. Whereas in both LHC Run 1 and 2 the Grid jobs were single-process and made use of a single CPU core, the new multicore jobs spawn multiple processes and threads within the payload. Some of these multicore jobs deploy a high amount of shortlived processes, in the order of more than a dozen per second. The overhead of starting so many processes impacts the overall CPU utilization of the payloads, in particular its System component. Furthermore, the short-lived processes were not correctly accounted for by the monitoring system of the experiment. This paper presents the developed new methodology for supervising the payload execution. We also present a black box analysis of the new multicore experiment software framework tracing the used resources and system function calls issued by MonteCarlo simulation jobs. Multiple sources of overhead in the lifecycle of processes and threads have thus been identified. This paper describes how the source of each was traced and what solutions were implemented to address them. These improvements have impacted the resource consumption and the overall turnaround time of these payloads with a notable 35% reduction in execution time for a reference production job. We also introduce how this methodology will be used to further improve the efficiency of our experiment software and what other optimization venues are currently under research. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
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8. The LHCb ultra-fast simulation option, Lamarr design and validation.
- Author
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Anderlini, Lucio, Barbetti, Matteo, Capelli, Simone, Corti, Gloria, Davis, Adam, Derkach, Denis, Kazeev, Nikita, Maevskiy, Artem, Martinelli, Maurizio, Mokonenko, Sergei, Siddi, Benedetto G., and Xu, Zehua
- Subjects
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MOTHERBOARDS , *CONSUMERS , *GENERATIVE grammar , *DETECTORS , *SECURITY systems - Abstract
Detailed detector simulation is the major consumer of CPU resources at LHCb, having used more than 90% of the total computing budget during Run 2 of the Large Hadron Collider at CERN. As data is collected by the upgraded LHCb detector during Run 3 of the LHC, larger requests for simulated data samples are necessary, and will far exceed the pledged resources of the experiment, even with existing fast simulation options. The evolution of technologies and techniques for simulation production is then mandatory to meet the upcoming needs for the analysis of most of the data collected by the LHCb experiment. In this context, we propose Lamarr, a Gaudi-based framework designed to offer the fastest solution for the simulation of the LHCb detector. Lamarr consists of a pipeline of modules parameterizing both the detector response and the reconstruction algorithms of the LHCb experiment. Most of the parameterizations are made of Deep Generative Models and Gradient Boosted Decision Trees trained on simulated samples or alternatively, where possible, on real data. Embedding Lamarr in the general LHCb Gauss Simulation framework allows combining its execution with any of the available generators in a seamless way. Lamarr has been validated by comparing key reconstructed quantities with Detailed Simulation. Good agreement of the simulated distributions is obtained with two order of magnitude speed-up of the simulation phase. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
9. Geant4 electromagnetic physics for Run3 and Phase2 LHC.
- Author
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Hahnfeld, Jonas, Ivanchenko, Vladimir, Novak, Mihaly, Pandola, Luciano, and Sawkey, Daren
- Subjects
- *
ELECTRIC windings , *PHYSICS , *MOTHERBOARDS , *ELECTRONS , *ATOMS - Abstract
For the new Geant4 series 11.X, the electromagnetic (EM) physics sub-libraries were revised and reorganized in view of requirements for simulation of Phase-2 LHC experiments. EM physics simulation takes a significant fraction of the available CPU during massive production of Monte Carlo events for LHC experiments. We present the recent evolution of Geant4 EM sublibraries for the simulation of gamma, electron, and positron transport. Updates of other components of EM physics are also discussed. These developments are included in the new Geant4 version 11.1 (December 2022). The most important modifications concern the reorganization of the initialization of EM physics and the introduction of alternative tracking software. These modifications affect the CPU efficiency of any simulation, and CPU savings depend on geometry and physics configuration for the concrete experimental setup. We will discuss several methods: gamma general process, Woodcock tracking, transportation with multiple scattering process, alternative tracking manager, and the new G4HepEm library. These developments provide a basis for the implementation of EM particle transport on co-processors and GPU. We also will present very recent updates in physics processes and in configuration of EM physics. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
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10. CMSSW Scaling Limits on Many-Core Machines.
- Author
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Jones, Christopher and Gartung, Patrick
- Subjects
- *
MOTHERBOARDS , *GRAPHICS processing units , *HADRONS , *EVENT processing (Computer science) , *ELECTRONIC data processing - Abstract
Today the LHC offline computing relies heavily on CPU resources, despite the interest in compute accelerators, such as GPUs, for the longer term future. The number of cores per CPU socket has continued to increase steadily, reaching the levels of 64 cores (128 threads) with recent AMD EPYC processors, and 128 cores on Ampere Altra Max ARM processors. Over the course of the past decade, the CMS data processing framework, CMSSW, has been transformed from a single-threaded framework into a highly concurrent one. The first multithreaded version was brought into production by the start of the LHC Run 2 in 2015. Since then, the framework's threading efficiency has gradually been improved by adding more levels of concurrency and reducing the amount of serial code paths. The latest addition was support for concurrent Runs. In this work we review the concurrency model of the CMSSW, and measure its scalability with real CMS applications, such as simulation and reconstruction, on modern many-core machines. We show metrics such as event processing throughput and application memory usage with and without the contribution of I/O, as I/O has been the major scaling limitation for the CMS applications. [ABSTRACT FROM AUTHOR]
- Published
- 2024
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11. Don’t buy AMD’s new Ryzen 9000 CPUs before knowing these seven key details.
- Author
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YEE, ALAINA
- Subjects
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PRICES , *VIDEO production & direction , *MOTHERBOARDS , *DEEP diving , *DESPAIR - Abstract
AMD's new Ryzen 9000 CPUs offer significant improvements in single-core performance, surpassing Intel's chips in benchmarks like Cinebench R23. However, multi-core performance is lackluster compared to Intel's 14th-gen processors. The performance gains can be optimized by adjusting motherboard settings, such as enabling Precision Boost Overdrive (PBO) and running RAM at a lower voltage. The Ryzen 9000 CPUs demonstrate impressive power efficiency, but gaming performance remains stagnant compared to the previous generation. Despite this, the Ryzen 9000 CPUs are priced lower than their predecessors and undercut Intel's rival chips. [Extracted from the article]
- Published
- 2024
12. Copper recovery by solvent extraction for nanoparticle synthesis from waste motherboards.
- Author
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Martins, Thamiris Auxiliadora Gonçalves, de Moraes, Viviane Tavares, and Espinosa, Denise Crocce Romano
- Subjects
NANOPARTICLE synthesis ,COPPER ,SOLVENT extraction ,ELECTRONIC waste ,METAL nanoparticles ,MOTHERBOARDS ,LEAD - Abstract
Printed circuit boards, which make up part of waste from electrical and electronic equipment, contain elements that can be economically reused, such as copper, silver, gold, and nickel, as well as metals that are harmful to the environment and health, such as lead, mercury, and cadmium. Thus, through recycling this scrap, materials that would otherwise be discarded can be reinserted as secondary raw materials to produce new consumer goods through urban mining. In this context, the synthesis of nanoparticles shows promise as it allows the reinsertion of these materials in the manufacture of new products. Therefore, this study used obsolete computer motherboards as a secondary material to obtain copper to produce nanoparticles of this metal. From a solution based on the leach liquor of this scrap, a purification route using solvent extraction was defined and applied to the real leach liquor. Applying the hydroxyoxime extractant at a dilution of 20% (v/v) in kerosene, A/O of 1/1, 298 K, and 0.25 h of contact during extraction, and stripping in H
2 SO4 (2 M), 298 K, 0.25 h, W/O ratio of 3/1, and two theoretical countercurrent stages, a solution containing more than 95% of the copper in the leach liquor could be obtained with less than 1% of contaminants. From this purified liquor, nanoparticles containing copper and metallic copper oxides and hydroxides were produced, with an average size of 84 nm, at pH 11, 3 h of hot stirring, volume of 0.015 L of ascorbic acid (0.50 M) and 0.015 L of precursor solution (0.03 M Cu), and temperature (343 K). [ABSTRACT FROM AUTHOR]- Published
- 2024
- Full Text
- View/download PDF
13. Hybrid booting with incremental hibernation for the baseboard management controllers.
- Author
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Jang, Joonhyouk, Park, Minho, and Hong, Jiman
- Subjects
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HIBERNATION , *SYSTEM failures , *MOTHERBOARDS - Abstract
The baseboard management controller (BMC) is a specialized processor installed on the motherboard of a server. The BMC operates independently from the server and provides administrators with functionalities for managing the server. In the event of a power outage or system failure causing server downtime, administrators should promptly access the server remotely to identify the cause and take necessary actions. To facilitate this, fast BMC booting is crucial. This paper proposes the concept of hybrid booting with the incremental hibernation technique. The proposed technique periodically stores the state of the BMC and offers various recovery options based on the saved state. It also employs an incremental backup technique for the efficient management of stored states and a hybrid booting technique to guarantee fast booting. In order to evaluate the performance of the proposed technique, the proposed technique is implemented on a development board where the BMC chipset operates and compared to the existing hibernation technique in terms of execution time, disk usage, and booting time. The experimental results show that the proposed technique efficiently enables BMC backup and reduces the booting times. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
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14. MSI and Asus roll out first Intel instability fix for a range of motherboards with 0x129 microcode BIOS
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Intel Corp. ,Motherboards ,Semiconductor industry ,Semiconductor industry ,Motherboard ,Computers - Abstract
Many PC gamers have been waiting with bated breath for a real non-bandaid fix for (https://www.pcgamer.com/hardware/processors/intel-cpu-crashes-what-you-need-to-knowmicrocode-to-blame-but-fix-incoming-this-month-alongside-two-year-extended-warranty/) Intel 13th and 14th Gen instability issues. After months of reported problems, investigations, and [...]
- Published
- 2024
15. ADLINK Launches IMB-C Value Series ATX Motherboards
- Subjects
Adlink Technology Inc. ,Intel Corp. ,Motherboards ,Semiconductor industry ,Semiconductor industry ,Motherboard - Abstract
Key Highlights: * ADLINK Technology Inc. launches IMB-C Value Series of ATX motherboards for budget-sensitive projects. * IMB-C Value Series includes features like 2.5 Gbe, PCIe 4.0, DDR4, and USB [...]
- Published
- 2024
16. Thermaltake Releases the CTE E660 MX Mid Tower Chassis with Support for Hidden-Connector Motherboards
- Subjects
Thermaltake Technology Company Ltd. ,Motherboards ,Computer hardware industry ,Technical education ,Connectors ,Computer industry ,Microcomputers ,Motherboard ,Connector - Abstract
Key Highlights: * Thermaltake launches the CTE E660 MX Mid Tower Chassis in four colors: Black, Snow, Racing Green, and Hydrangea Blue. * The CTE E660 MX supports ASUS and [...]
- Published
- 2024
17. Asus motherboards now support native Windows RGB controls
- Subjects
Motherboard ,Logitech International S.A. ,Motherboards ,Computer peripherals industry - Abstract
As someone who’s https://www.pcworld.com/article/406235/best-gaming-keyboard.html, I think I have the authority to say that most Windows apps created by manufacturers for programming RGB lights suck—especially https://www.pcworld.com/article/1915729/asus-azoth-keyboard-review.html. Which is why it’s great […]
- Published
- 2024
18. Best Mini-ITX motherboards in 2024: My pick from all the mini mobo marvels I've tested
- Subjects
Intel Corp. ,Motherboards ,Semiconductor industry ,Semiconductor industry ,Motherboard ,Computers - Abstract
Fans of small form factor PCs are a dedicated bunch, with the best Mini-ITX motherboards being the absolute superstars of each build. And it's easy to understand why. A mini [...]
- Published
- 2024
19. hXDP: Efficient Software Packet Processing on FPGA NICs.
- Author
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Brunella, Marco Spaziani, Belocchi, Giacomo, Bonola, Marco, Pontarelli, Salvatore, Siracusano, Giuseppe, Bianchi, Giuseppe, Cammarano, Aniello, Palumbo, Alessandro, Petrucci, Luca, and Bifulco, Roberto
- Subjects
- *
NETWORK interface devices , *COMPUTER networks , *MOTHERBOARDS , *ELECTRONIC data processing , *COMPUTERS , *TECHNOLOGICAL innovations - Abstract
The network interface cards (NICs) of modern computers are changing to adapt to faster data rates and to help with the scaling issues of general-purpose CPU technologies. Among the ongoing innovations, the inclusion of programmable accelerators on the NIC's data path is particularly interesting, since it provides the opportunity to offload some of the CPU's network packet processing tasks to the accelerator. Given the strict latency constraints of packet processing tasks, accelerators are often implemented leveraging platforms such as Field-Programmable Gate Arrays (FPGAs). FPGAs can be re-programmed after deployment, to adapt to changing application requirements, and can achieve both high throughput and low latency when implementing packet processing tasks. However, they have limited resources that may need to be shared among diverse applications, and programming them is difficult and requires hardware design expertise. We present hXDP, a solution to run on FPGAs software packet processing tasks described with the eBPF technology and targeting the Linux's eXpress Data Path. hXDP uses only a fraction of the available FPGA resources, while matching the performance of high-end CPUs. The iterative execution model of eBPF is not a good fit for FPGA accelerators. Nonetheless, we show that many of the instructions of an eBPF program can be compressed, parallelized, or completely removed, when targeting a purpose-built FPGA design, thereby significantly improving performance. We implement hXDP on an FPGA NIC and evaluate it running real-world unmodified eBPF programs. Our implementation runs at 156.25MHz and uses about 15% of the FPGA resources. Despite these modest requirements, it can run dynamically loaded programs, achieves the packet processing throughput of a high-end CPU core, and provides a 10× lower packet forwarding latency. [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF
20. FPGAs in Client Compute Hardware.
- Author
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MATTIOLI, MICHAEL
- Subjects
- *
FIELD programmable analog arrays , *COMPUTER input-output equipment , *COMPUTER science research , *MOTHERBOARDS , *GRAPHICS processing units - Abstract
The article explores FPGAs, field-programmable gate arrays, and how they might be used in a variety of applications and industries, including client compute hardware. FGPAs are used in the early stages of hardware design include rapid prototyping, testing, and development. Challenges to using FPGAs are also noted as are benefits.
- Published
- 2022
- Full Text
- View/download PDF
21. BUYER'S GUIDE.
- Subjects
GRAPHICS processing units ,BUYERS' guides ,MOTHERBOARDS ,VALUE (Economics) ,POWER resources ,PRICES - Abstract
This article is a buyer's guide for building a PC based on different budget levels. It provides recommendations for three different builds: budget, mid-range, and advanced. Each build includes specific components such as motherboard, processor, graphics card, cooler, memory, power supply, storage, case, display, keyboard, mouse, and headset. The article offers options for different price points and highlights the features and value of each component. [Extracted from the article]
- Published
- 2024
22. BUYER’S GUIDE.
- Subjects
BUYERS' guides ,MOTHERBOARDS ,PRICES - Abstract
This article is a buyer's guide for building a PC based on different budget levels. It provides recommendations for hardware components such as motherboards, CPUs, GPUs, memory, storage, cases, monitors, keyboards, mice, and headsets. The guide offers options for budget builds, mid-range builds, and advanced builds, catering to different needs and preferences. The article includes specific product recommendations and prices for each component. [Extracted from the article]
- Published
- 2024
23. New Intel Arrow Lake leak alleges no Thunderbolt 5 support for Z890 motherboards
- Author
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McLoughlin, Aleksha
- Subjects
Intel Corp. ,Motherboards ,Semiconductor industry ,Semiconductor industry ,Motherboard ,Science and technology - Abstract
Byline: Aleksha McLoughlin A prominent hardware leaker has alleged that the upcoming Z890 motherboards for Intel Core Ultra 200 will miss out on Thunderbolt 5 support. A prominent hardware leaker [...]
- Published
- 2024
24. New Products -- Technology -- Miscellaneous: BIOS Updates for Intel Motherboards
- Subjects
Intel Corp. ,Motherboards ,Semiconductor industry ,Semiconductor industry ,Motherboard ,Electronics - Abstract
ASUS has released BIOS updates for its Intel 700 and 600 series motherboards, significantly enhancing their capabilities by supporting up to 256GB of DDR5 memory. These motherboards supported less memory, [...]
- Published
- 2024
25. Intel blames aggressive motherboards for high-end CPU crashes
- Subjects
Intel Corp. ,Motherboards ,Motherboard ,Computers - Abstract
There’s an ongoing saga around some of the latest Intel Core desktop CPUs, and how they’re crashing when running 3D games and other resource-intense programs. Intel has previously stated that [...]
- Published
- 2024
26. BIOSTAR AMD AM5 SERIES MOTHERBOARDS TO RECEIVE AGESA PI 1.1.7.0 Patch A BIOS UPDATE
- Subjects
Central processing units ,Motherboards ,Microprocessors ,Computer storage devices ,Computer peripherals industry ,Microprocessor ,Data storage device ,Microprocessor upgrade ,Motherboard - Abstract
BIOSTAR announces a BIOS update for AMD AM5 series motherboards to support next-gen AMD CPUs, incorporating the latest architecture for future-ready performance. Key Highlights: * BIOSTAR is a leading manufacturer [...]
- Published
- 2024
27. Micro-ATX vs. Mini-ITX: Pros and cons for tiny motherboards
- Subjects
Motherboards ,Motherboard ,Computers - Abstract
Mini-ITX motherboards, which measure approximately 6.7 x 6.7 inches, are significantly smaller than Micro-ATX models measuring 9.6 x 9.6 inches. This smaller size makes Mini-ITX ideal for tiny computers that [...]
- Published
- 2024
28. Modeling and Optimization of Cost-Based Hybrid Flow Shop Scheduling Problem using Metaheuristics.
- Author
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Ullah, Wasif, Rashid, Mohd Fadzil Faisae Ab., and Mu'tasim, Muhammad Ammar Nik
- Subjects
PARAPSYCHOLOGISTS ,COMPUTATIONAL intelligence ,METAHEURISTIC algorithms ,MOTHERBOARDS ,ALGORITHMS - Abstract
The cost-based hybrid flow shop (CHFS) scheduling has been immensely studied due to its huge impact on productivity. For any profit-oriented organization, it is important to optimize total production costs. However, few researchers have studied hybrid flow shops (HFS) with total production cost utilization. This paper aims to develop a computational model and test the exploration capability of metaheuristics algorithms while optimizing the CHFS problem. Carlier and Neron defined three hypothetical benchmark problems for computational experiments. The popular optimization algorithms PSO, GA, and ACO were implemented on the CHFS model with ten optimization runs. The experimental results proven that ACO performed well regarding mean fitness value for all benchmark problems. Besides this, CPU time for PSO was very high compared to other algorithms. In the future, other optimization algorithms will be tested for the CHFS model, such as Teaching Learning Based Optimization (TLBO) and the Crayfish Optimization Algorithm (COA). [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
29. Design and Implementation of a Whiteboard Web-Application Using Block Chain Technology.
- Author
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UDO, E. U., ILO, S. F., NNOCHIRI, I. U., and AKUMA, I. U.
- Subjects
INTERACTIVE whiteboards ,PEER-to-peer architecture (Computer networks) ,OPEN source software ,MOTHERBOARDS ,SOFTWARE ecosystems - Abstract
The decentralized whiteboard application using New Kind of Network (NKN) is a real time collaborative application. Decentralized whiteboard uses NKN as a peer-to-peer network layer which is optimized to manage network resources. Decentralized applications create an innovative open-source software ecosystem which is both secure and resilient. Presently, when majority of researchers want to access information on the network, they often face the risk of learning online and some of the challenges they encountered are high bandwidth usage, high CPU usage, physical connectivity issues, malfunctioning devices, domain name server (DNS) issues and interference in the wireless network. The method adopted involves the breaking down of its compositional sub-system in a reverse engineering fashion. The top-down model helps researchers to write the main procedure that names all the major function needed in developing the decentralized whiteboard web-application. The results obtained shows that decentralized whiteboard has given software developers ability to reuse code in various program fragments and also provided better connectivity for their users. In conclusion, it is recommended that institution of higher learning can adapt this as a learning tool to aid a better learning experience in their institutions of higher learning. [ABSTRACT FROM AUTHOR]
- Published
- 2023
30. "Thank you for the terrific party!" – An analysis of Hungarian negative emotive words.
- Author
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Szabó, Martina Katalin, Vincze, Veronika, and Bibok, Károly
- Subjects
SPEECH ,VOCABULARY ,MOTHERBOARDS - Abstract
The term negative emotive word refers to those words that, on their own, i.e. without context, have a semantic content that may be associated with negative emotion, but sometimes they lose it partly or wholly. In the literature negative emotive words are mainly discussed within the group of intensifiers, e.g. awfully good. In the present paper, we call this phenomenon polarity loss. At the same time, there is another use of negative emotive words that is rarely discussed in the literature, namely the case where the examined word, despite its negative semantic content, expresses a positive evaluation of the speaker, e.g. brutális alaplap (lit. 'brutal motherboard' – 'high quality motherboard'). We call this phenomenon polarity shift. The aim here is to thoroughly examine the two different phenomena on the basis of the data of a Hungarian speech corpus HuTongue. After an in-depth analysis of the qualitative and quantitative features of negative emotive words, we propose corresponding ways of their meaning representations, using a lexical pragmatic approach and the concept of enantiosemy. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
31. KAPCHEROP TECHNICAL and VOCATIONAL COLLEGE invites tenders for Supply of Mother boards 1pc
- Subjects
Motherboards ,Motherboard ,News, opinion and commentary - Abstract
KAPCHEROP TECHNICAL and VOCATIONAL COLLEGE, Kenya has invited tenders for Supply of Mother boards 1pc. Tender Notice No: KTVC/PROC/8/2024-2025 Deadline: July 10, 2024 Copyright © 2011-2022 pivotalsources.com. All rights reserved. [...]
- Published
- 2024
32. Linear Address Spaces.
- Author
-
KAMP, POUL-HENNING
- Subjects
- *
COMPUTER architecture , *COMPUTER storage capacity , *OBJECT-oriented methods (Computer science) , *MOTHERBOARDS , *COMPUTERS - Abstract
The article discusses various aspects of computer-related linear physical and virtual addresses, and it mentions Cambridge University’s CHERI computer architecture platform and the computer memory-based difficulties that are associated with translating from linear virtual to linear physical addresses. The ARM and x64 types of central processing units (CPUs) are examined, along with object-oriented computing and the Rational R1000/s400 computer.
- Published
- 2022
- Full Text
- View/download PDF
33. INTEL Z790 REFRESH MOTHERBOARDS.
- Subjects
VALUE (Economics) ,PRICES ,RIP currents ,MOTHERBOARDS ,WIRELESS Internet ,MEMORY - Abstract
This article discusses the release of Intel's 14th Generation processors and the accompanying Z790 refresh motherboards. These motherboards offer improved features and higher memory speeds compared to their predecessors. While they are generally considered the best motherboards of the LGA 1700 generation, they may not be necessary for those who do not require specific features like Wi-Fi 7 or high-speed memory. The article evaluates four different motherboards, highlighting their features, performance, and price. It recommends the Asus TUF Gaming Z790-Pro WiFi for Asus fans or those who need specific expansion slots, the Gigabyte Z790 Aorus Master X for its wide range of features and excellent memory support, the MSI MAG Z790 Tomahawk Max WiFi as a good value option with a powerful VRM and strong I/O capabilities, and the Asrock Z790 Riptide WiFi as a competitor with a similar feature set at a lower price. [Extracted from the article]
- Published
- 2023
34. GEAR of the YEAR.
- Subjects
HEADSETS ,HEADPHONES ,PROJECTORS ,WIRELESS Internet ,MOTHERBOARDS ,CENTRAL processing units - Abstract
The article discusses the best hardware products of 2023, focusing on advancements in CPU technology, screen technology, and notable peripherals. It provides specific product recommendations and includes links to where they can be purchased. The text covers a range of products including headphones, handheld gaming PCs, motherboards, projectors, mini PCs, VR headsets, surround speakers, cases, gaming chairs, video capture devices, homebrew PC alternatives, and Wi-Fi dongles. [Extracted from the article]
- Published
- 2023
35. AMD's monstrous Threadripper 7000 CPUs aim for desktop PC dominance.
- Author
-
HACHMAN, MARK
- Subjects
- *
VIDEO editing , *CENTRAL processing units , *PRICE marks , *SOCIAL dominance , *MOTHERBOARDS , *ZEN Buddhism - Abstract
AMD has announced the release of three new Ryzen Threadripper 7000-series chips, with up to 64 cores and 128 threads, and the option of a Pro-class Threadripper 700 WX series with 96 cores and 192 threads. These chips are designed for video editing and content creation and are optimized for such tasks. They feature AMD's Zen 4 architecture, higher core counts, faster boost frequencies, and PCI Express 5.0. The new chips require new motherboards and consume 350W of power. They are available for purchase as of November 21, but they come with a high price tag. [Extracted from the article]
- Published
- 2023
36. Intel Core i7-14700K and Core i9-14900K: More features, mild speed bump.
- Author
-
YEE, ALAINA
- Subjects
- *
BUDGET , *ARTIFICIAL intelligence , *MOTHERBOARDS , *COMPUTER software , *INTEL microprocessors - Abstract
Intel has released its 14th generation of desktop CPUs, called Raptor Lake processors. The lineup includes six chips, with two variants each of the Core i9, Core i7, and Core i5 parts. The flagship Core i9-14900K offers a small increase in clock speed and is cheaper than the previous Core i9-13900K. The Core i7-14700K stands out with four additional efficiency cores and performs well in content creation tasks. The processors are compatible with existing motherboards and come with AI software features for easier overclocking. However, they do not offer significant improvements in power efficiency compared to the previous generation. The choice between Intel and AMD processors depends on individual circumstances and budget constraints. [Extracted from the article]
- Published
- 2023
37. BUYER'S GUIDE.
- Subjects
MOTHERBOARDS ,INTEL 432 (Microprocessor) - Abstract
The article reviews several personal computer (PC) related products including the B660M Pro RS, motherboard from ASRock; the Laminar RM1 (included with CPU) cooler from Intel; and the S2722DGM display from Dell.
- Published
- 2023
38. BIOSTAR AMD 400 AND 500 SERIES MOTHERBOARDS NOW COMPATIBLE WITH AMD RYZEN 5000 SERIES PROCESSORS
- Subjects
Motherboards ,Motherboard - Abstract
BIOSTAR announces compatibility of its AMD AM4 series motherboards with the latest AMD Ryzen 5000 series processors. AMD has introduced four new processors in the Ryzen 5000 Series. The Ryzen [...]
- Published
- 2024
39. Thermaltake Reveals the Ceres 330 TG ARGB Mid Tower Chassis, Compatible with the Latest ATX Hidden-Connector Motherboards
- Subjects
Thermaltake Technology Company Ltd. ,Motherboards ,Computer hardware industry ,Computer industry ,Motherboard - Abstract
Thermaltake has launched the Ceres 330 TG ARGB Mid Tower Chassis, which is compatible with the latest ATX hidden-connector motherboards. The chassis features a 55% perforated panel design for optimal [...]
- Published
- 2024
40. ADLINK Launches New IMB-C Value Series ATX Motherboards
- Subjects
Adlink Technology Inc. ,Intel Corp. ,Motherboards ,Motherboard ,Telecommunications industry - Abstract
(PRWeb) - New series of ATX motherboards bring quality, affordability, and reliable performance to value-conscious users SAN JOSE, Calif., July 18, 2024 /PRNewswire-PRWeb/ -- Summary: Cost-effective ATX motherboards optimized for [...]
- Published
- 2024
41. ADLINK Launches New IMB-C Value Series ATX Motherboards
- Subjects
Adlink Technology Inc. ,Intel Corp. ,Motherboards ,Semiconductor industry ,Semiconductor industry ,Motherboard ,Business ,News, opinion and commentary - Abstract
New series of ATX motherboards bring quality, affordability, and reliable performance to value-conscious users SAN JOSE, Calif., July 18, 2024 /PRNewswire-PRWeb/ -- Summary: Cost-effective ATX motherboards optimized for budget, with [...]
- Published
- 2024
42. THE BUILDS.
- Subjects
SOLID state drives ,CLOUD storage ,PRICES ,MOTHERBOARDS ,AIR flow - Abstract
This article provides information on the current state of the computer parts market and offers recommendations for building AMD and Intel systems at various price points. The AMD system includes the Ryzen 5 7600 chip, an AM5 motherboard, and DDR5 memory, while the Intel system features the Core i5-12400F chip and an ASUS Prime B760-Plus motherboard. Both builds include a Corsair 4000D Airflow case, a Thermaltake Toughpower GX2 80+ Gold PSU, and SSD storage. The article also discusses market changes, such as the release of new AMD and Intel chips, as well as the growing popularity of cloud storage and affordable M.2 and SSD drives. The text provides detailed information on the prices of computer components from different brands, ranging from $951 to $3,358, depending on the chosen components and brands. [Extracted from the article]
- Published
- 2024
43. ASROCK IS READY WITH A COMPLETE LINEUP OF NEXT GENERATION MOTHERBOARDS
- Subjects
Intel Corp. ,Motherboards ,Semiconductor industry ,Semiconductor industry ,Motherboard ,Science and technology - Abstract
Asrock didn't seem to get the memo from either AMD or Intel, and it proudly showed off a complete range of next-generation AMD X870 and for now unnamed Intel motherboards. [...]
- Published
- 2024
44. Shared-Semaphored Cache Implementation for Parallel Program Execution in Multi-Core Systems.
- Author
-
Milik, Adam and Walichiewicz, Michał
- Subjects
- *
MULTICORE processors , *SCHEDULING , *COMPILERS (Computer programs) , *MOTHERBOARDS , *COMPUTER interfaces - Abstract
The paper brings forward an idea of multi-threaded computation synchronization based on the shared semaphored cache in the multi-core CPUs. It is dedicated to the implementation of multi-core PLC control, embedded solution or parallel computation of models described using hardware description languages. The shared semaphored cache is implemented as guarded memory cells within a dedicated section of the cache memory that is shared by multiple cores. This enables the cores to speed up the data exchange and seamlessly synchronize the computation. The idea has been verified by creating a multi-core system model using Verilog HDL. The simulation of task synchronization methods allows for proving the benefits of shared semaphored memory cells over standard synchronization methods. The proposed idea enhances the computation in the algorithms that consist of relatively short tasks that can be processed in parallel and requires fast synchronization mechanisms to avoid data race conditions. [ABSTRACT FROM AUTHOR]
- Published
- 2023
- Full Text
- View/download PDF
45. Add Raspberry Pi GPIO to your PC.
- Author
-
Bedford, Mike
- Subjects
RASPBERRY Pi ,PERSONAL computers ,DATA acquisition systems ,MOTHERBOARDS ,COMPUTER interfaces - Abstract
The article offers suggestions to add Raspberry Pi general purpose input/output (GPIO) to personal computers (PC). It mentions products that do this are generally referred to as data acquisition, or DAQ, devices, and connect via USB or occasionally plug into the motherboard. It also mentions Ryanteck RTk.GPIO is available from various sources in several counties and facts should allow Raspberry Pi projects or HATs to be transferred to a PC.
- Published
- 2023
46. SkyCore: Moving Core to the Edge for Untethered and Reliable UAV-Based LTE Networks.
- Author
-
Moradi, Mehrdad, Sundaresan, Karthikeyan, Chai, Eugene, Rangarajan, Sampath, and Mao, Z. Morley
- Subjects
- *
DRONE aircraft , *LONG-Term Evolution (Telecommunications) , *COMPUTER software , *PROTOTYPES , *MOTHERBOARDS - Abstract
The advances in unmanned aerial vehicle (UAV) technology have empowered mobile operators to deploy LTE (long-term evolution) base stations (BSs) on UAVs and provide ondemand, adaptive connectivity to hotspot venues as well as emergency scenarios. However, today's evolved packet core (EPC) that orchestrates LTE's radio access network (RAN) faces fundamental limitations in catering to such a challenging, wireless, and mobile UAV environment, particularly in the presence of multiple BSs (UAVs). In this work, we argue for and propose an alternate, radical edge EPC design, called SkyCore that pushes the EPC functionality to the extreme edge of the core network--collapses the EPC into a single, lightweight, self-contained entity that is colocated with each of the UAV BS. SkyCore incorporates elements that are designed to address the unique challenges facing such a distributed design in the UAV environment, namely the resource constraints of UAV platforms, and the distributed management of pronounced UAV and UE mobility. We build and deploy a fully functional version of SkyCore on a two-UAV LTE network and showcase its (i) ability to interoperate with commercial LTE BSs as well as smartphones, (ii) support for both hotspot and stand-alone multi-UAV deployments, and (iii) superior control and data plane performance compared to other EPC variants in this environment. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
47. Enabling AI at the Edge with XNOR-Networks.
- Author
-
Rastegari, Mohammad, Ordonez, Vicente, Redmon, Joseph, and Farhadi, Ali
- Subjects
- *
ARTIFICIAL intelligence , *CONVOLUTIONAL neural networks , *ARTIFICIAL neural networks , *MOTHERBOARDS - Abstract
In recent years we have seen a growing number of edge devices adopted by consumers, in their homes (e.g., smart cameras and doorbells), in their cars (e.g., driver assisted systems), and even on their persons (e.g., smart watches and rings). Similar growth is reported in industries including aerospace, agriculture, healthcare, transport, and manufacturing. At the same time that devices are getting smaller, Deep Neural Networks (DNN) that power most forms of artificial intelligence are getting larger, requiring more compute power, memory, and bandwidth. This creates a growing disconnect between advances in artificial intelligence and the ability to develop smart devices at the edge. In this paper, we present a novel approach to running state-of-the-art AI algorithms at the edge. We propose two efficient approximations to standard convolutional neural networks: Binary-Weight-Networks (BWN) and XNOR-Networks. In BWN, the filters are approximated with binary values resulting in 32× memory saving. In XNOR-Networks, both the filters and the input to convolutional layers are binary. XNOR-Networks approximate convolutions using primarily binary operations. This results in 58× faster convolutional operations (in terms of number of the high precision operations) and 32× memory savings. XNORNets offer the possibility of running state-of-the-art networks on CPUs (rather than GPUs) in real-time. Our binary networks are simple, accurate, efficient, and work on challenging visual tasks. We evaluate our approach on the ImageNet classification task. The classification accuracy with a BWN version of AlexNet is the same as the full-precision AlexNet. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
48. MSI says motherboards supporting 256GB RAM are coming soon
- Subjects
Memory (Computers) ,Motherboards ,Semiconductor memory ,Motherboard ,Computers - Abstract
You can never have too much memory, in the same sense that you can never have too much toilet paper. If this philosophy appeals to you, you might want to [...]
- Published
- 2023
49. BIOSTAR SILVER SERIES MOTHERBOARDS FOR INTEL CORE I7-14700K PROCESSOR
- Subjects
Intel Corp. ,Motherboards ,Semiconductor industry ,Computer storage devices ,Computer peripherals industry ,Semiconductor industry ,Data storage device ,Motherboard - Abstract
BIOSTAR, a leading manufacturer of motherboards, graphics cards, and storage devices, has introduced SILVER series motherboards that are compatible with the latest Intel Core i7-14700K Raptor Lake-S Refresh processor. The [...]
- Published
- 2023
50. BIOSTAR INTRODUCES THE BEST MOTHERBOARDS TO POWER THE BEEFY INTEL CORE i9-14900K PROCESSOR
- Subjects
Intel Corp. ,Memory (Computers) ,Motherboards ,Semiconductor industry ,Semiconductor industry ,Semiconductor memory ,Motherboard - Abstract
BIOSTAR, a leading manufacturer of motherboards, introduces its best motherboards, including the Z790 VALKYRIE, Z790A-SILVER, Z690A VALKYRIE, and Z690A-SILVER, which are optimized for the Intel Core i9-14900K processor. These motherboards [...]
- Published
- 2023
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