1. All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter
- Author
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Tero Tikka, Jussi Ryynanen, Yury Antonov, Kari Stadius, Department of Micro and Nanosciences, Aalto-yliopisto, and Aalto University
- Subjects
Engineering ,PVT calibration ,Monitoring ,optimisation ,Serial communication ,Phase (waves) ,Phase locked loops ,power saving ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,Clock generator ,Delays ,ADPLL phase accumulator speed optimization ,Clocks ,all-digital phase-locked loop ,business.industry ,clock generator ,CMOS ,loop type changing criteria ,Transmitter ,phase digitization process ,CMOS digital integrated circuits ,calibration ,CMOS integrated circuits ,Transmitters ,digital phase locked loops ,size 40 nm ,Phase-locked loop ,Loop (topology) ,MIPI M-PHY serial link transmitter ,Pipeline processing ,Accumulator (computing) ,business ,frequency 1.2 GHz to 5.8 GHz - Abstract
This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.
- Published
- 2015
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