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We propose a main mechanism of large valley splitting experimentally observed at the interface of buried oxide (BOX)/silicon-on-insulator (SOI) structures. Silicon metal-oxide-semiconductor field effect transistors fabricated on a SIMOX (001) substrate, which is a kind of the SOI substrate, that is annealed at high temperatures for a long time are known to exhibit large valley splitting, but the origin of this splitting has long been unknown. Extended zone effective-mass approximation predicts that strain significantly affects valley splitting. In this study, we analyzed valley splitting based on this theory and found that the shear strain along [110] of approximately 5% near the BOX interface is a promising source for large valley splitting. [ABSTRACT FROM AUTHOR]

This paper provides a comprehensive study of the impact of the gate recess depth (RD) on the GaN-on-Si MOS-HEMTs DC performances. IDS = f(VGS) and IDS = f(VDS) measurements are conducted at 25 and 150 °C, respectively, in forward and blocking modes. The gate recessed depth (50, 150, and 350 nm) is modulated by adjusting the plasma etching time, which is a critical step for improving the dielectric/GaN interface quality and the gate channel electron mobility. Three distinct regions can be defined separately: the bottom, the sidewall, and the corner region being the junction between the two previous regions. To assess the impact of gate recessed depth (RD) on the several mobilities around the gate cavity first, we applied our previous methodology allowing us to extract the bottom (μbot) and the entire sidewall region mobility (μT), without distinction from the corner. The mobility of the transverse region was found surprisingly to increase with deeper RD. To gain insight into the impact of the RD on this transverse section, a new extraction methodology is proposed to extract separately the gate corner (μcorner) and sidewall (μSW) mobility. These extractions show that the corner mobility is found to be reduced compared to the sidewall one (μcorner < μSW) evidencing the different weighting contributions over the transverse mobility. Moreover, these mobilities are found to be more degraded compared to the bottom one, highlighting the different contributions on the on-state resistance (RON). Indeed, the on-state resistance is lowered with the shallower RD due to the reduced sidewall resistance contribution (lower sidewall length) and despite the incremental contribution of the bottom resistance (larger effective gate length). However, the shallower RD shows an increase in the drain–source leakage current in reason of a lower gate electrostatic control. Technology Computer Aided Design (TCAD) simulations of the three RD morphologies are carried out to validate the experimental trends and the proposed methodology. [ABSTRACT FROM AUTHOR]

The study of interface states and bulk traps and their connection to device instability is highly demanded to achieve reliable β-Ga2O3 metal-oxide-semiconductor (MOS) devices. However, a comprehensive analysis of the capture/emission behavior of interface states and bulk traps can be challenging due to widespread time constant distribution. In this study, using capacitance transient measurement tools, trap states of the ZrO2/β-Ga2O3 MOS gate stack were explicitly investigated, particularly its bias- and temperature-dependent relaxation kinetics. As forward bias is enlarged, it is observed that the interface state density (Dit) increases by 12.6%. Two bulk traps with discrete levels identified as 0.43 eV (E1) and 0.74 eV (E2) below the conduction band minimum were extracted by deep-level transient spectroscopy. It is further revealed that the emission processes of E1 and E2 are thermally enhanced, while the capture processes remain insensitive to temperature. The electric-field dependence of E1 indicates that the dominant mechanism follows the rule of Poole–Frenkel emission. The capacitance–voltage (C–V) hysteresis deteriorated at a higher forward bias due to the higher trap density and increased population of trapped charges. These findings provide an important framework for future device optimization to improve the reliability and performance of β-Ga2O3 MOS devices. [ABSTRACT FROM AUTHOR]

In recent years, neural networks have achieved phenomenal success across a wide range of applications. They have also proven useful for solving differential equations. The focus of this work is on the Poisson–Boltzmann equation (PBE) that governs the electrostatics of a metal–oxide–semiconductor capacitor. We were motivated by the question of whether a neural network can effectively learn the solution of PBE using the methodology pioneered by Lagaris et al. [IEEE Trans. Neural Netw. 9 (1998)]. In this method, a neural network is used to generate a set of trial solutions that adhere to the boundary conditions, which are then optimized using the governing equation. However, the challenge with this method is the lack of a generic procedure for creating trial solutions for intricate boundary conditions. We introduce a novel method for generating trial solutions that adhere to the Robin and Dirichlet boundary conditions associated with the PBE. Remarkably, by optimizing the network parameters, we can learn an optimal trial solution that accurately captures essential physical insights, such as the depletion width, the threshold voltage, and the inversion charge. Furthermore, we show that our functional solution can extend beyond the sampling domain. [ABSTRACT FROM AUTHOR]

In this study, the effects of Al2O3 and Y2O3 passivation layers on Ge substrates are investigated to enhance the thermal stability of Ge-based devices. Using X-ray photoelectron spectroscopy, we analyze the growth characteristics and chemical composition of Al2O3, Y2O3, and ZrO2 on Ge. The changes in the crystallinity of ZrO2 on different substrates of Ge, Al2O3/Ge, and Y2O3/Ge configurations are observed via X-ray diffraction. Material properties, including capacitance, flat band voltage shift (ΔVFB), oxide charge trap (Not), interface defect density (Dit), and leakage current, are analyzed using the metal–oxide–semiconductor capacitor, with a particular focus on their electrical characteristics. Additionally, we investigate whether the passivation mechanisms of each material are more suitable for enhancing thermal stability. Overall, this study provides insight into the role of passivation layers in improving the interface and thermal stability of Ge-based devices, offering valuable contributions to the advancement of semiconductor technology. [ABSTRACT FROM AUTHOR]

This paper reports the structural, optical, and electrical properties of dysprosium oxide (Dy2O3) deposited by electron beam deposition under ultra-vacuum on porous p-type GaAs. A porous GaAs layer was produced by electrochemical anodic etching of a (100)-heavily doped p-type GaAs substrate in hydrofluoric acid (HF) and ethanol C2H5OH solution. The surface topography of the elaborated Dy2O3 layer was determined based on atomic force microscopy (AFM) images. AFM studies showed that the structure and roughness of the Dy2O3 layer were strongly dependent on the roughness and surface of porous GaAs. Dy2O3 is polycrystalline and exhibits a cubic crystalline structure, as confirmed by x-ray diffraction (XRD) analysis. The optical properties of Dy2O3/p-porous GaAs were analyzed using various techniques including ellipsometry and photoluminescence (PL) to obtain information on surface and interface quality, bandgap, optical constants, dielectric constant, and thickness. The photoluminescence (PL) spectra revealed an intense peak at 835 nm and additional weak emission peaks at 473 nm and 540 nm, respectively. The observed intense peak can be directly attributed to the interband recombination process of free carriers in the direct bandgap of p-GaAs, while the weak emission peaks at 473 nm and 540 nm correspond to 4F9/2-6H15/2 and 4F9/2-6H13/2 transitions, respectively. In the spectral region of 350 nm to 500 nm, the average thickness of the Dy2O3 layer was determined to be 11 nm. The electrical properties of the (Co/Au)/Dy2O3/p-porous GaAs metal–oxide–semiconductor (MOS) capacitor were investigated via capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements in the temperature range of 100–400 K and frequency range of 50 Hz to 1 MHz, respectively. The experiments demonstrated that both capacitance and conductance were influenced by temperature and frequency. Additionally, the effect of temperature on interface state density (Nss) was studied, which showed that an increase in temperature led to a decrease in the interface state density (Nss) of the (Co/Au)/Dy2O3/p-porous GaAs (MOS) capacitor, as calculated by the Hill–Coleman method. The mean values of Nss for the (Co/Au)/Dy2O3/p-porous GaAs (MOS) capacitor were determined to be approximately 1012 eV−1 cm−2, making it suitable for electronic device applications. The lower values of Nss can be attributed to a low amount of local defect microstructure at the Dy2O3/p-porous GaAs interface due to the incorporation of the Dy2O3 layer into the porous GaAs. The electrical conductivity of the (Co/Au)/Dy2O3/p-porous GaAs (MOS) capacitor was studied using impedance spectroscopy in the frequency range from 50 Hz to 1 MHz at temperatures ranging from 80 K to 450 K. At low frequencies, the conductivity of alternating current (σAC) remained nearly constant, whereas at high frequencies, it increased rapidly, representing σDC and σAC, respectively. The Arrhenius plot of σAC shows two distinct slopes corresponding to two activation energies, 35 MeV and 10 MeV, in the chosen temperature range. [ABSTRACT FROM AUTHOR]

The relationship between the electrical properties and the carrier trap properties of the SiO2/GaN metal–oxide–semiconductor (MOS) capacitors was investigated using electrical measurements and deep level transient spectroscopy (DLTS). The capacitance–voltage (C–V) measurement showed that the frequency dispersion of the C–V curves became smaller after an 800 °C annealing in O2 ambient. DLTS revealed that before the annealing, the interface trap states, in a broad energy range above the midgap of GaN, were detected with the higher interface state density at around 0.3 and 0.9 eV below the conduction band minimum (EC) of GaN. Moreover, the oxide trap states were formed at around 0.1 eV below the EC of GaN, plausibly indicating a slow electron trap with a tunneling process. Although both trap states affect the electrical reliability and insulating property of the SiO2/GaN MOS capacitors, they were found to drastically decrease after the annealing, leading to the improvement of the electrical properties. [ABSTRACT FROM AUTHOR]

The reliability issues in silicon carbide (SiC)-based devices with gate dielectric formed through heat oxidation are significant factors limiting their application in power devices. Aluminum oxide (Al2O3) was chosen as a high-k material to form the gate oxide layer on top of a SiC substrate. Atomic layer deposition (ALD) was used to fabricate an Al2O3/4H-SiC heterostructure, and the quality of the ALD Al2O3 layer was examined by XPS and electrical experiments. The XPS analysis suggests that the created heterojunction is a type-I heterojunction with ΔEC = 1.89 eV and ΔEV = 1.83 eV. Metal-insulated semiconductor structures with upper and lower Al electrodes were prepared for investigating leakage current and breakdown voltage characteristics. The leakage current density and breakdown electric field of an MOS capacitor structure with an Al2O3/4H-SiC heterojunction are ∼10−10 A/cm2 and 9.3 MV/cm, respectively. The interfacial defect density (Dit) near the conduction band of the MOS capacitive structure with the SiC substrate is 1.44 × 1012 eV−1 cm−2, while the interface charge (Neff) of the oxide layer of this sample can also be controlled at a level of 1011 cm−2. The Al2O3/SiC structure fabricated in this work exhibits superior electrical performance compared to the heterostructure based on the Si substrate and other relevant heterostructures documented in previous studies. [ABSTRACT FROM AUTHOR]

Nanoengineering polar oxide films have attracted great attention in energy storage due to their high energy density. However, most of them are deposited on thick and rigid substrates, which is not conducive to the integration of capacitors and applications in flexible electronics. Here, an alternative strategy using van der Waals epitaxial oxide dielectrics on ultra‐thin flexible mica substrates is developed and increased the disorder within the system through high laser flux. The introduction of defects can efficiently weaken or destroy the long‐range ferroelectric ordering, ultimately leading to the emergence of a large numbers of weak‐coupling regions. Such polarization configuration ensures fast polarization response and significantly improves energy storage characteristics. A flexible BiFeO3‐BaTiO3 (BF‐BT) capacitor exhibits a total energy density of 43.5 J cm−3 and an efficiency of 66.7% and maintains good energy storage performance over a wide temperature range (20–200 °C) and under large bending deformation (bending radii ≈ 2 mm). This study provides a feasible approach to improve the energy storage characteristics of dielectric oxide films and paves the way for their practical application in high‐energy density capacitors. [ABSTRACT FROM AUTHOR]

Tetragonal ZrO2 high-k material as the dielectric layer of dynamic random access memory (DRAM) capacitors faces bulk defect related leakage current, which is one of the main obstacles to the down-scaling of DRAM devices. Boron and hydrogen impurities are known to be responsible for leakage current degradation and are hard to be removed in DRAM capacitors. However, the defect origins of boron and hydrogen leakage current are still puzzling, and corresponding suppression methods are urged. In this work, the properties of boron and hydrogen impurities in tetragonal ZrO2 are investigated using first-principles calculations, and defect types such as boron and hydrogen interstitials are discovered to have detrimental defect levels related to leakage current. Based on the discovery, a chlorine co-doping approach that can passivate detrimental defects by forming defect complexes is further proposed. By introducing level repulsion due to coupling between defect states, defect levels of passivated defect complexes are moved out of the region of leakage current contribution. Thus, bulk defect related leakage current in tetragonal ZrO2 based DRAM capacitors can be effectively suppressed without device structure modification, and a broad vista is opened for next-generation DRAM devices. [ABSTRACT FROM AUTHOR]

The adverse effects of leakage currents and short channel effects (SCE) on mobility degradation in CMOS technology below the 100-nanometer scale. To mitigate these effects, the paper suggests using material engineering techniques to improve the mobility of charge carriers and control SCE effects. Specifically, the switching characteristics of a dual-gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) are enhanced by stacking the gate with various oxide layers including SiO2, HfO2, and TiO2. These oxide layers possess a range of permittivity capabilities from low to high. By combining different oxide layers the proposed device aims to improve its performance. To evaluate the performance of the proposed device we have employ simulation models such as CONMOB (Concentration Dependent Mobility), AUGER (Auger Recombination), and FLMOB (Field Dependent Mobility). These techniques help to obtain the accurate and reliable simulation results. We have utilized the parameters like drain current, transconductance, electric field, ION, IOFF, and ION/IOFF and simulate them using the Silvaco TCAD tool. The analysis of these parameters are discussed in the paper we have highlighted the compatibility of the proposed DGMOSFET device for low-power applications. In this paper, we have focus on the improving the switching characteristics of a dual-gate MOSFET by utilizing gate stacks with various oxide layers. The proposed device is evaluated through simulations using concentration-dependent mobility, Auger recombination, and field-dependent mobility techniques. The results indicate that the device is suitable for low-power applications. [ABSTRACT FROM AUTHOR]

The relationship between the dielectric constant and leakage current of materials often exhibits a negative correlation. However, to sustain Moore's Law, the semiconductor industry necessitates novel materials that simultaneously possess a high dielectric constant and low leakage current, meeting the shrinking demands of electronic components. In this study, a high-performance hafnium-based thin film capacitor achieved through the collaborative effects of bottom electrode engineering and ion doping. Tungsten (W) as the bottom electrode, with its chemically inert nature and low thermal expansion coefficient, proves advantageous in improving interface quality and promoting the generation of the high- k phase in HfO 2. Concurrently, yttrium (Y) ion doping contributes to stabilizing the high- k phase of HfO 2 , reducing non-lattice oxygen, and enhancing the disorderliness of the dielectric thin film. By synergistically integrating these factors, the hafnium-based thin film capacitor achieves a high dielectric constant of 36.6 while maintaining minimal leakage current (Electric field ∼ 6 MV/cm, J ∼ 10−8 A/cm2) and a high charge storage capacity (U rec ∼ 104.4 J/cm³). These research findings open a promising pathway for the development of novel hafnium-based materials with broad applicability and exceptional dielectric performance. [ABSTRACT FROM AUTHOR]

The unique semiconducting characteristics of 2D materials, such as transition metal dichalcogenides (TMDs), have drawn significant interest in the field of electronic devices. However, the dependence of the device performance on the electrical properties of electrochemically exfoliated TMD nanoflakes remains unclear. In this study, the intrinsic electrical properties of diverse electrochemically exfoliated TMD nanoflakes are investigated and their applications in fully solution‐processed 2D electronics are explored. The study reveals that MoSe2 and WS2 nanoflakes are suitable candidates with moderate electron concentrations of 5.7 × 1012 and 2.5 × 1012 cm−2, respectively. These moderate electron concentrations enable a low off‐state current and high on‐state current, leading to a large on–off ratio (> 106) for the fabricated transistors. Furthermore, moderate annealing can increase the mobility by one order of magnitude by reducing the contact resistance and improving charge transport. Additionally, the trap density is significantly reduced, leading to an improved stability. Finally, fully solution‐processed 2D complementary inverters with a high voltage gain of 60 are demonstrated. This study contributes to a growing understanding of the properties of 2D materials in terms of transistor performances and promotes the development of solution‐processed devices applicable in next‐generation electronics. [ABSTRACT FROM AUTHOR]

This paper proposes a unique sensor for detecting total ionizing dose (TID) on metal–oxide–semiconductor (MOS) devices. The proposed capacitive radiation sensor is based on commercial 180 nm complementary metal-oxide semiconductor (CMOS) technology. The sensor parameters of 180 nm length (L) and 20 nm oxide thickness (TOX) have been finalized based on simulation and mathematical analysis. Low and high radiation doses ranging from 100 rad to 1 Mrad are used to characterize it. The sensor's sensitivity for 0–10 krad is 20 mV/krad, 10 krad–100 krad is 3.9 mV/krad, and 100 krad–1 Mrad is 0.6 mV/krad when threshold shift is considered into account. Analysis of fixed oxide charge and interface trap charge generation due to ionizing radiation is done. Because interface traps are crucial to device performance, this device is evaluates using traps between 1 E06 cm−3 and 1 E14 cm−3 for realistic performance. Every interface trap exhibits a threshold voltage (VT) shift. Visual technology computer-aided design (TCAD) simulator was used to build, study, and evaluate a capacitive radiation sensor that might be used as a dosimeter for TID monitoring. [ABSTRACT FROM AUTHOR]

In this study, we report on the direct-current (DC) and frequency characteristics of split-gate heterostructure field-effect transistors (HFETs) with different split-gate lengths. The split-gate HFET contains two distinct operating parts, the large and the small transconductance parts. The split-gate HFET has a current cutoff frequency ( f T ) of 814 MHz and a maximum oscillation frequency ( f max ) of 18.8 GHz in the large transconductance part. Meanwhile, in the small transconductance part, there is a higher unilateral power gain of f max = 2 7. 7 GHz. Also, the split-gate HFET exhibits a voltage gain greater than 1 (0 dB) at both DC and frequencies. Additionally, compared to the large transconductance part, the small transconductance part of the split-gate HFET presents a 53.5% reduction in DC power consumption and a larger input signal voltage range. Split-gate HFETs can be used as conventional power amplifiers in the large transconductance part and are also suitable as low-power voltage amplifiers in the small transconductance part. [ABSTRACT FROM AUTHOR]

We investigated the effects of gate bias regarding the degradation of electrical characteristics during gamma irradiation. Moreover, we observed the punch through failure of 1.2 kV rated commercial Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) due to the influence of gate bias. In addition, the threshold voltage (VT) and on-resistance (Ron) of the SiC MOSFETs decreased significantly by the influence of gate bias during gamma irradiation. We extracted the concentration of carriers and fixed charge (QF) in oxide using N-type SiC MOS capacitors and Transmission Line Measurement (TLM) patterns to analyze the effects of gamma irradiation. The Total Ionizing Dose (TID) effect caused by high-energy gamma-ray irradiation resulted in an increase in the concentration of holes and QF in both SiC and oxide. To analyze the phenomenon for increment of hole concentration in the device under gate bias, we extracted the subthreshold swing of SiC MOSFETs and verified the origin of TID effects accelerated by the gate bias. The QF and doping concentration of p-well values extracted from the experiments were used in TCAD simulations (version 2022.03) of the planar SiC MOSFET. As a result of analyzing the energy band diagram at the channel region of 1.2 kV SiC MOSFETs, it was verified that punch-through can occur in 1.2 kV SiC MOSFETs when the gate bias is applied, as the TID effect is accelerated by the gate bias. [ABSTRACT FROM AUTHOR]

As diamond possesses only deep dopants, certain conventional physics and characterization methods are not applicable to diamond devices, owing to the explicit or implicit assumption of shallow dopants. To resolve this limitation, the capacitance–voltage (C–V) characteristics of metal–insulator–semiconductor (MIS) capacitors formed on a semiconductor substrate with deep and compensating dopants were successfully formulated. Based on these equations, methods for accurately estimating the MIS capacitor properties were developed and validated through their application in the analysis of an actual MIS capacitor formed on a boron-doped hydrogen-terminated diamond substrate. The high-frequency C–V characteristic of the capacitor exhibited a prominent dip specific to deep dopants. However, the dip depth was considerably shallower than theoretically expected. This C–V characteristic was accurately reproduced theoretically, assuming the presence of a surficial diamond layer that contains acceptors with an activation energy of 0.23 eV, which is less than the value 0.37 eV for boron, and has a thickness of the extrinsic Debye length (40 nm in this study) or larger. The insulator charge of the MIS capacitor was estimated as −4.6 × 1012 cm−2 in units of electronic charge, which is sufficiently large to induce two-dimensional hole gas. The interface-state density was 1.4 × 1012 cm−2 eV−1 for interface-state energies of 0.3–0.5 eV above the valence band maximum. Hence, the proposed methodology and the possible presence of the reduced activation energy layer will guide the development of diamond-based devices. [ABSTRACT FROM AUTHOR]

Electrically detected magnetic resonance (EDMR) is arguably the most sensitive method available to study electrically active point defects in semiconductor devices. Most EDMR studies have utilized spin-dependent recombination current and, thus, require p–n junctions or a photoconductive structure. Some time ago, Chen and Lang proposed and demonstrated EDMR via spin-dependent deep level transient spectroscopy in metal–oxide–semiconductor capacitors. We report on a similar and significantly simpler technique: spin-dependent transient spectroscopy (SDTS). We show that the sensitivity of this technique is independent of the resonance field and frequency. Through capacitance–voltage analysis, combined with our SDTS results, this technique can (crudely) provide information about the density of states of defects with a broad distribution of energy levels. In addition, we show that SDTS can be readily adapted to near-zero-field magnetoresistance effect measurements. [ABSTRACT FROM AUTHOR]

This study explores the optimization of a hetero-dielectric tunnel field-effect transistor (HDTFET) structure to improve device performance. By incorporating a high-k oxide pocket in a portion of the source-side gate insulator, a local minimum in the conduction band edge is induced at the source-channel interface. This technique leads to improved tunneling rates and increased current handling capability. The simulation analysis focuses on optimizing the position and dimension of the high-k dielectric pocket to enhance key device characterization metrics such as ON-state current (I ON), ON-to-OFF-state current ratio (I ON / I OFF), subthreshold swing (SS), and cutoff frequency (f T). The resulting optimized design for a 30 nm-channel length involves a pocket shift of 1 nm and a pocket length of 12 nm. This configuration achieves a remarkable ON current of 55 µA/µm, which is 30 times higher than that of a conventional TFET. Importantly, other analog performance parameters remain unaffected, with f T surpassing 175 GHz for the 30 nm-channel. Additionally, transient analysis is conducted by applying a resistive load inverter circuit to a pulse input. The fall propagation delay (t phl) exhibits a greater than two orders of magnitude enhancement, along with improved overshoot voltage (V P) compared to a TFET without a pocket. The study further explores the impact of supply scaling on transient parameters. Optimal pocket scalability concerning channel length is found to be 40% for pocket length and approximately 2.5% for pocket shift relative to the source-channel interface. The proposed design significantly enhances DC and analog as well as circuit-level metrics compared to the traditional uniform gate oxide TFET. [ABSTRACT FROM AUTHOR]

Direct extraction of gap states from a metal-oxide-semiconductor field-effect transistor (MOSFET) in which inversion electrons and holes in a p-type body coexist is challenging. We demonstrate gap-state extraction in lateral-type GaN MOSFETs with high channel mobilities using multi-terminal capacitance–voltage (C–V) methods. The gate stack of the MOSFET was composed of AlSiO/AlN/p-type GaN formed on a p+/n+ GaN tunnel junction structure. The substrate electrode was short-circuited to a p-type body layer through the tunnel junction. The MOSFET was equipped with gate, source, drain, body, and substrate electrodes. When the gate was the high side and the other electrodes were the low side in the AC circuit, a V-shaped C–V curve was obtained because of electron inversion and hole accumulation. When the body/substrate electrodes were connected to the ground level (i.e., split C–V method), the inversion electrons between the gate and source/drain electrodes could be evaluated. We proposed a "reverse" split C–V method in which the source/drain electrodes are grounded and the body/substrate electrodes are connected to the low side. This method enabled extraction of gap states near the valence-band maximum of GaN, with exclusion of the overlap capacitance and the capacitance due to inversion electrons. The proposed method demonstrated overall gap states in the GaN MOSFET with a wide bandgap. The results suggest that hole traps with discrete energy levels caused negative bias instability (NBI) in the GaN MOSFET. Furthermore, NBI and discrete gap states were consistently suppressed by Mg doping at >1018 cm−3 into a p-type body. [ABSTRACT FROM AUTHOR]

High-k oxide materials for metal–oxide–semiconductor field-effect transistors and metal–oxide–semiconductor (MOS) structure on SiC have been explored to enhance SiC-based device performance. In our experiments, the MOS capacitors with a high-k barium titanate (BaTiO3) insulating layer were fabricated using the aerosol deposition (AD) method, and post-deposition annealed in O2 atmospheres. We examined the effects of post-deposition annealing on the BaTiO3 films and their impact on the surface and electrical characteristics of MOS capacitors. The crystallinity and surface morphologies of the BaTiO3 films were analyzed by X-ray diffraction, scanning electron microscopy, energy-dispersive X-ray spectroscopy, and atomic force microscopy. We conducted the electrical analysis through current–voltage and capacitance–voltage (C–V) measurements. The post-deposition annealing process effectively reduced the gate leakage current of BaTiO3/4H-SiC and elevated the rectification ratio from 9.12 × 108 to 1.61 × 109. C–V characteristics were measured at 1 MHz to investigate the oxide defect charges inside the MOS capacitors. Near-interface trap density ( N it ) decreased from 9.10 × 1011 to 5.53 × 1011 cm−2 due to post-annealing, which diminished flat band voltage hysteresis. Fixed oxide charge density ( Q f ) also diminished from 4.00 × 1011 to 3.58 × 1011 cm−2, and the oxygen vacancies were compensated by the oxygen atoms introduced from the O2 during the post-deposition annealing. Our findings suggest that the post-deposition annealed process significantly influences surface and electrical properties during BaTiO3 thin film deposition using AD. [ABSTRACT FROM AUTHOR]

We report on the experimental demonstration of high-performance suspended channel transistors with single- and bilayer (1L and 2L) molybdenum disulfide (MoS2), and on operating them as vibrating channel transistors (VCTs) and exploiting their built-in dynamic electromechanical coupling to read out picoampere (pA) transconduction current directly at the vibrating tones, without frequency conversion or down-mixing, for picometer (pm)-scale motion detection at room temperature. The 1L- and 2L-MoS2 VCTs exhibit excellent n-type transistor behavior with high mobility [150 cm2/(V·s)] and small subthreshold swing (98 mV/dec). Their resonance motions are probed by directly measuring the small-signal drain-source currents (iD). Electromechanical characteristics of the devices are extracted from the measured iD, yielding resonances at f0 = 31.83 MHz with quality factor Q = 117 and f0 = 21.43 MHz with Q = 110 for 1L- and 2L-MoS2 VCTs, respectively. The 2L-MoS2 VCT demonstrates excellent current and displacement sensitivity (Si1/2 = 2 pA/Hz1/2 and Sx1/2 = 0.5 pm/Hz1/2). We demonstrate f0 tuning by controlling gate voltage VG and achieve frequency tunability Δf0/f0 ≈ 8% and resonance frequency change Δf0/ΔVG ≈ 0.53 kHz/mV. This study helps pave the way to realizing ultrasensitive self-transducing 2D nanoelectromechanical systems at room temperature, in all-electronic configurations, for on-chip applications. [ABSTRACT FROM AUTHOR]

This study proposes a phosphosilicate glass (PSG)-based electrolyte gate synaptic transistor with varying phosphorus (P) concentrations. A metal oxide semiconductor capacitor structure device was employed to measure the frequency-dependent (C-f) capacitance curve, demonstrating that the PSG electric double-layer capacitance increased at 103 Hz with rising P concentration. Fourier transform infrared spectroscopy spectra analysis facilitated a theoretical understanding of the C-f curve results, examining peak differences in the P-OH structure based on P concentration. Using the proposed synaptic transistors with different P concentrations, changes in the hysteresis window were investigated by measuring the double-sweep transfer curves. Subsequently, alterations in proton movement within the PSG and charge characteristics at the channel/PSG electrolyte interface were observed through excitatory post-synaptic currents, paired-pulse facilitation, signal-filtering functions, resting current levels, and potentiation and depression characteristics. Finally, we demonstrated the proposed neuromorphic system's feasibility based on P concentration using the Modified National Institute of Standards and Technology learning simulations. The study findings suggest that, by adjusting the PSG film's P concentration for the same electrical stimulus, it is possible to selectively mimic the synaptic signal strength of human synapses. Therefore, this approach can positively contribute to the implementation of various neuromorphic systems. [ABSTRACT FROM AUTHOR]

To replace SiO2 as gate dielectrics in complementary metal‐oxide‐semiconductor‐compatible microelectronic devices, research on alternative high‐k dielectric materials is deeply focused. Although high‐k dielectrics have high permittivity, it suffers from poor electrical quality due to the presence of charge densities during the deposition process. To suppress these charge densities, there is an urge for a suitable fabrication process. Herein, radio frequency magnetron sputtering is used to deposit Ta2O5 thin films on p‐type Si. During deposition, sputtering pressure and Ar/O2 gas flow ratio are varied systematically. Postdeposition annealing is carried out for an hour at 900 °C in air ambient. The microstructural, morphological, and electrical properties are studied from X‐ray diffraction (XRD), Fourier transform infrared spectroscopy, atomic force microscopy (AFM), capacitance–voltage, and current–voltage characteristics. XRD reveals orthorhombic β‐phase structure of the film annealed at 900 °C. The AFM micrographs show that the roughness of the film increases with the increase in both sputtering pressure and Ar/O2 gas flow ratio. The oxide charge density (Qox), interface charge density (Dit), and leakage current are found to be decreased with the increase in both Ar/O2 gas flow ratio and sputtering pressure. [ABSTRACT FROM AUTHOR]

Ultrathin flexible encapsulation (UFE) using multilayered films has prospects for practical applications, such as implantable and wearable electronics. However, existing investigations of the effect of mechanical bending strains on electrical properties after the encapsulation procedure provide insufficient information for improving the electrical stability of ultrathin silicon nanomembrane (Si NM)-based metal oxide semiconductor capacitors (MOSCAPs). Here, we used atomic layer deposition and molecular layer deposition to generate 3.5 dyads of alternating 11 nm Al2O3 and 3.5 nm aluminum alkoxide (alucone) nanolaminates on flexible Si NM-based MOSCAPs. Moreover, we bent the MOSCAPs inwardly to radii of 85 and 110.5 mm and outwardly to radii of 77.5 and 38.5 mm. Subsequently, we tested the unbent and bent MOSCAPs to determine the effect of strain on various electrical parameters, namely the maximum capacitance, minimum capacitance, gate leakage current density, hysteresis voltage, effective oxide charge, oxide trapped charge, interface trap density, and frequency dispersion. The comparison of encapsulated and unencapsulated MOSCAPs on these critical parameters at bending strains indicated that Al2O3/alucone nanolaminates stabilized the electrical and interfacial characteristics of the Si NM-based MOSCAPs. These results highlight that ultrathin Al2O3/alucone nanolaminates are promising encapsulation materials for prolonging the operational lifetimes of flexible Si NM-based metal oxide semiconductor field-effect transistors. [ABSTRACT FROM AUTHOR]

We developed an in-operando x-ray topography method for dynamically visualizing single Shockley-type stacking fault (1SSF) expansion motions in silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) during their operations and investigated the effect of the operating condition applied to the body diodes in SiC MOSFETs on dislocation glide velocity. In-operando x-ray topography observations were carried out in reflection geometry, and a high-resolution x-ray camera was used as a detector to record topographies dynamically. The sequence of 1SSF expansion motions in the SiC MOSFETs was observed at a high resolution of 1 s in x-ray topographies, which is sufficient to analyze the dislocation glide velocity of a 1SSF expansion. The observation results of changing the forward current density applied to the body diodes in SiC MOSFETs revealed that each triangular and bar-shaped 1SSF expands at different forward current densities. The 1SSF expansion timings also differed, even in the same chip under the same current density. The dislocation glide velocity of each expanded 1SSF in SiC MOSFETs was extracted, and it increased with the forward current density. Our method enables the dynamic visualization of bipolar degradation in SiC MOSFETs during their operations, and we can accurately obtain the information of when, where, and which 1SSF expands in a SiC MOSFET. [ABSTRACT FROM AUTHOR]

In this paper, we implement the pulsed current–voltage (PIV) technique for the metal-oxide-semiconductor field-effect transistor (MOSFET) device's ultrafast characterization based on the OpAmp amplifier OPA818. The latter dropped down the measurement time for a whole MOSFET characteristic to = 50 ns as an enhancement. Furthermore, a study concerning the technique's dependency on measurement time (), channel length (), and channel width () is accomplished. It is found that the distortion in the technique's results, labeled as hysteresis, is inversely proportional to measurement time and it increases dramatically with very low values of . Also, the results show that PIV could have a somehow direct proportionality to channel length, and it is justified by the gate/drain capacitance () effect. On the other hand, the technique shows no dependency on channel width at all. Moreover, as measurements limitations, the results couldn't record drain currents less than ≈ 10–7 A, this makes PIV limited to the study of threshold voltage degradation () only. However, this issue is well discussed and solutions have been proposed. [ABSTRACT FROM AUTHOR]

One main obstacle to obtaining high carrier mobility in transistors with metal-oxide-semiconductor (MOS) structures is carrier scattering, which has been systematically investigated. In the past few decades, much attention was preferentially paid to the scatterings arising from the region near the semiconductor/oxide interface because they can affect the carrier transport in the semiconductor channel more directly and effectively, e.g., polaronic effect, Coulomb scattering, surface-roughness scattering, and intrinsic phonon scattering resulted from the thermal vibration of the semiconductor channel. However, scattering originated from hybrid interface plasmon/optical-phonon excitations, so-called remote phonon scattering, has been neglected to some extent, but is especially severe for gate oxides with high dielectric constants due to the easy vibrations of their atoms. On the other hand, plasmons generated from the oscillations of majority carriers in the gate electrode can couple with the remote phonons to suppress the remote phonon scattering, which is called the gate screening effect. However, when the frequency of the gate-electrode plasmon is close/equal to that of the gate-dielectric phonon, the resonance between the gate electrode and the gate dielectric greatly enhances the remote phonon scattering to severely degrade the carrier mobility (so-called gate antiscreening effect). This work intends to give a comprehensive review on the origins, effects, suppression methods, and recent advances of the remote phonon scattering, with a view to achieving high-mobility MOS devices (including those based on two-dimensional semiconductors) with high-k gate dielectrics for future high-speed electronic applications. [ABSTRACT FROM AUTHOR]

In this study, we investigated the crystallographic and electrical properties of ZrO2 thin films prepared by an ozone-based atomic layer deposition process. Cyclopentadienyl tris(dimethylamino) zirconium [CpZr(NMe2)3] was used as the Zr precursor, and O3 was used as the reactant. ZrO2 films were produced using O3 in various concentrations from 100 to 400 g/m3. These thin films were used to fabricate metal–oxide–semiconductor capacitors, whose electrical properties were evaluated and correlated with crystallographic analysis. As the O3 concentration increased, the tetragonal phase of the ZrO2 film stabilized and the dielectric constant improved. However, the leakage current density characteristics concurrently deteriorated due to the high concentration of O3, increasing the number of grain boundaries in the ZrO2 film by increasing crystallinity. Thus, the concentration of O3 can control the number of OH groups of the ZrO2 film, affecting the device characteristics. [ABSTRACT FROM AUTHOR]

Optical phase shifters are essential elements in photonic integrated circuits (PICs) and function as a direct interface to program the PICs. Non‐volatile phase shifters, which can retain information without a power supply, are highly desirable for low‐power static operations. Here a non‐volatile optical phase shifter is demonstrated by driving a III‐V/Si hybrid metal‐oxide‐semiconductor (MOS) phase shifter with a ferroelectric field‐effect transistor (FeFET) operating in the source follower mode. Owing to the various polarization states in the FeFET, multistate non‐volatile phase shifts up to 1.25π are obtained with CMOS‐compatible operation voltages and low switching energy up to 3.3 nJ. Furthermore, a crossbar array architecture is proposed to simplify the control of non‐volatile phase shifters in large‐scale PICs and verify its feasibility by confirming the selective write‐in operation of a targeted FeFET with a negligible disturbance to the others. This work paves the way for realizing large‐scale non‐volatile programmable PICs for emerging computing applications such as deep learning and quantum computing. [ABSTRACT FROM AUTHOR]

Ferroelectric negative capacitance transistors (Fe‐NCFETs) have emerged as a promising technology for low‐power electronics and have the potential to continue Moore's law. However, the existing 2D ferroelectric materials are predominantly sulfides or halides, which are susceptible to oxidation or hydrolysis, thereby hindering their commercial production due to concerns related to performance and stability. To address these obstacles, the authors have optimized the Fe‐NCFETs composed of 2D ferroelectric CuInP2S6 and semiconductor WS2 using high‐k Al2O3 passivation and dual‐gate modulation strategy. With atomic layer deposition (ALD) of Al2O3, all‐2D Fe‐NCFETs, operated at a low driven voltage of 0.3 V, achieve much improvement in stability and performance with a high ON/OFF ratio of 109 and minimum subthreshold swing (SS) of 14 mV dec−1, which is attributed to the negative capacitance effect of CuInP2S6 and passivation effect of ALD‐Al2O3. The dual‐gate modulation approach is also implemented to maintain the device stability and enable the improved ON/OFF ratio from 105 to 108, minimum SS of 10 mV dec−1, and an average SS of ≈60 mV dec−1 covering more than five orders of magnitude of current. This work provides a facile and effective strategy for designing all‐2D Fe‐NCFETs with ultra‐steep SS and high stability, showing exciting potential for future low‐power electronic applications. [ABSTRACT FROM AUTHOR]

The gas detectors consist of two parts: metal-oxides gas sensor and transducer. The sensing material is made of a thin semiconductor layer. The transducer is responsible for converting the change in the several physical parameters of the thin sensitive layer into a measurable signal. Due to the high output resistance of high resistive gas sensors and the low input currents of amplifiers, electrometric cascades are employed, followed by the conversion of the gas sensors small direct current into an active current signal using a mechanical modulator (dynamic capacitor) to enhance sensitivity and stability. The aim of this research is to analyze the main characteristics of a novel type of dynamic capacitor that utilizes a surface metal-oxide-semiconductor (MOS) photovaricap (PV) as the regulating element when detecting signals from high resistive gas sensors. For the creation of surface MOS PVs, samples of p-Si with varying resistivity were chosen. A thin layer of SiO2 was deposited on these samples, onto which a translucent metallic electrode was applied. Modulation of the PV capacitance was achieved by illuminating it with a gallium arsenide LED. As a result, the capacitance of the PV is changed, producing a variable voltage across the load resistor, which was then amplified and recorded. It was observed that the settling time of the useful signal is determined by two factors. The first is the RC chain composed of the load resistance of the gas sensor and the input capacitance of the PV, and the second is slow relaxation phenomena in the structure of the MOS PV that lead to the screening of the induced charge. Characteristics of the MOS PV as a dynamic capacitor and the features of the photo capacitance as a semiconductor element, in turn, determine the transimpedance conversion coefficient. The conducted research showed that MOS PVs can be applied to register small DC currents and voltages from high resistive gas sensors. In this case, ordinary narrowband or wideband amplifiers with relatively low input resistance can be used instead of electrometric amplifiers with mechanical dynamic capacitors. The considered circuit has been experimentally tested with commercial resistors. [ABSTRACT FROM AUTHOR]

In this work, a dual interfacial passivation layer (IPL) consisting of TaON/GeON is implemented in GaAs metal-oxide-semiconductor (MOS) capacitors with ZrTaON as a high-k layer to obtain superior interfacial and electrical properties. As compared to the samples with only GeON IPL or no IPL, the sample with the dual IPL of TaON/GeON exhibits the best performance: low interface-state density (1.31 × 1012 cm−2 eV−1), small gate leakage current density (1.62 × 10−5 A cm−2 at Vfb + 1 V) and large equivalent dielectric constant (18.0). These exceptional results can be attributed to the effective blocking action of the TaON/GeON dual IPL. It efficiently prevents the out-diffusion of Ga/As atoms and the in-diffusion of oxygen, thereby safeguarding the gate stack against degradation. Additionally, the insertion of the thin TaON layer successfully hinders the interdiffusion of Zr/Ge atoms, thus averting any reaction between Zr and Ge. Consequently, the occurrence of defects in the gate stack and at/near the GaAs surface is significantly reduced. [ABSTRACT FROM AUTHOR]

Advances in the growth processes of 4H-SiC epitaxial layers have led to the continued expansion of epilayer thickness, allowing for the detection of more penetrative radioactive particles. We report the fabrication and characterization of high-resolution Schottky barrier radiation detectors on 250 μm thick n-type 4H-SiC epitaxial layers, the highest reported thickness to date. Several 8 × 8 mm2 detectors were fabricated from a diced 100 mm diameter 4H-SiC epitaxial wafer grown on a conductive 4H-SiC substrate with a mean micropipe density of 0.11 cm−2. From the Mott–Schottky plots, the effective doping concentration was found to be in the range (0.95–1.85) × 1014 cm−3, implying that full depletion could be achieved at ∼5.7 kV (0.5 MV/cm at the interface). The current-voltage characteristics demonstrated consistently low leakage current densities of 1–3 nA/cm2 at a reverse bias of −800 V. This resulted in the pulse-height spectra generated using a 241Am alpha source (5486 keV) manifesting an energy resolution of less than 0.5% full width at half maximum (FWHM) for all the detectors at −200 V. The charge collection efficiencies (CCEs) were measured to be 98–99% with no discernable correlation to the energy resolution. A drift-diffusion model fit to the variation of CCE as a function of bias voltage, revealed a minority carrier diffusion length of ∼10 μm. Deep level transient spectroscopy measurements on the best resolution detector revealed that the excellent performance was the result of having ultralow concentrations of the order of 1011 cm−3 lifetime limiting defects—Z1/2 and EH6/7. [ABSTRACT FROM AUTHOR]

The 2D electrons trapped in vacuum near the atomically thin dielectric (ATD, mono- or N -layer film of h -BN or transition metal dichalcogenide) are considered. ATD is suspended above the back gate and forms the capacitor, which is controlled by the biased voltage determining 2D concentration, n 2 D . It is found that the leakage current through ATD is negligible, and the effect of the polarizability of ATD is weak if N ≤ 5. At temperatures T = 0.1 – 15 K and n 2 D = 5 × 10 8 – 10 10 cm − 2 , one deals with the Boltzmann liquid having a macroscopic thickness of ∼ 100 A. Due to the bending of ATD, the quadratic dispersion law of the flexural vibrations is transformed into the linear one at small wave vectors. The scattering processes of the electrons caused by these phonons or the monolayer islands on ATD are examined and the momentum and energy relaxation rates are analyzed based on the corresponding balance equations. The momentum relaxation times vary over orders of magnitude in the above region (T , n 2 D ) and N. The response may change from the polaron transport, for a perfect single-layer ATD at low T and high n 2 D , to the high-mobility (≥ 10 7 cm 2 / V s) regime at high T and low n 2 D . The quasi-elastic energy relaxation due to phonon-induced scattering is considered, and the conditions for the heating of electrons by a weak in-plane electric field are found. [ABSTRACT FROM AUTHOR]

The state-of-the-art technology for gate oxides on SiC involves the introduction of nitrogen to reduce the density of interface defects. However, SiC metal–oxide–semiconductor (MOS) field-effect transistors still suffer from low channel mobility even after the nitridation treatment. Recent reports have indicated that this is due to near-interface traps (NITs) that communicate with electrons in the SiC conduction band via tunneling. In light of this evidence, it is clear that conventional interface trap analysis is not appropriate for these defects. To address this shortcoming, we introduce a new characterization method based on conductance–temperature spectroscopy. We present simple equations to facilitate the comparison of different fabrication methods based on the density and location of NITs and give some information about their origin. These techniques can also be applied to NITs in other MOS structures. [ABSTRACT FROM AUTHOR]

The bulk and interfacial properties of aluminum silicon oxide (AlSiO) on N-polar GaN were investigated systematically employing capacitance-voltage (C-V) methods on metal-oxide-semiconductor capacitors using a thickness series of the AlSiO dielectric. The fixed charge density, electron slow trap density, and electron fast trap density located near the interface were extracted to be -1.5 × 1012 cm-2, 3.7 × 1011 cm-2, and 1.9 × 1011 cm-2, respectively. Using ultraviolet (UV) assisted C-V methods, an average interface state density of ~4.4 × 1011 cm-2 eV-1 and a hole trap concentration in bulk AlSiO of ~8.4 × 1018 cm-3 were measured. The negative fixed interface charge makes it favorable to achieve a normally off GaN transistor. The analysis presented in this paper provides a systematic and quantitative model to study the properties of oxide dielectrics on wide bandgap (WBG) semiconductors, which can promote the development of metal-oxide-semiconductor-based WBG semiconductor devices. [ABSTRACT FROM AUTHOR]

Integration of the emerging layered materials with the existing CMOS platform is a promising solution to enhance the performance and functionalities of the future CMOS based integrated circuits. In this direction, we have experimentally studied the suitability of the layered semimetals, namely, Td-WTe2, 1T′-MoTe2, 1T-PtTe2, and 1T-PtSe2, as an electrode with two most commonly used semiconductors, i.e., silicon (Si) and germanium (Ge) used in the CMOS technology. Two kinds of devices, i.e., metal–oxide–semiconductor (MOS) capacitors and metal-semiconductor (MS) diodes, are investigated with these semimetals as a conducting electrode. Through detailed electrical and physical characterizations, it is established that these semimetals form excellent interface with the underneath dielectric (SiO2) in the MOS structure and with the semiconductor (Ge) in the MS diode. Near ideal CV curves of MOS devices and large ON-current in the MS diodes signify that these semimetals act perfectly well as a contact electrode. Reduction in the Schottky barrier height of the MS diodes with decreasing values of the semimetal WF suggests the excellent interface of these semimetals with the Ge substrate. Most importantly, these semimetals do not add any unwanted series resistance across the current conduction path in the diode. Guided by these experimental observations, we propose that these semimetals can indeed be integrated with conventional CMOS platform, thus paving a way for an era of CMOS based heterogeneous electronics. [ABSTRACT FROM AUTHOR]

This short article is concerned with the floating high-side gate driver suitable for driving the high side MOSFET/IGBT switch in the series capacitor buck converter family or converters with similar topological features. Biasing the high-side driver in series capacitor buck converters presents an engineering challenge. To alleviate the problem, a modified high-side driver with a voltage lift circuit for driving a high-side switch is proposed. The suggested solution, while being simple and low cost, has several benefits over the earlier propositions. The primary advantage of the proposed circuit is that it relies on a regulated supply to recharge its boot capacitor so to properly bias the high-side driver. Moreover, the proposed driver can operate in a wide range of input voltages while self-adjusting the correct voltage lift according to the operating point of a particular phase of the series buck converter. Thus, any number of phases can be implemented, avoiding cross-coupling effects and providing the high-switch with gating pulses of same amplitude. [ABSTRACT FROM AUTHOR]

Self-aligned metal-oxide-semiconductor (MOS) capacitors are studied with several low-temperature, wet chemical silicon dioxide (SiO2) interlayers to understand their impact on electrical performance. Self-aligned MOS capacitors are fabricated with a bottom-up patterning technique that uses a poly(methyl methacrylate) brush and dopant-selective KOH etch combined with area-selective atomic layer deposition of hafnium dioxide (HfO2) and Pt. The wet chemical pretreatments used to form the SiO2 interlayer include hydrofluoric acid (HF) etch, 80 °C H2O, and SC-2. Capacitance-voltage measurements of these area-selective capacitors exhibit a HfO2 dielectric constant of ∼19, irrespective of pretreatment. After a forming gas anneal, the average interface state density decreased between 1.8 and 7.5 times. The minimum observed Dit is 1 × 1011 eV−1 cm−2 for the HF-last treatment. X-ray photoelectron spectroscopy shows an increase in stoichiometric SiO2 in the interfacial layer after the anneal. Additional carbon is also observed; however, comparison with capacitors fabricated in a nonselective process reveals minimal impact on performance. [ABSTRACT FROM AUTHOR]

Perovskite solar cells (PSCs) using carbon as the counter electrode fabricated through a low‐temperature full solution‐process method can significantly simplify the preparation process and reduce production cost. Herein, a high‐performance PSC is presented with printed carbon electrode and dopant‐free poly(3‐hexylthiophene) (P3HT) is employed as hole transport materials. Different organic bromide salts are employed to modify the perovskite/P3HT interface to further enhance the performance. As a result, methylammonium bromide (MABr) modification significantly enhances the device open‐voltage (Voc) and fill factor (FF) by reducing interface defects and facilitates charge transport. A champion power conversion efficiency (PCE) of 19.22% (Voc of 1.118 V, FF of 0.765, and short‐circuit current of 22.48 mA cm−2) is achieved with MABr modification. The unencapsulated devices maintain 96% of the initial efficiency after storage for 3600 h and 88% after thermal treatment at 70 °C for 1200 h. Additionally, perovskite solar modules are also prepared based on printing and interface passivation route with PCE reaches 13.20%. These results represent an important progress in the enhancement of device PCE and up‐scaling of PSCs with cost‐effective, stable, and printed carbon electrode. [ABSTRACT FROM AUTHOR]

Metal-oxide-semiconductor (MOS) capacitors with Al2O3 as a gate insulator are fabricated on cubic silicon carbide (3C-SiC). Al2O3 is deposited both by thermal and plasma-enhanced Atomic Layer Deposition (ALD) on a thermally grown 5 nm SiO2 interlayer to improve the ALD nucleation and guarantee a better band offset with the SiC. The deposited Al2O3/SiO2 stacks show lower negative shifts of the flat band voltage VFB (in the range of about −3 V) compared with the conventional single SiO2 layer (in the range of −9 V). This lower negative shift is due to the combined effect of the Al2O3 higher permittivity (ε = 8) and to the reduced amount of carbon defects generated during the short thermal oxidation process for the thin SiO2. Moreover, the comparison between thermal and plasma-enhanced ALD suggests that this latter approach produces Al2O3 layers possessing better insulating behavior in terms of distribution of the leakage current breakdown. In fact, despite both possessing a breakdown voltage of 26 V, the T-ALD Al2O3 sample is characterised by a higher current density starting from 15 V. This can be attributable to the slightly inferior quality (in terms of density and defects) of Al2O3 obtained by the thermal approach and, which also explains its non-uniform dC/dV distribution arising by SCM maps. [ABSTRACT FROM AUTHOR]

In this work, we design and simulate a three-dimensional (3D) SU-8 tapered edge coupler for effectively guiding light from an edge-emitting semiconductor laser diode directly to a silicon waveguide to realize a hybrid on-chip silicon light source. A series of coupling efficiencies for the commonly used top silicon thicknesses of the silicon-on-insulator wafers from 220 to 3000 nm are obtained, showing that this polymer taper can largely improve the coupling efficiency when the silicon waveguide thickness is moderate, for instance, from 41% (with no taper) to 67% for the 700 nm- thick silicon waveguide under 1 μ m gap offset and relax the lateral misalignment tolerance to above one micron by suppressing the butt refractive index contrast and the mode mismatch between the laser diode and the silicon waveguide. Wave transformation inside the tapered coupler and the input silicon waveguide has also been revealed by 3D finite-difference time-domain simulations. This 3D tapered coupler is cost effective and easily fabricated which can have wide practical applications in massive production of various silicon photonic chips based on the present complementary metal-oxide-semiconductor foundry. [ABSTRACT FROM AUTHOR]

It was shown in [1, 2] that the dependence of the fault tolerance of a static RAM cell on the energy of secondary particles resulting from the action of a neutron flux does not take into account another significant factor—the part of the transistor in which these secondary particles are generated. In order to determine the area of the memory cell in which the impact of secondary particles can lead to a failure, the probability of a failure depending on the location of the occurrence of the secondary particle is studied. A method for analyzing the accumulated charge is proposed for assessing the fault tolerance of a static random access memory cell depending on the place of occurrence of the secondary particle and the charge corresponding to the margin of static noise immunity. The analysis is carried out based on the results of the instrumental-technological simulation of a single MOS transistor, which is part of a static RAM cell, and the integration of the obtained values of the current responses from the regions of the transistor. [ABSTRACT FROM AUTHOR]

We fabricate top-gate transistors on the three-layer molybdenum disulfide (MoS2) with three, two, and one layers in the source and drain regions using atomic layer etching (ALE). In the presence of ALE, the device at zero gate voltage can exhibit high and low levels of drain current under the forward and reverse gate bias, respectively. The hysteresis loop on the transfer curve of transistor indicates that two distinct charge states exist in the device within a range of gate bias. A long retention time of the charge is observed. Unlike conventional semiconductor memories with transistors and capacitors, the two-dimensional (2D) material itself plays two parts in the current conduction and charge storage. The persistent charge storage and memory operation of the multilayer MoS2 transistors with thicknesses of a few atomic layer will further expand the device application of 2D materials with reduced linewidths. [ABSTRACT FROM AUTHOR]

In this study, a high-K material, aluminum oxide (AlOx), as the dielectric of organic field-effect transistors (OFETs) was used to reduce the threshold and operating voltages, while focusing on achieving high-electrical-stability OFETs and retention in OFET-based memory devices. To achieve this, we modified the gate dielectric of OFETs using polyimide (PI) with different solid contents to tune the properties and reduce the trap state density of the gate dielectric, leading to controllable stability in the N, N'-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (PTCDI-C13)-based OFETs. Thus, gate field-induced stress can be compensated for by the carriers accumulated due to the dipole field created by electric dipoles within the PI layer, thereby improving the OFET's performance and stability. Moreover, if the OFET is modified by PI with different solid contents, it can operate more stably under fixed gate bias stress over time than the device with AlOx as the dielectric layer only can. Furthermore, the OFET-based memory devices with PI film showed good memory retention and durability. In summary, we successfully fabricated a low-voltage operating and stable OFET and an organic memory device in which the memory window has potential for industrial production. [ABSTRACT FROM AUTHOR]

Herein, zirconia thin films are successfully prepared on silicon substrates using the sol–gel method, and the microstructure, optical, and electrical properties of zirconia high‐k gate dielectric films are analyzed at different annealing temperatures. X‐ray diffraction results show that ZrO2 films crystallize above 500 °C and the grain size increases with the increase of annealing temperature; X‐ray photoelectron spectroscopy analysis confirms that metal–oxygen bonds can be effectively formed and defects in the films are eliminated by annealing treatment, with significant changes in the valence band shift (ΔEv) and conduction band shift (ΔEc) with increasing annealing temperature. Analysis of the optical properties of the films by UV‐Vis confirms that all zirconia films have high transmittance, with the bandgap increasing from 5.54 to 5.74 eV with increasing annealing temperature. Atomic force microscope and field emission scanning electron microscope show that the film quality is better and the root mean square roughness of the zirconia films increases from 0.551 to 1.190 nm and the film thickness decreases from 176.19 to 58.73 nm with increasing annealing temperature. Electrical performance tests show that proper annealing is effective in improving electrical properties, such as obtaining a larger dielectric constant (k) and a lower leakage current density. [ABSTRACT FROM AUTHOR]

Very fast interface traps have recently been suggested to be the main cause behind the rather poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors (MOSFETs). Using capacitance voltage analysis and conductance spectroscopy on metal oxide semiconductor capacitors, at cryogenic temperatures, we find that these fast traps are absent in oxides made by sodium enhanced oxidation, and high inversion channel-carrier mobility in MOSFETs made by sodium enhanced oxidation is observed. [ABSTRACT FROM AUTHOR]