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While complete automated design is a harder problem than computer-assisted design, automated hardware reconfiguration is an even more challenging problem, because it needs to adjust to limited resources and various factors, such as noise and parasitic capacitance, a resistance and inductance. This paper presents some experimental results of on-chip automated design and reconfiguration using evolvable hardware techniques. It describes a stand-alone board level evolvable system, and its use to demonstrate on-chip synthesis of new circuits in only a few seconds. The experiments presented here indicate a recovery capability in the case of extreme environmental conditions, such as extreme temperatures, that adversely affect electronics. Some of the difficulties of dealing with the real hardware are exposed, as well as challenges more generally related to automated evolution of complex electronic systems.

The STAR Time Projection Chamber was successfully operated during the first RHIC run in 2000. Most of the STAR contributions reported in these proceedings are based on the analysis of data from the TPC. In this article, we show that the performance achieved by the TPC, in terms of track reconstruction, position resolution, and particle identification are well suited for measuring precise and reliable physics observables.

We report measurements of Xi and Xi-bar hyperon absolute yields as a function of rapidity in 158 GeV/c Pb+Pb collisions. At midrapidity, dN/dy = 2.29 +/- 0.12 for Xi, and 0.52 +/- 0.05 for Xi-bar, leading to the ratio of Xi-bar/Xi = 0.23 +/- 0.03. Inverse slope parameters fitted to the measured transverse mass spectra are of the order of 300 MeV near mid-rapidity. The estimated total yield of Xi particles in Pb+Pb central interactions amounts to 7.4 +/- 1.0 per collision. Comparison to Xi production in properly scaled p+p reactions at the same energy reveals a dramatic enhancement (about one order of magnitude) of Xi production in Pb+Pb central collisions over elementary hadron interactions.

We propose a tuning method for Micro-Electro-Mechanical Systems (MEMS) gyroscopes based on evolutionary computation that has the capacity to efficiently increase the sensitivity of MEMS gyroscopes through tuning and, furthermore, to find the optimally tuned configuration for this state of increased sensitivity. We present the results of an experiment to determine the speed and efficiency of an evolutionary algorithm applied to electrostatic tuning of MEMS micro gyros. The MEMS gyro used in this experiment is a pyrex post resonator gyro (PRG) in a closed-loop control system. A measure of the quality of tuning is given by the difference in resonant frequencies, or frequency split, for the two orthogonal rocking axes. The current implementation of the closed-loop platform is able to measure and attain a relative stability in the sub-millihertz range, leading to a reduction of the frequency split to less than 100 mHz.

We propose a tuning method for Micro-Electro-Mechanical Systems (MEMS) gyroscopes based on evolutionary computation to increase the accuracy of MEMS gyroscopes through electrostatic tuning. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation. We also report on the development and preliminary results of a hardware platform for integrated tuning based on “switched drive-angle” of MEMS gyroscopes whereby the same gyro is operated with its drive direction first at 0° and then at 90°. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). The hardware platform easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

The Evolvable Computation Group, at NASA's Jet Propulsion Laboratory (JPL), is tasked with demonstrating the utility of computational engineering and computer optimized design for complex space systems. The group is comprised of researchers over a broad range of disciplines including biology, genetics, robotics, physics, computer science and system design, and employs biologically inspired evolutionary computational techniques to design and optimize complex systems. Over the past two years we have developed tools using genetic algorithms, simulated annealing and other optimizers to improve on human design of space systems. We have further demonstrated that the same tools used for computer-aided design and design evaluation can be used for automated innovation and design, and be applied to hardware in the loop such as robotic arms and MEMS micro-gyroscopes. These powerful techniques also serve to reduce redesign costs and schedules.

The intrinsic evolution of analog controllers to provide closed-loop control of the speed of a DC motor has been previously demonstrated at NASA Marshall Space Flight Center. A side effect of the evolutionary process is that during evolution there are necessarily poor configurations to be evaluated that could cause damage to the plant. This paper concerns the development and implementation of a safe evolvable analog controller (EAC) architecture able to evolve controllers on-line even in the presence of these poor configurations. The EAC concept is discussed and experimental results are presented that show the feasibility of the approach. This EAC architecture represents the first in a series of steps required to make deployment of an evolvable controller a reality.

We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning and, furthermore, to find the optimally tuned configuration for this state of increased sensitivity. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation.

We report the temperature dependence of the JPL/Boeing MEMS second generation post resonator gyroscopes and determine the effect of hysteresis over the range 35degC to 65degC. The results indicate a strong linear dependence of the drive frequency and sense frequency with temperature of 0.093Hz/degC and AGC bias voltage with temperature of 13mV/degC. The results also indicate a significant time lag of the gyroscope of these quantities when responding to external temperature variations but determined no hysteresis exists in the drive frequency, sense frequency, and AGC bias. Both the time-frequency and time-bias voltage relationships are of the form y = A+B*exp(-t/T) where A is an offset parameter in Hertz and Volts respectively and B depends on the magnitude of the temperature variation

We propose a tuning method for MEMS gyroscopes based on evolutionary computation that has the capacity to efficiently increase the sensitivity of MEMS gyroscopes through tuning and, furthermore, to find the optimally tuned configuration for this state of increased sensitivity. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation

This paper serves as a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to total ionizing dose (TID) effects. The experiments are performed using a JPL-developed reconfigurable device, a field programmable transistor array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on evolvable hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach, and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad

We report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The platform was developed and tested for the second generation JPL/Boeing post-resonator MEMS gyroscope. The control of this device is implemented through a digital design on a field programmable gate array (FPGA). A software interface allows the user to configure, calibrate, and tune the bias voltages on the microgyro. The interface easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip

We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation We also report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). The hardware platform easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

Temperature and radiation tolerant electronics, as well as long life survivability are the key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. Compensation techniques such as bias cancellation circuitry have also been employed. However, current technology can only ensure very limited lifetime in extreme environments. This paper presents a novel approach, based on evolvable hardware technology, which allows adaptive in-situ circuit redesign/reconfiguration during operation in extreme environments. This technology complements material/device advancements and increases the mission capability to survive harsh environments. The approach is demonstrated on a mixed-signal programmable chip, which recovers functionality until 280/spl deg/C. We show in this paper the functionality recovery at high temperatures for a variety of circuits, including rectifiers, amplifiers and filters.

Evolvable systems in silicon are third generation hardware in terms of flexibility and fault-tolerance. The first generation was fixed silicon: once a device was fabricated its structure was forever fixed. Reconfigurable hardware came as a second generation: new configurations could be downloaded changing the function of the device and also bypassing faulty areas, if any. The third generation is that of self-configurable, evolvable hardware (EHW), and adds the automatic reconfiguration feature, enabling truly adaptive hardware. This chapter addresses current efforts in building and using evolvable chips. The first section refers to evolutionary algorithms for evolvable hardware. The second section describes the JPL evolvable hardware testbed and the JPL Field Programmable Transistor Array (FPTA) chip designed and used for circuit evolution in silicon. The third section addresses the application of evolvable hardware for adaptive filtering and noise cancellation. The fourth section discusses the importance of fault-tolerant hardware in space and describes the evolvable hardware approach for faulttolerant design of a 4-bit data converter. The final section concludes the work.

Evolvable systems in silicon are third generation hardware in terms of flexibility. The first generation was fixed silicon: once a device was fabricated its structure was forever fixed. Reconfigurable hardware came as a second generation: new configurations could be downloaded changing the function of the device and also bypassing faulty areas, if any. The third generation is that of self-configurable, evolvable hardware (EHW), and adds the automatic reconfiguration feature, enabling truly adaptive hardware. This paper addresses current efforts in building and using evolvable chips. The first section refers to evolutionary algorithms for evolvable hardware. The second section describes the JPL evolvable hardware testbed and the JPL Field Programmable Transistor Array (FPTA) chip designed and used for circuit evolution in silicon. The third section addresses the application of evolvable hardware for signal separation and noise cancellation. The final section concludes the work.

This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit digital to analog converter (DAC) using the JPL stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems and provides autonomous, fast (tens to hundreds of seconds), on-chip evolution involving about 100,000 circuit evaluations. Its main components are a JPL field programmable transistor array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper describes an experiment consisting of the hierarchical evolution of a 4-bit DAC using 20 cells of the FPTA chip. Fault-recovery is demonstrated after applying stuck-at 0 faults to all switches of one particular cell, and using evolution to recover functionality. It is verified that the functionality can be recovered in less than one minute after the fault is detected while the evolutionary design of the 4-bit DAC from scratch took about 3 minutes.

No silicon fabrication and characterization of circuits with topologies designed by evolution has been done before, leaving open questions about the feasibility of the evolutionary design approach, as well as on how high performance, robust, or portable such designs could really be when implemented in hardware. This paper is the first to report on a silicon implementation of circuits evolved in simulation. Several circuits were evolved and fabricated in a 0.5-micron CMOS process. This paper focuses on results of logical gates evolved at a transistor level. It discusses the steps taken in order to increase the chances of robust and portable designs, summarizes the results of characterization tests based on chip measurements, and comments on the performance comparing to simulations.

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation field programmable transistor array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.

The paper presents some experiments in automatic reconfiguration of field programmable devices using evolutionary algorithms. The experiments use a Field Programmable Transistor Array (FPTA), reconfigurable at transistor level. While parasitic effects of imperfect switches interconnecting transistors deteriorate performance of conventional designs when mapped to the FPTA, evolutionary algorithms are able to find a working design solution. The experiments are performed with a stand-alone board-level evolvable system (SABLES) in which the evolutionary algorithm is implemented with a DSP. SABLES can automatically configure the FPTA in tens to hundreds of seconds, time in which evaluates /spl sim/100,000 circuit candidate solutions. The paper overviews some examples of evolutionary synthesis of analog circuits on the FPTA.

This paper comments on some directions of growth for evolvable hardware, proposes research directions that address the scalability problem and gives examples of results in novel areas approached by EHW. The directions of growth include Software/Hardware hybrids, electronic/non-electronic hybrids, and networked systems. The research directions proposed here are (1) evolutionary compilation of descriptions from behavioral Hardware Description languages (HDL) to structural HDL (for both the case of digital and analog/mixed signal) (2) evolutionary synthesis, i.e. converting from synthesizable HDL to circuits and (3) hardware-software partitioning (co-design) for CPU/FPGA hybrids. The results presented here illustrate evolutionary design of multi-junctional/adaptive circuits including polymorphic and reconfiguration based circuits, and evolution of optimized circuits, in particular low-voltage circuits.

Evolutionary algorithms (EA) offer good promise for automated design of analog circuits as well as for adaptation and automatic reconfiguration of programmable devices. In particular, EAs facilitate the design of analog circuits for very specific requirements, such as those related to the implementation of fuzzy operators, or even of complete fuzzy systems. The paper starts with a brief overview of the evolutionary process applied to circuit design and of a family of analog programmable devices that support on-chip evolution. As a case study, we describe the evolutionary design of a fuzzy controller, using re-configurable analog chips models and unstructured representation. We were able to achieve a circuit that approximates the control surface of a 2-input fuzzy controller, mapping thus a full fuzzy system in only seven transistors. The paper presents evidence that EA can provide very compact solutions for implementation of fuzzy systems, and that programmable analog devices are an efficient and rapid solution for rapid deployment of fuzzy systems.

Evolution of electronic circuits has been intensively investigated for the last five years. The main challenge of the area is the evolution of circuits for industrial applications and also to find methods to improve the performance of evolutionary computation in electronic circuit synthesis. The authors have been studying this problem using different approaches, such as new methods for circuit representation and fitness evaluation function. We describe in this paper experiments on the evolution of current mode circuits. Experimental results in the area of computational circuits suggest that the search space for this class of circuits is more amenable for evolution than their voltage mode counterparts. At the end of the paper we propose an application in the area of fuzzy control, which can provide benefits for the aerospace community, such as in applications for propulsion controlled aircraft.

The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occur during evolution with real hardware in the loop, or when the intention of the user is not completely reflected in the fitness function. SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution. It also illustrates how specifications not completely reflected in the fitness function, such as the time scales of response for logical circuits, may lead to overall unsatisfactory solutions. Both such situations can be handled with appropriate modification of fitness function and additional testing.

A drawback of using redundant number representation in arithmetic operations for general purpose processors is the need to convert the result to conventional notation before retiring the instruction. A possible solution is to allow forwarding of redundant-form results. To improve the efficiency of forwarding, functional units which can accept operands in redundant form are needed. To this end, a multiplier which accepts a redundant multiplicand and multiplier has been designed, simulated and compared with a conventional multiplier. The redundant multiplicand is converted to radix-2/sup k/ carry/save form before the multiples are formed. Simulations of a 32/spl times/32 bit multiplier show that for instructions which can use redundant form operands there is as much as 20% speedup compared to using conventional form.

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware plaform utilizing a Field Programmable Transistor Array (FPTA). The performance of these evolved controllers is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design.

In this paper we describe the hardware evolution of analog circuits performing signal separation tasks using JPL's Stand-Alone Board-Level Evolvable System (SABLES). SABLES integrates a Field Programmable Transistor Array chip (FPTA-2) and a Digital Signal Processor (DSP) implementing the Evolutionary Platform (EP). The FPTA-2 is a second generation reconfigurable mixed signal array chip whose cells can be programmed at the transistor level. Its chip architecture consists of an 8×8 matrix of reconfigurable cells. The FPTA-2 is reconfigured by evolution to achieve circuits that can extract a target signal that is combined with an undesired component or to perform the separation of a combination of two signals. The paper considers also an adaptive filter where the fitness function depends on the input signal. The results demonstrate that SABLES is not only able to perform signal separation and extraction, but it is also flexible enough to adapt to different input signals without human intervention, such as in the case of self-tuning and adaptive filters.

We present a design for a multiplier with redundant operands which conforms to the IEEE-754 floating-point standard. The design consists of a multiplier core and a rounding unit which conforms to the rounding modes specified by the IEEE standard and introduces a novel technique for calculating the sticky bit directly from the operands. We simulate a single-extended precision design and evaluate the delay versus a conventional design to be roughly equivalent, with extra savings possible with minor modification. The area is also estimated to be roughly 15% larger than a conventional design of the same precision.

We report the temperature dependence from 330 to 230 K of the photoconductivity measured in sublimed films of buckminsterfullerene, specifically, C60/70, up to 3 μm thick. In contrast to the temperature dependence of the dark conductivity, where reversible structure, associated with the onset of a phase transition to orientational ordering below 250 K, is observed, the photoconductivity shows an essentially monotonic decrease to lower temperatures. This provides additional evidence that the thermal generation rate increases as the C60/70 becomes orientationally ordered. It also suggests that the increased order below the transition temperature does not lead to significantly increased carrier mobilities.

We report photoeffects in the visible and near-infrared spectrum in submitted films of C60/70. The peak photoefficiency (photocarrier per absorbed photon) is ≈ 10−4. Since for wavelengths > 7000 A, absorption in C60/70 films is very weak, carrier photoinjection from the electrodes into the conduction states of C60/70 must be considered. Evidence, based on the energy level structure of C60 films, is discussed which suggests this may not be the source of the photocurrents. Alternatively, the observed threshold may be photoconductive edge associated with the reported weak absorption due to forbidden transitions in the lowest direct bandgap, which recent calculations place at 1.5 eV.

We report the electrical conductivity,σ, and its temperature dependence from 400 to 160 K measured in 1.5 μm thick, sublimed films of C60/70. At room temperature, σ≈ 10−14 (Ωcm)−1. Reversible structure in the temperature dependence, extending from ≈ 300 to 270 K, may reflect reported phase transitions related to orientational order. Assuming solid C60/70 is an intrinsic semiconductor, the high temperature bandgap is about 1.9 eV and the observations are consistent with a transition to a semiconductor, below ≈ 250 K, with a smaller bandgap. Higher carrier mobilities, due to the increased order below the transition, may also play a role.

A novel liquid argon calorimeter concept with thin cylindrical shell gaps, meeting the required physics performance for the forward region (/ vbη / vb > 3) in a high energy, high luminosity hadron collider experiment such as ATLAS, is described. A prototype for the electromagnetic section was built and tested in two electron testbeam runs at the Brookhaven AGS and at the CERN North Area in 1993, covering a total energy range from 2 to 200 GeV. Dependences of the signal on the impact angle and varying inactive material in front of the calorimeter have been studied. Important performance requirements such as signal linearity better than 2%, a sufficient energy resolution with a constant term of about 4% and a very good space resolution of about 0.6 mm have been demonstrated.

First results from the NA49 experiment with a {sup 208}Pb beam on a Pb target at the CERN SPS with total energy of 33 TeV are presented. Data on transverse energy production, forward energy flow and rapidity density of negative hadrons are shown and discussed. The degree of nuclear stopping and the energy densities achieved are estimated for near head-on collisions.

We propose a tuning method for Micro-Electro-Mechanical Systems (MEMS) gyroscopes based on evolutionary computation that has the capacity to efficiently increase the sensitivity of MEMS gyroscopes through tuning and, furthermore, to find the optimally tuned configuration for this state of increased sensitivity. We present the results of an experiment to determine the speed and efficiency of an evolutionary algorithm applied to electrostatic tuning of MEMS micro gyros. The MEMS gyro used in this experiment is a pyrex post resonator gyro (PRG) in a closed-loop control system. A measure of the quality of tuning is given by the difference in resonant frequencies, or frequency split, for the two orthogonal rocking axes. The current implementation of the closed loop platform is able to measure and attain a relative stability in the sub-millihertz range, leading to a reduction of the frequency split to less than 100 mHz.