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Two factors primarily drive the soaring cost of semiconductor test: the number of test patterns applied to each chip and the time it takes to run each pattern. Typical semiconductor testing for each chip involves a set of 1,000 to 5,000 test patterns. These tests are applied through scan chains that operate at about 25 MHz. Depending on the size of the scan chains on the chip, a set of test patterns can take a few seconds to execute per chip. It's easy to see that even a small decrease in either the number of patterns or the time to execute them can quickly add up to big savings across millions of fabricated chips. This potential savings forms the basis for dynamic scan, a new approach to the well-established scan test methodology. The authors initial studies indicate that dynamic scan could easily reduce the time spent applying test patterns by 40 percent. A more theoretical analysis shows a potential savings of as much as 80 percent.

We present a new technique for mapping the backpropagation algorithm on hypercube and related architectures. A key component of this technique is a network partitioning scheme called checkerboarding. Checkerboarding allows us to replace the all-to-all broadcast operation performed by the commonly used vertical network partitioning scheme, with operations that are much faster on the hypercubes and related architectures. Checkerboarding can be combined with the pattern partitioning technique to form a hybrid scheme that performs better than either one of these schemes. Theoretical analysis and experimental results on nCUBE and CM5 show that our scheme performs better than the other schemes, for both uniform and nonuniform networks. >

The authors discuss the requirements of learning for generalization, where the traditional methods based on gradient descent have limited success. A stochastic learning algorithm based on simulated annealing in weight space is presented. The authors verify the convergence properties and feasibility of the algorithm. An implementation of the algorithm and validation experiments are described. >

Sequential circuit fault simulation is a compute-intensive problem. Parallel simulation is one method to reduce fault simulation time. In this paper, we discuss a novel technique to partition the fault set for the fault parallel simulation of sequential circuits on multiple processors. When applied statically, the technique can scale well for up to thirty two processors on an ethernet. The fault set partitioning technique is simple and can itself be parallelized. Processors working in parallel require no communication with one another. An existing uniprocessor algorithm can be used for parallel simulation without modification. Therefore, this system can be used effectively on a low-cost parallel resource, such as a network of workstations.

Sequential circuit fault simulators use the multiple bits in a computer data word to accelerate simulation. We introduce, and implement, a new sequential circuit fault simulator, a parallel pattern parallel fault simulator, ZAMBEZI, which simultaneously simulates multiple faults with multiple vectors in one data word. ZAMBEZI is developed by enhancing the control flow, of existing parallel pattern algorithms. For a very wide range of benchmark circuits, compared to parallel fault and parallel pattern simulators, ZAMBEZI offers either the best, or very close to the best, uniprocessor performance. ZAMBEZI also offers superior performance when parallelized.

Several generic parallel formulations of the backpropagation learning algorithm have been proposed recently. Further speedups are possible by customizing parallel formulations to the architecture of the neural network. The paper addresses the issue of customizing parallel formulations of the backpropagation learning algorithm to a given neural network architecture on multiprocessors with hypercube-like communication topology. We introduce a new parallel formulation called rectangular checkerboarding which adapts to the network architecture and can provide performance gains for non-uniform neural networks, where the number of nodes vary across the layers. Algebraic analysis shows that each instance of rectangular checkerboarding (using a specific rectangular processor grid) is optimal for an important family of network architectures. Experiments on CM-5 show that customizing to network architecture can provide significant (/spl sim/50%) performance gains for many interesting non-uniform neural network architectures, which are currently used in important applications. We also introduce the staircase framework, which can use different processor grids for different layers of a neural network. >

Fault simulation is a computer-intensive problem. Parallel processing is one method to reduce simulation time. In this paper, we discuss a technique to partition the fault set for fault-parallel simulation on multiple processors. When applied statically, the technique can scale well for up to 32 processors. The fault-set partitioning technique is simple and can itself be parallelized. Existing uniprocessor algorithms, based on parallel-pattern simulation, can be used for multiprocessor simulation without modification. Therefore, the techniques can be used effectively on a low-cost parallel resource such as a network of workstations.

RTL-based high level design methodology suffers a major drawback in the area of testability analysis due to lack of effective RTL fault models. Testability of a design is considered structure dependent. Since the structure of a design changes drastically with every logic synthesis run, testability analysis is performed only after final logic synthesis and therefore findings of such effort are too late to be implemented in the design without a significant schedule impact. In this paper we analyze the testability relationship between the RT level design and different structural (gate level) implementations resulting from optimization driven logic synthesis runs. We empirically establish that the testability properties of structural implementations are derived from architectural descriptions at the RT level and therefore logic synthesis does not significantly impact them. Furthermore, various different structural implementations resulting from logic synthesis (with different optimization constraints) exhibit poor testability in the same RTL design space. The data presented in this paper provides a missing key ingredient towards successful RTL fault modeling. We also propose the use of preliminary gate level netlist for early analysis to estimate testability properties of the final implementation.

We consider output regulation for SISO nonlinear plants by gain scheduling on the plant output. The objective of design is to keep the states within prescribed bound from their instantaneous trim values and output asymptotic tracking of reference signal. The controller is constructed using synthesis of chaos and a scheduler monitoring the error between reference signal and the output. The design eliminates the need for scheduling variable to vary slowly yet the feedback system has robust performance and nominal stability.

Bladder neoplasia of the transitional cell type progresses by two distinct, but occasionally interrelated, pathways characterized morphologically by a papillary or nonpapillary configuration. In this review, the authors discuss intraepithelial lesions of the urinary bladder, le, those lesions confined within the basement membrane of the urothelium. The emphasis is on histogenesis of bladder neoplasia, its putative precursor lesions, and its noninvasive forms. Areas of controversies are highlighted, and the pertinent clinical features, histological findings, and biological potential of these lesions examined.

Coatings of hexagonal ferrites on a wire antenna reduce its back-scattering radar cross-sections (r.c.s.) at microwave frequencies without causing significant deterioration of its radiation efficiency at the h.f. and v.h. communication bands. The back-scattering r.c.s. of an infinitely long conducting cylinder coated with a multilayer of hexagonal ferrites is derived and the result modified to take account of the finite length of a monopole antenna. Computed results for layered coatingsare presented to demonstrate the improvement in the microwave absorption bandwidth obtainable for a given coating thickness. It follows that the technique is best applied with all material and geometric parameters having tapered distribution and the ferrimagnetic resonances staggered over the required frequency band. Finally, the theory is illustrated by the measurement of the backscattering losses of a v.h.f. ferrite-coated antenna in the microwave frequency band (for both TM and TE polarizations of the incident waves) and its radiation performance at the v.h.f. range

A study of the generation of intermodulation products due to nonlinearities in braided coaxial cables at L-, S-and C-band frequencies is in progress and some results are presented. The different cable parameters responsible for intermodulation products at microwave frequencies have been examined and their relative contributions towards the total nonlinearities assessed.

The lack of suitable materials having permeabilities (μr) greater than unity at microwave frequencies has previously made it difficult to design thin coatings of broadband radar absorbersat this frequency range. A possible solution is to utilize the hexagonal ferrites that exhibit significant μrvalues (5) over narrow frequency bands and this paper investigates methods of deploying this material to design thin broadband microwave absorbers. Several techniques are evolved involving layering of the materials and staggering of the material electrical parametersand dimensions to achieve a good match ofthe incident waves. The computed results are substantiated by measurements of the manufacturedmaterials; measurement techniques and details of the materials used are given in appendices. It is established that a planar absorbent sheet having a reflection loss > 10 dB over 5–20 GHz is realizable within a practically acceptable thickness.