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This study addresses the complementary metal-oxide-semiconductor-compatible fabrication of vertically stacked Si/SiO2/Si nanopillars (NPs) with embedded Si nanodots (NDs) as key functional elements of a quantum-dot-based, gate-all-around single-electron transistor (SET) operating at room temperature. The main geometrical parameters of the NPs and NDs were deduced from SET device simulations using the nextnano++ program package. The basic concept for single silicon ND formation within a confined oxide volume was deduced from Monte-Carlo simulations of ion-beam mixing and SiO x phase separation. A process flow was developed and experimentally implemented by combining bottom-up (Si ND self-assembly) and top-down (ion-beam mixing, electron-beam lithography, reactive ion etching) technologies, fully satisfying process requirements of future 3D device architectures. The theoretically predicted self-assembly of a single Si ND via phase separation within a confined SiO x disc of 3 volume was experimentally validated. This work describes in detail the optimization of conditions required for NP/ND formation, such as the oxide thickness, energy and fluence of ion-beam mixing, thermal budget for phase separation and parameters of reactive ion beam etching. Low-temperature plasma oxidation was used to further reduce NP diameter and for gate oxide fabrication whilst preserving the pre-existing NDs. The influence of critical dimension variability on the SET functionality and options to reduce such deviations are discussed. We finally demonstrate the reliable formation of Si quantum dots with diameters of less than 3 nm in the oxide layer of a stacked Si/SiO2/Si NP of 10 nm diameter, with tunnelling distances of about 1 nm between the Si ND and the neighboured Si regions forming drain and source of the SET.

This study analyzes feasibility of complementary metal–oxide–semiconductor (CMOS)-compatible manufacturing of a hybrid single electron transistor–field effect transistor (SET-FET) circuit. The fundamental element towards an operating SET at room temperature is a vertical nanopillar (NP) with embedded Si nanodot generated by ion-beam irradiation. The integration process from NPs to contacted SETs is validated by structural characterization. Then, the monolithic fabrication of planar FETs integrated with vertical SETs is presented, and its compatibility with standard CMOS technology is demonstrated. The work includes process optimization, pillar integrity validation, electrical characterization and simulations taking into account parasitic effects. The FET fabrication process is adapted to meet the requirements of the pre-fabricated NPs. Overall, this work establishes the groundwork for the realization of a hybrid SET-FET circuit operating at room temperature.

Directed Self-Assembly (DSA) of Block Copolymers (BCP) by chemo-epitaxial alignment is a promising high resolution lithography technique compatible with CMOS high-volume manufacturing. It allows overcoming limitations in resolution and local stochasticity by conventional, imaging based, lithography. However, for BCP with pitches below 20 nm and guide patterning by immersion lithography (193i), multiplication factors ≥ 4 become necessary, imposing stringent requirements on the guides and defectivity becomes hard to control. The Arkema-CEA (ACE) process flow overcomes this limit by creating the guides by a self-aligned double patterning (SADP) process flow, followed by the deposition of a cross-linkable neutral mat and selective grafting of the guides. This paper reports on the transfer of the process flow to immersion lithography, details challenges encountered in process optimization, notably the dependence of the wetting of the neutral layer on the surface energy and the morphology of the spacers. Last, the paper presents a metrology and defectivity roadmap combined with preliminary, promising results.

International audience; SETs (Single-Electron-Transistors) arouse growing interest for their very low energy consumption. For future industrialization, it is crucial to show a CMOS-compatible fabrication of SETs, and a key prerequisite is the patterning of sub-20 nm Si Nano-Pillars (NP) with an embedded thin SiO2 layer. In this work, we report the patterning of such multi-layer isolated NP with e-beam lithography combined with a Reactive Ion Etching (RIE) process. The Critical Dimension (CD) uniformity and the robustness of the Process of Reference are evaluated. Characterization methods, either by CD-SEM for the CD, or by TEM cross-section for the NP profile, are compared and discussed.

Directed Self-Assembly (DSA) of Block Copolymer (BCP) is a promising lithography approach to achieve high resolution pattern dimensions. The current chemo-epitaxy process used to induce block copolymer self-alignment is showing today its limitations. This is due to the resolution limitation of conventional lithography technics needed for the guide formation, used to achieve BCP alignment. This paper introduces a new chemo-epitaxy process, named ACE (Arkema-CEA), which is based on sidewall image transfer (SIT) patterning. This process has the great advantage to offer guides of small critical dimension (CD) and pitch that allows the integration of high χ BCP. In this paper, different parameters of the ACE process are investigated (commensurability, spacer CD …) in order to precisely determine the DSA process window defining the best conditions for BCP alignment. Process window with multiplication factor ranging from 2 to 4 are obtained on BCP under investigation.

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International audience; The development of multiple e-beam lithography equipment is seen as an alternative for next generation lithography. However, similarly to EUV lithography, this technology faces important challenges in controlling the contamination of the optics due to deposition of carbon layer induced by the outgassed chemical species from resist under electron bombardment. An experimental setup was designed and built at LETI to study the outgassed species and observe the carbon layer. In this setup, resist coated wafers 100 mm size are exposed under a 5 kV e-beam gun. During exposure, byproducts from outgassed species are monitored with a Residual Gas Analyzer (RGA). The identification of outgassed chemical species is done with an ex-situ TD-GC-MS analysis (ThermoDesorption-Gaz Chromatography-Mass Spectrometry). In a second part of this investigation, we observed the contamination carbon layer growth induced by the outgassing. Thereby, we fabricated a device which consists of a silicon membrane with micro-machined apertures. During e-beam exposure, this device simulates the multiple parallel beams of the optic system of a maskless lithography tool. The deposited contamination layer on device is then observed and thickness measured under SEM. In this paper, we present the results of outgassing and contamination on 3 chemically amplified resists showing that contamination is not directly dependent of the overall outgassing rate but on first order of the outgassing from Photo Acid Generator (PAG). It also reports on the performance in reducing outgassing and contamination of applying a top-coat layer on top of the resist and shows that reduction is more important for contamination than for outgassing.

International audience