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A 28 nm CMOS software-defined transceiver (SDTRX) enabling high-speed data (HSD) streaming, including ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024-QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the-art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a digital-to-analog converter-based TX and a smart phase-locked loop system. It operates over 0.4–1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple transmitter (TX) to receiver (RX) loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia system-on-chip and is, to the authors’ knowledge, the first reported transceiver front-end to enable true HSD streaming within home cable networks.

A 28 nm CMOS Software-Defined Transceiver (SDTRX) enabling High-Speed Data (HSD) streaming, including Ultra HD TV, within home cable networks is presented. By making efficient use of available cable bandwidth, the SDTRX dynamically handles up to 1024QAM OFDM-modulated HSD streams. This paper addresses SDTRX system-level design methodology as the key driver in enabling performance optimization for achieving a wide frequency range of operation at the lowest power and area consumption. By employing an optimized architecture constructed on available state-of-the art 28 nm functional building blocks, the monolithic SDTRX consists of a mixer-based harmonic rejection RX with a DAC-based TX and a smart PLL system. It operates over a 0.4-to-1.7 GHz frequency range while consuming less than 475 mW in half-duplex mode. Moreover, by developing a simple TX-RX loopback circuit, the system is enabled to efficiently calibrate TX output power and to remove the need for a dedicated external pin. This low-cost SDTRX is embedded in various 28 nm CMOS multimedia SoCs and is, to the authors' knowledge, the first reported transceiver front end to enable true high-speed data streaming within home cable networks.

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.

A 28 nm CMOS software-defined receiver front end (SDRX) for the analog signal conditioning of high-speed data streams on cable is presented. By making efficient use of the available cable bandwidth, the presented SDRX is, to the authors' knowledge, the first reported receiver front end to enable high-speed data and Ultra-HDTV video streaming within home cable networks. This paper focuses on the SDRX system-level design methodology as the key factor in finding the most effective circuit-level solutions for power and area optimization. Its direct result is that we have implemented the most power-efficient SDRX architecture for the 28 nm CMOS process, and we have developed enhanced building blocks to optimize further the system performance. The optimal filtering strategy defines the harmonic rejection feature to reduce the external filter complexity and cost, and it also finds the appropriate ADC resolution and speed to reduce the baseband low-pass filter power and area. The SDRX gain partitioning strategy maximizes the output SNR by making sure both the mixer and baseband ADCs are fully loaded. Thus, enhanced gain blocks have been designed to accommodate a < 1 dB gain step. The presented monolithic SDRX is embedded in 28 nm CMOS multimedia SoCs, and it can cover frequency bands up to 1800 MHz and channel bandwidths up to 225 MHz. The success of the top-down design approach is validated by the 265/180 mW power consumption for 225/100 MHz signal bandwidth.

The IEEE 802.3an standard describes full-duplex 10Gb/s Ethernet transmission over four pairs of up to 100m UTP cable. The performance required from the analog front end (AFE) of a 10GBASE-T Ethernet transceiver strongly depends on the length of the cable connected to it. Maximum-length cables require the highest performance, and hence, determine the worst-case power dissipation of the transceiver. In practice, however, the vast majority of cable lengths used are below 30m. For these shorter cables, the standard specifies the transmitted power level to be lowered, inherently leading to a reduction in power consumption of the transmitter (TX). In most designs, the power consumption of the receiver (RX), unfortunately, does not benefit from the shorter cable lengths [1,2]. This paper presents a power-efficient 13b RX, implemented in 28nm CMOS. By switching to a 10b mode for short cables, 143mW is saved in the AFE for one complete Ethernet port, comprising four receivers. In addition, to further reduce power, the RX heavily relies on calibrations.

The increased competition to deliver broadband data to the home (including GPON and VDSL) is motivating cable providers to deliver data rates which far exceed what is presently available based on the DOCSIS 1.x and DOCSIS 2.0 standards. The DOCSIS 3.0 standard provides this bandwidth increase as well as additional flexibility, where higher data throughput can be obtained by bonding together multiple downstream (DS) channels. This standard calls for the ability to bond any 4 channels in a 64MHz contiguous RF bandwidth. Solutions that allow even more channel bonding and provide more flexibility in the allocated frequency spectrum are preferred. This paper reports an embedded dual-tuner architecture able to select two independent 32MHz frequency bands, allowing for a maximum of 10 demodulated 6MHz Annex B DS channels. In Fig. 6.6.1 the top level block diagram is shown: an external LNA amplifies the RF signal which drives an internal splitter, followed by the two low-IF tuners. Each tuner downconverts 5 DS channels to IF frequencies centered at 0MHz (CH 0), +6MHz (CH +1), +12MHz (CH +2), −6MHz (CH −1) and −12MHz (CH −2). Channels +1 and +2 lie at the images of channels −1 and −2 respectively. Any or all channels can be selected for demodulation by the SoC, up to a maximum of eight. Image rejection is enhanced digitally, taking advantage of the tuner integration into the SoC.

A complete analog front-end, with the exclusion of the frequency synthesizer, for FM broadcasting occupies 2.8 mm 2 active area in a standard 0.35 μm CMOS technology. The use of current driven passive mixer and switch capacitor polyphase filter gives +100 dBμV IIP3, 52 dB adjacent channel selectivity and +39 dB image rejection without trimming or tuning. The output noise is 390 nV//√Hz, with a conversion gain of about 39 dB. This front-end consumes only 5 mA from a 2.4 V supply © 2006 IEEE.