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This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180 GΩ and 700 GΩ were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz.

ISFETs (ion sensitive field effect transistors) are ion solid-state sensors based on MOSFETs (metal oxide semiconductor field effect transistors) applied in many areas including ion imaging, detection of viruses and bacteria and DNA sequencing. ISFETs implemented in standard CMOS technology adopt the inherent Si3N4 passivation as the sensing layer, and benefit from a high integration level with no need of post-processing steps. However, this implementation is associated with non-idealities such as output temporal drift, capacitive attenuation of the input signal and random offsets in the threshold voltage due to trapped charges. Most of these non-idealities, which require better understanding, are characterized through biasing a reference electrode immersed in a solution in contact with the passivation layer. To remove electrochemical effects from the measurements, this paper proposes a dry test where the wet test setup is replaced with a sputtered gold thin film that provides electrical contact with the ISFETs. Dry tests were performed in arrays of n-ISFETs and p-ISFETs from chips fabricated in a standard 180 nm high voltage CMOS technology. The intra-die threshold voltages of the n-ISFETs and p-ISFETs presented, on average, similar offsets, but their die-to-die fluctuation was high. Wet tests on an n-ISFET and a p-ISFET of two non-metalized chips indicated sensitivities of 38 mV/pH and 46 mV/pH, respectively. The dry test introduced herein allows the electrical parameters of ISFETs to be determined without the interference of chemical contributions as well as the charges trapped in the passivation layer to be estimated.

A DC-DC boost converter for ultra-low-voltage thermal energy harvesting is presented herein. The focus of this brief is to provide both self-startup and efficient conversion at ultra-low input voltages. The converter startup is achieved through the use of a cold starter based on an ultra-low-voltage oscillator and a charge pump. The inductive boost converter architecture uses two low-side switches in order to independently optimize the low-voltage startup and the steady-state conversion efficiency. The model of the developed converter allows optimization of the boost switches as a function of the TEG internal resistance and input voltage. A zero current switching circuit with accurate detection for low input voltages is designed and implemented. The prototype fabricated in 130 nm standard CMOS technology achieves startup for an input voltage of 11 mV and, once started, the system can perform the boost operation for input voltages as low as 7.3 mV, delivering 50% of end-to-end efficiency at 10.5 mV and peak end-to-end efficiency of 85% at 140 mV.

This brief describes a compact test chip in a 130-nm CMOS technology, aimed at characterizing both the short- and long-channel transistors and the series association of halo-implanted transistors. The chip contains a set of low-threshold-voltage (LVT) nMOS/pMOS transistors with several channel lengths and transistors associated in series. Parameters, such as threshold voltage, specific current, and intrinsic voltage gain, were determined through simulation and measurements of 20 chips. The results reported herein provide integrated circuit designers with guidelines for choosing either long-channel lengths or series association of transistors to comply with the requirements of their design.

The Internet of Things paradigm considers the deployment in the environment of a profusion of heterogeneous sensor nodes, connected in a complex network, and autonomously powered. Energy harvesting is the common proposed solution to supply such sensors, and many different sources such as light, mechanical vibrations, temperature differences can be considered individually or in combination. Specifically, a thermoelectric generator (TEG), taking advantage of the Seebeck effect, is able to harvest electrical power from a temperature gradient of a few degrees. This study presents a chip fabricated in 130 nm CMOS technology, designed to convert a typical 50 mV output from a TEG into 1 V. The batteryless design utilises both halves of a 50% duty cycle clock. Measurements have been performed by using a TEG, and an equivalent TEG model, i.e. voltage source (50 mV-200 mV) with a series resistance of 5 Ω. The result shows that the proposed prototype can extract 60% (at 50 mV) to 65% (at 200 mV) of the total available power. The energy harvester can self-start at 50 mV with a 2.8 ms startup time, which is a significant improvement over the past work.

This paper presents the design and testing of a self-biased current source. The design described in this paper is based on the concept of inversion coefficient, which allows a direct calculation of the dispersion in the output current in terms of the internal bias errors and transistor mismatch. The circuit was fabricated in a standard CMOS 180 nm technology.

The ISFET (Ion Sensitive Field Effect Transistor) is a structure based on the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is capable of measuring ionic concentration of a solution. The ISFET has been used for such areas as DNA sequencing, viruses and bacteria detection. The basic idea behind the ISFETs emerged in 1970, but a deeper understanding of some of its non-idealities and the development of architectures to reduce their effects are still needed. For that reason, this work revisits the basic principles of ISFET operation. The ISFET modeling using the binding site theory, Gouy-Chapman-Stern model and the Advanced Compact Model of the transistor is introduced and implemented in Matlab®. Furthermore, the details of a chip designed on the Virtuoso® platform, aimed at characterizing the ISFETs on the SilTerra D18V technology, are presented. Simulation results estimate an average sensitivity of 45.3 mV/pH for the designed devices over a pH range from 1 to 10. The chip sent for fabrication was kindly supported by Chipus Microeletronica S.A. and SilTerra Malaysia Sdn Bhd.

A compact presentation of the basic theory of the MOS transistor is given. Instead of the usual approach of furnishing separate analytical formulas for the strong and weak inversion regions of the MOS transistor, we provide simple formulas which are valid in all operating regions, including moderate inversion. We review ultra-low-power circuits operating near the threshold condition that allow the automatic extraction of the specific current IS and the threshold voltage VT of MOS transistors, which are the most fundamental parameters for technology characterization, circuit design, and testing.

This paper presents an enhanced-swing Colpitts oscillator that operates from supply voltages below 4kT/q. The oscillation frequency, start-up condition, and amplitude of oscillation were analyzed. The condition for the minimum voltage gain, extended to the minimum supply voltage, required for operation of the Colpitts oscillator is derived. Measurement results obtained for a prototype integrated in the IBM 130 nm technology demonstrate the operation of the oscillator with 86 mV of supply voltage.

This paper describes an efficient method to explore the design space of AC/DC converters for energy harvesting circuits. A simple analytical model of the rectifier circuit valid down to ultra-low-voltage operation (input voltage below the thermal voltage) is proposed. Based on the Shockley diode equation, the use of an optimization equation that relates the number of stages of the rectifier to the saturation current of the diodes is demonstrated. A set of universal normalized curves to guide the designer regarding the minimum available power from the AC power source is presented. Three rectifiers with different numbers of stages and saturation currents along with matching networks integrated in a 130 nm CMOS technology demonstrated a conversion efficiency of around 10% for an available power of around $-$ 20 dBm and DC load voltage and current of 1 V and 1 $\mu{\rm A}$ , respectively.

Purpose This paper presents a low-cost MOSFET dosimeter suitable for in vivo radiotherapy applications. We analyze different methods to extract the threshold voltage and how this extraction is affected by the dose dependence of slope factor and carrier mobility. Also, we discuss fundamental aspects of the basic building blocks of a MOSFET dosimeter, namely, the radiation sensor, the reader circuit and temperature desensitization. Methods Experiments with ionizing radiation (6 MV X-ray beams) were carried out at the Centro de Pesquisas Oncologicas (CEPON) using linear accelerators to test the MOSFET dosimeter. Results The main performance parameters of the dosimeter prototype are radiation sensitivity about 100 mV/Gy (sensor's sensitivity is around 6.7 mV/Gy), thermal dependence of 0.5 cGy/°C, reproducibility is about 2.6%, and radiation beam attenuation of 0.14%. Conclusions The MOSFET dosimeter described in this article, which combines a simple and accurate readout procedure with a small size, low-cost, cable/battery-free sensor and very little attenuation of the radiation beam is a very appealing option for in vivo dosimetry.

A prototype chip fabricated in 130 nm CMOS technology, designed to extract maximum power from a thermoelectric generator (TEG) is presented. In the measurements, the TEG is modelled by a voltage source (V TEG) with a series resistance of 5 Ω. The prototype is fully electric, starts from V TEG = 50 mV and it can extract 60% (at 50 mV) to 65% (at 200 mV) of the available power. Also by using present circuit schematic, an improved transient response of 3 ms (at 50 mV) and startup voltage of 50 mV is achieved.

A superconducting magnetic energy storage (SMES) is an attractive power supply for electromagnetic rail launchers (EMRL), which require pulse currents to launch projectiles at very high speeds. Moreover, the accelerating force in an EMRL may be enhanced by adding a background field, a principle known as launcher S3EL concept (Superconducting Self-Supplied Electromagnetic Launcher) consists in using the SMES both as a power supply and for background field generation. The challenge is to reach the operating current and peak magnetic field of such launchers, which can be up to hundreds of kA and up to 10 T. The use of a high-temperature superconductor is mandatory to maintain superconducting operation during a launch, though operation at 4.2 K is foreseen to benefit from the RareEarth-BaCuO (REBCO) tape high critical current densities. The aim of this work is to derive a practical design for a 1-m-long small-scale S3EL proof of concept using REBCO coated conductor, with a reduced output velocity (100 m/s). After preliminary sizing studies, the spatial constraints for the SMES-Launcher integration is presented. A parametric joint analytical and Finite Element Method (FEM) study is conducted to refine the design and maximize the operation margins while maintaining the launch performances. Finally, cable design and discharge method suitable to reach the required operating current are presented.

This paper presents two fully integrated inductive ring oscillators that operate with supply voltages below 2kT/q for energy harvesting applications. Expressions for the oscillation frequency as well as the minimum transistor gain and supply voltage required for the starting up of oscillations are derived for each topology. The experimental results for two cross-coupled oscillators, with topologies comprised of a single-inductor and two-inductors per stage, are presented. The two oscillators operate with supply voltages as low as V DD = 46 mV at 11.5 µW DC power and V DD = 31 mV at 15 µW DC power, respectively, thus confirming the extremely low voltage operation of the prototypes integrated in a 130 nm technology.

This letter presents MOS analog circuits that can operate with very low supply voltages. Operation of the MOS transistor in the triode region is emphasized owing to the limited voltages available. Special attention has been given to the properties of the zero-VT transistor due to its high drive capability at low voltages. Simulation and measurement results for a Colpitts oscillator prototype set up around a zero-VT MOSFET demonstrated that the oscillator operates with supply voltages lower than the thermal voltage kT/q. Finally, ultra-low-voltage rectifiers using diodes or diode-connected MOSFETs operating in weak inversion are analyzed.

This paper exploits a universal current-based definition of the threshold voltage (V"T) and discusses some direct methods to measure it. The consistency, accuracy, and sensitivity of the extraction procedures to second-order effects are examined through numerical simulations and experimental measurements. In addition to three procedures based on dc current measurements we propose an automatic V"T-extractor circuit which allows the direct determination of the threshold voltage with minimum influence of second-order effects.

This paper describes a simple analytical model of the rectifier circuit valid down to very low voltage operation (input voltage below the thermal voltage). Steady-state and transient analyses of the rectifier with the diode described by an exponential I-V characteristic are presented. We provide formulas for the dc output voltage level, the output voltage ripple, and the power conversion efficiency. We also give a compact expression for the charging time of the load capacitor. The models of the rectifier and the voltage doubler for input voltages down to the thermal voltage are verified with simulations and measurements using circuits built with off-the-shelf 1N4148 diodes.

In this work we apply the current-based threshold voltage definition (equality between the drift and diffusion components of drain current) to intrinsic symmetric double-gate MOSFETs. We show that the half maximum point of the gm/ID (transconductance-to-current ratio) curve in the linear region corresponds exactly to the condition IDdrift = I Ddiff when mobility variation is neglected. Numerical simulations show that the threshold voltages determined from the gm/ID curve and from the IDdrift = IDdiff condition differ by about φt/2 (one half of the thermal voltage) when considering realistic mobility variations. Simulation results show that the threshold voltages determined with the gm/ID procedure are close to those obtained with the Y (=ID/gm) function method for a considerable range of silicon film thicknesses, channel lengths, and temperature values. The current-based procedure has also been successfully applied experimentally to a FinFET over a wide temperature range. © 2010 Elsevier Ltd. All rights reserved. 56 1 89 94

The authors propose a four-quadrant multiplier based on a core cell that exploits the general relationship between the saturation current of an MOS transistor and the source inversion charge density, valid from weak to strong inversion. The advantages of the proposed circuit are simplicity, low distortion and feasibility of low-voltage operation. Experimental results in a 0.35 mum CMOS prototype indicate 1 mA consumption for 1 MHz bandwidth, and distortion level below 1 for an input current of 80 of the full-scale range. The multiplier core area is around 10 000 m 2 .