29 results on '"Lyu, Liangjian"'
Search Results
2. A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR
3. A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback
4. A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces
5. Stretch‐Tolerant Waterproof and Self‐cleaning CBNPs/Graphene Strain Sensor for Multifunctional Applications
6. A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros
7. A chopper amplifier with a low duty‐cycle sub‐sampling in the switched‐capacitor integrator for noise reduction
8. A 19-$\mu$W Blocker-Tolerant Wake-Up Receiver With $-$90-dBm Energy-Enhanced Sensitivity
9. Review of the Intelligent Sensor‐Memory‐Control Fusion Systems
10. A 19-μW Blocker-Tolerant Wake-Up Receiver With −90–dBm Energy-Enhanced Sensitivity
11. Waterproof and Breathable Graphene‐Based Electronic Fabric for Wearable Sensors
12. High Throughput In–Situ Temperature Sensor Array with High Sensitivity and Excellent Linearity for Wireless Body Temperature Monitoring
13. Flexible Pressure Sensor Array with Multi-Channel Wireless Readout Chip
14. An in Situ Embedded System for Electrocardiography and Photoplethysmography Acquisition
15. Graphene‐Based Hydrogel Strain Sensors with Excellent Breathability for Motion Detection and Communication
16. A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range
17. High‐performance flexible humidity sensors for breath detection and non‐touch switches
18. An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording
19. A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification
20. A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS
21. A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction
22. A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation
23. A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission
24. A 2.46GHz, −88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer
25. A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply
26. A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology
27. A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power
28. Review of the Intelligent Sensor‐Memory‐Control Fusion Systems
29. An in situdigital background calibration algorithm for multi-channel R-βR ladder DACs
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.