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Due to the rapid growth of the data traffic and the integration density of systems, the electromagnetic compatibility (EMC) of communication circuits is increasingly challenging to accomplish. In modern data centers, thousands of paralleled backplane communication links enable the tremendous volume of data throughput. However, these backplane links also generate undesired electromagnetic interference (EMI), which can potentially cause system malfunction. In a typical backplane communication link, differential non-return-to-zero (NRZ) signaling has been widely used for years. However, non-linear distortion of differential NRZ signals leads to a large common-mode (CM) noise at the double Nyquist frequency, which is a primary source of EMI. Therefore, the first half of the thesis focuses on investigating the CM noise of NRZ signals to understand the EMI issue in high-speed backplane links. Similar to the NRZ signaling, 4-level pulse amplitude modulation (PAM-4), which is the key solution for the next generation of 200/400 GbE communications, also suffers from the similar EMI problems. Hence, the second half of the thesis focuses on the EMI-related CM noise of PAM-4 signals. In the first half, the analysis of EMI-related CM noise of differential NRZ signals is presented from a circuit design perspective. A current-mode logic (CML) driver circuit is used for analysis and simulations. It is observed that the CM noise is correlated with the data rate, amplitude, and mismatch of rising and falling edges. Accordingly, a method for EMI reduction is proposed by optimizing the signal swing and the biasing voltage of the circuit. The proposed method is experimentally verified on a test chip fabricated in a 65 nm CMOS process. In the second half, the analysis of PAM-4 signals is presented, showing a correlation between the EMI-related CM noise and the system architecture. It is observed that the CM noise of a PAM-4 transmitter with a thermometer-coded architecture is intrinsicall

This paper presents an analysis for the electromagnetic interference (EMI) related common-mode (CM) noise in differential high-speed data links with different signal modulation schemes, e.g. non-return-To-zero (NRZ) and 4-level pulse amplitude modulation (PAM-4). The CM noises, introduced by the mismatch of data rising and falling edges in both cases, exhibit the similar positive correlation with signal swing, but due to the complexity of PAM-4 signal, the amplitude distortion leads to different CM noise behavior. © 2017 IEEE.

A fully integrated optical-to-wireless modulator for low-cost fiber-optical backhaul links is presented in this paper. In the receiver, a CMOS photodetector with a bandwidth of 0.5 GHz is integrated to perform optical-to-electrical conversion. A gain-boosted inverter based transimpedance amplifier achieves a high gain-bandwidth product without using inductive peaking. The two-stage equalizer compensates the photodetector bandwidth and extends the operation data rate to 4 Gb/s. The wireless modulator directly up-converts and modulates the baseband I/Q NRZ data to a QPSK signal centered at 60 GHz. Realized in 65-nm CMOS, the optical front-end achieves -3-dBm optical input sensitivity at 4 Gb/s with 10mathrm -12 BER. The modulator produces -7.2-dBm output power with -12-dB EVM at a bit efficiency of 19.6 pJ/b. This design demonstrates that a small form factor and low cost optical-to-millimeter-wave modulator can be realized to support future fiber-wireless networks. © 2004-2012 IEEE.

This brief presents, for the first time, a comprehensive analysis and prediction of electromagnetic interference (EMI)-related common-mode (CM) noise for a 20- Gb/s source-series terminated (SST) I/O driver in a 65-nm CMOS process. The novel methodology is proposed to systematically analyze and predict the CM noise of an output driver from various dependent parameters, including CMOS process corners, input signal, power supply and passive interconnections. Analysis reveals that the non-linear active circuit predominantly produces an asymmetric rise and fall time of the output signal and is an intrinsic source responsible for generating the CM noise. For the SST driver, due to the push-pull NMOS-PMOS configuration, CM noise level variations are aggravated under process corners. The post-layout simulation results indicate that the critical step in controlling the CM noise is at the source, rather than improving the matching of passive interconnections. The presented methodology can also be applied to other serializer/deserializer (SERDES) I/O drivers.

The rise/fall time mismatch in a differential signal is responsible for a serious common-mode (CM) issue in high-speed CMOS serializer/deserializer (SERDES) transmitters (Txs). The non-linear parasitic impedance variations of the switching devices and differences in parasitic impedances in the charging and discharging loop produce deterministic spurs on the CM voltage that generate certain spectral tones at twice the Nyquist frequency, causing the electromagnetic compatibility (EMC) failure. The CM radiation is generally more significant than differential-mode (DM) radiation, and therefore suppressing CM noise is essential for improving EMC performance. This paper presents a new circuit design perspective to address the CM noise issue in a source-series terminated (SST) output driver by calibrating parallel impedance scaled SST stages. Simulated in a 65-nm CMOS process, our results indicate that adjusting the MOS devices circumvents the CM noise by more than 65% in the worst case scenario as it affects most of the output CM noise profile. © 2017 IEEE. All rights reserved.

This work presents a self-Adaptation algorithm to automatically adjust the peaking settings of a continuous-Time linear equalizer (CTLE) in a high-speed PAM4 receiver. A statistical approach is adopted to improve the robustness and flexibility of the adaptation algorithm. The PAM4 top level distribution around the peak value of several consecutive top levels guides the CTLE to attain the optimal digital settings. By performing the peak detection at the output of the equalization summer, the effect of digital equalization is inherently accounted for by the proposed algorithm. To demonstrate the effectiveness of the proposed algorithm, a PAM4 receiver employing two stages of CTLE and 1-Tap feed forward equalizer (FFE) is designed to compensate up to 11.8-dB channel loss for a data rate of 56 Gb/s. © 2017 IEEE.

This paper presents a compact 4:1 ratio transformer-based balun design in 65-nm CMOS process. The insertion loss is lower than 1.5 dB from 56 GHz to 64 GHz. The balun also serves as a matching network between the output of mixer and chip output terminal. By choosing appropriate inductance ratio and mutual coupling coefficient, the impedance transforms from (52.9+j85.8) Ω to (29.1+j4.7) Ω. Cascade ABCD parameter de-embedding technique is applied to remove the connection parasitic effects in the testing structure.

This paper presents, for the first time, an optical-to-mm-wave modulator SoC with an integrated 850-nm wavelength optical receiver front-end for short-range backhaul connectivity in emerging fiber-wireless mobile networks. Realized in 65-nm CMOS, the optical front-end achieves -3dBm optical input sensitivity at 4Gb/s with 10-12 BER. The modulator directly up-converts the de-multiplexed 2Gb/s I/Q NRZ data to a 4Gb/s QPSK signal at 60GHz. The SoC consumes 78mW and produces -7.2dBm output power with -12dB EVM at a bit efficiency of 19.6pJ/b. © 2015 IEEE.

This paper presents the ongoing research efforts in optical communication transceiver SoC design for emerging fiber-wireless mobile networks and next generation 200/400GbE optical networks using advanced CMOS technologies. First, a 4-Gb/s fiber-to-mm-wave baseband-over-fiber (BoF) modulator SoC using 65-nm CMOS with a fully integrated 850-nm wavelength optical receiver front-end for short-range wireless backhaul connectivity is reviewed. Next, design considerations for an improved 10-Gb/s BoF I/Q modulator SoC with integrated 60-GHz power amplifier is described. Lastly, a novel PAM4/NRZ transceiver architecture featuring BER built-in-self-test is discussed.