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1. A Front-End Circuit in 28 nm CMOS for Hydrogenated Amorphous Silicon Detectors in Clinical Dosimetry.

Author

Giovanni Mazza, Lorenzo Piccolo, Luca Antognini, Saba Aziz, Aishah Bashiri, Lucio Calcagnile, Daniela Calvo, Domenico Caputo, Anna Paola Caricato, Roberto Catalano, Roberto Cirio, Giuseppe Antonio Pablo Cirrone, Tommaso Croci, Giacomo Cuttone, Gianpiero De Cesare, Paolo De Remigis, Sylvain Dunand, Michele Fabi, Luca Frontini, Catia Grimani, Mariacristina Guarrera, Maria Ionica, Keida Kanxheri, Matthew Large, Francesca Lenta, Valentino Liberali, Nicola Lovecchio, Maurizio Martino, Giuseppe Maruccio, Mauro Menichelli, Anna Grazia Monteduro, Arianna Morozzi, Francesco Moscatelli, Augusto Nascetti, Stefania Pallotta, Daniele Passeri, Maddalena Pedio, Marco Petasecca, Giada Petringa, Francesca Peverini, Pisana Placidi, Gianluca Quarta, Silvia Rizzato, Federico Sabbatini, Leonello Servoli, Alberto Stabile, Cinzia Talamonti, Jonathan Emanuel Thomet, Luca Tosti, Mattia Villani, Richard James Wheadon, Nicolas Wyrsch, and Nicola Zema

Published
2024
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2. Single-Photon Detectors for Quantum Integrated Photonics

Author

Thu Ha Dao, Francesco Amanti, Greta Andrini, Fabrizio Armani, Fabrizio Barbato, Vittorio Bellani, Vincenzo Bonaiuto, Simone Cammarata, Matteo Campostrini, Samuele Cornia, Fabio De Matteis, Valeria Demontis, Giovanni Di Giuseppe, Sviatoslav Ditalia Tchernij, Simone Donati, Andrea Fontana, Jacopo Forneris, Roberto Francini, Luca Frontini, Gian Carlo Gazzadi, Roberto Gunnella, Ali Emre Kaplan, Cosimo Lacava, Valentino Liberali, Leonardo Martini, Francesco Marzioni, Claudia Menozzi, Elena Nieto Hernández, Elena Pedreschi, Paolo Piergentili, Paolo Prosposito, Valentino Rigato, Carlo Roncolato, Francesco Rossella, Matteo Salvato, Fausto Sargeni, Jafar Shojaii, Franco Spinella, Alberto Stabile, Alessandra Toncelli, Gabriella Trucco, and Valerio Vitali

Subjects
quantum information, integrated photonics, single-photon detectors, Applied optics. Photonics, TA1501-1820
Abstract

Single-photon detectors have gained significant attention recently, driven by advancements in quantum information technology. Applications such as quantum key distribution, quantum cryptography, and quantum computation demand the ability to detect individual quanta of light and distinguish between single-photon states and multi-photon states, particularly when operating within waveguide systems. Although single-photon detector fabrication has been established for some time, integrating detectors with waveguides using new materials with suitable structural and electronic properties, especially at telecommunication wavelengths, creates more compact source-line-detector systems. This review explores the state of the art of single-photon detector research and examines the potential breakthroughs offered by novel low-dimensional materials in this field.

Published
2024
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3. Mobility Gaps of Hydrogenated Amorphous Silicon Related to Hydrogen Concentration and Its Influence on Electrical Performance

Author

Francesca Peverini, Saba Aziz, Aishah Bashiri, Marco Bizzarri, Maurizio Boscardin, Lucio Calcagnile, Carlo Calcatelli, Daniela Calvo, Silvia Caponi, Mirco Caprai, Domenico Caputo, Anna Paola Caricato, Roberto Catalano, Roberto Cirro, Giuseppe Antonio Pablo Cirrone, Michele Crivellari, Tommaso Croci, Giacomo Cuttone, Gianpiero de Cesare, Paolo De Remigis, Sylvain Dunand, Michele Fabi, Luca Frontini, Livio Fanò, Benedetta Gianfelici, Catia Grimani, Omar Hammad, Maria Ionica, Keida Kanxheri, Matthew Large, Francesca Lenta, Valentino Liberali, Nicola Lovecchio, Maurizio Martino, Giuseppe Maruccio, Giovanni Mazza, Mauro Menichelli, Anna Grazia Monteduro, Francesco Moscatelli, Arianna Morozzi, Augusto Nascetti, Stefania Pallotta, Andrea Papi, Daniele Passeri, Marco Petasecca, Giada Petringa, Igor Pis, Pisana Placidi, Gianluca Quarta, Silvia Rizzato, Alessandro Rossi, Giulia Rossi, Federico Sabbatini, Andrea Scorzoni, Leonello Servoli, Alberto Stabile, Silvia Tacchi, Cinzia Talamonti, Jonathan Thomet, Luca Tosti, Giovanni Verzellesi, Mattia Villani, Richard James Wheadon, Nicolas Wyrsch, Nicola Zema, and Maddalena Pedio

Subjects
amorphous hydrogenated silicon, photoemission, inverse photoemission, flexible substrate, radiation detector, Raman, Chemistry, QD1-999
Abstract

This paper presents a comprehensive study of hydrogenated amorphous silicon (a-Si)-based detectors, utilizing electrical characterization, Raman spectroscopy, photoemission, and inverse photoemission techniques. The unique properties of a-Si have sparked interest in its application for radiation detection in both physics and medicine. Although amorphous silicon (a-Si) is inherently a highly defective material, hydrogenation significantly reduces defect density, enabling its use in radiation detector devices. Spectroscopic measurements provide insights into the intricate relationship between the structure and electronic properties of a-Si, enhancing our understanding of how specific configurations, such as the choice of substrate, can markedly influence detector performance. In this study, we compare the performance of a-Si detectors deposited on two different substrates: crystalline silicon (c-Si) and flexible Kapton. Our findings suggest that detectors deposited on Kapton exhibit reduced sensitivity, despite having comparable noise and leakage current levels to those on crystalline silicon. We hypothesize that this discrepancy may be attributed to the substrate material, differences in film morphology, and/or the alignment of energy levels. Further measurements are planned to substantiate these hypotheses.

Published
2024
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5. X-ray qualification of hydrogenated amorphous silicon sensors on flexible substrate.

Author

Mauro Menichelli, Luca Antognini, Aishah Bashiri, Marco Bizzarri, Lucio Calcagnile, M. Caprai, Anna Paola Caricato, Roberto Catalano, Giuseppe Antonio Pablo Cirrone, Tommaso Croci, Giacomo Cuttone, Sylvain Dunand, Michele Fabi, Luca Frontini, Catia Grimani, Maria Ionica, Keida Kanxheri, Matthew Large, Valentino Liberali, Maurizio Martino, Giuseppe Maruccio, Giovanni Mazza, A. G. Monteduro, Arianna Morozzi, Francesco Moscatelli, Stefania Pallotta, A. Papi, Daniele Passeri, Maddalena Pedio, Marco Petasecca, Giada Petringa, Francesca Peverini, Lorenzo Piccolo, Pisana Placidi, Gianluca Quarta, Silvia Rizzato, G. Rossi, Federico Sabbatini, Alberto Stabile, Leonello Servoli, Cinzia Talamonti, Luca Tosti, Mattia Villani, Richard James Wheadon, Nicolas Wyrsch, and N. Zema

Published
2023
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6. Integrated Photonic Passive Building Blocks on Silicon-on-Insulator Platform

Author

Francesco Amanti, Greta Andrini, Fabrizio Armani, Fabrizio Barbato, Vittorio Bellani, Vincenzo Bonaiuto, Simone Cammarata, Matteo Campostrini, Thu Ha Dao, Fabio De Matteis, Valeria Demontis, Simone Donati, Giovanni Di Giuseppe, Sviatoslav Ditalia Tchernij, Andrea Fontana, Jacopo Forneris, Luca Frontini, Roberto Gunnella, Simone Iadanza, Ali Emre Kaplan, Cosimo Lacava, Valentino Liberali, Leonardo Martini, Francesco Marzioni, Luca Morescalchi, Elena Pedreschi, Paolo Piergentili, Domenic Prete, Valentino Rigato, Carlo Roncolato, Francesco Rossella, Matteo Salvato, Fausto Sargeni, Jafar Shojaii, Franco Spinella, Alberto Stabile, Alessandra Toncelli, and Valerio Vitali

Subjects
silicon-on-insulator, silicon photonics, integrated photonic circuits, optical interconnect, semiconductor, integrated waveguide devices, Applied optics. Photonics, TA1501-1820
Abstract

Integrated photonics on Silicon-On-Insulator (SOI) substrates is a well developed research field that has already significantly impacted various fields, such as quantum computing, micro sensing devices, biosensing, and high-rate communications. Although quite complex circuits can be made with such technology, everything is based on a few ’building blocks’ which are then combined to form more complex circuits. This review article provides a detailed examination of the state of the art of integrated photonic building blocks focusing on passive elements, covering fundamental principles and design methodologies. Key components discussed include waveguides, fiber-to-chip couplers, edges and gratings, phase shifters, splitters and switches (including y-branch, MMI, and directional couplers), as well as subwavelength grating structures and ring resonators. Additionally, this review addresses challenges and future prospects in advancing integrated photonic circuits on SOI platforms, focusing on scalability, power efficiency, and fabrication issues. The objective of this review is to equip researchers and engineers in the field with a comprehensive understanding of the current landscape and future trajectories of integrated photonic components on SOI substrates with a 220 nm thick device layer of intrinsic silicon.

Published
2024
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7. Hybrid Integrated Silicon Photonics Based on Nanomaterials

Author

Domenic Prete, Francesco Amanti, Greta Andrini, Fabrizio Armani, Vittorio Bellani, Vincenzo Bonaiuto, Simone Cammarata, Matteo Campostrini, Samuele Cornia, Thu Ha Dao, Fabio De Matteis, Valeria Demontis, Giovanni Di Giuseppe, Sviatoslav Ditalia Tchernij, Simone Donati, Andrea Fontana, Jacopo Forneris, Roberto Francini, Luca Frontini, Gian Carlo Gazzadi, Roberto Gunnella, Simone Iadanza, Ali Emre Kaplan, Cosimo Lacava, Valentino Liberali, Leonardo Martini, Francesco Marzioni, Claudia Menozzi, Elena Nieto Hernández, Elena Pedreschi, Paolo Piergentili, Paolo Prosposito, Valentino Rigato, Carlo Roncolato, Francesco Rossella, Andrea Salamon, Matteo Salvato, Fausto Sargeni, Jafar Shojaii, Franco Spinella, Alberto Stabile, Alessandra Toncelli, Gabriella Trucco, and Valerio Vitali

Subjects
integrated silicon photonics, nanostructured materials, hybrid photonic platforms, integrated photonic circuits, Applied optics. Photonics, TA1501-1820
Abstract

Integrated photonic platforms have rapidly emerged as highly promising and extensively investigated systems for advancing classical and quantum information technologies, since their ability to seamlessly integrate photonic components within the telecommunication band with existing silicon-based industrial processes offers significant advantages. However, despite this integration facilitating the development of novel devices, fostering fast and reliable communication protocols and the manipulation of quantum information, traditional integrated silicon photonics faces inherent physical limitations that necessitate a challenging trade-off between device efficiency and spatial footprint. To address this issue, researchers are focusing on the integration of nanoscale materials into photonic platforms, offering a novel approach to enhance device performance while reducing spatial requirements. These developments are of paramount importance in both classical and quantum information technologies, potentially revolutionizing the industry. In this review, we explore the latest endeavors in hybrid photonic platforms leveraging the combination of integrated silicon photonic platforms and nanoscale materials, allowing for the unlocking of increased device efficiency and compact form factors. Finally, we provide insights into future developments and the evolving landscape of hybrid integrated photonic nanomaterial platforms.

Published
2024
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9. Solid-State Color Centers for Single-Photon Generation

Author

Greta Andrini, Francesco Amanti, Fabrizio Armani, Vittorio Bellani, Vincenzo Bonaiuto, Simone Cammarata, Matteo Campostrini, Thu Ha Dao, Fabio De Matteis, Valeria Demontis, Giovanni Di Giuseppe, Sviatoslav Ditalia Tchernij, Simone Donati, Andrea Fontana, Jacopo Forneris, Roberto Francini, Luca Frontini, Roberto Gunnella, Simone Iadanza, Ali Emre Kaplan, Cosimo Lacava, Valentino Liberali, Francesco Marzioni, Elena Nieto Hernández, Elena Pedreschi, Paolo Piergentili, Domenic Prete, Paolo Prosposito, Valentino Rigato, Carlo Roncolato, Francesco Rossella, Andrea Salamon, Matteo Salvato, Fausto Sargeni, Jafar Shojaii, Franco Spinella, Alberto Stabile, Alessandra Toncelli, Gabriella Trucco, and Valerio Vitali

Subjects
color centers, solid state, diamond, silicon carbide, hBN, nitrides, Applied optics. Photonics, TA1501-1820
Abstract

Single-photon sources are important for integrated photonics and quantum technologies, and can be used in quantum key distribution, quantum computing, and sensing. Color centers in the solid state are a promising candidate for the development of the next generation of single-photon sources integrated in quantum photonics devices. They are point defects in a crystal lattice that absorb and emit light at given wavelengths and can emit single photons with high efficiency. The landscape of color centers has changed abruptly in recent years, with the identification of a wider set of color centers and the emergence of new solid-state platforms for room-temperature single-photon generation. This review discusses the emerging material platforms hosting single-photon-emitting color centers, with an emphasis on their potential for the development of integrated optical circuits for quantum photonics.

Published
2024
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10. Quantum Information with Integrated Photonics

Author

Paolo Piergentili, Francesco Amanti, Greta Andrini, Fabrizio Armani, Vittorio Bellani, Vincenzo Bonaiuto, Simone Cammarata, Matteo Campostrini, Samuele Cornia, Thu Ha Dao, Fabio De Matteis, Valeria Demontis, Giovanni Di Giuseppe, Sviatoslav Ditalia Tchernij, Simone Donati, Andrea Fontana, Jacopo Forneris, Roberto Francini, Luca Frontini, Roberto Gunnella, Simone Iadanza, Ali Emre Kaplan, Cosimo Lacava, Valentino Liberali, Francesco Marzioni, Elena Nieto Hernández, Elena Pedreschi, Domenic Prete, Paolo Prosposito, Valentino Rigato, Carlo Roncolato, Francesco Rossella, Andrea Salamon, Matteo Salvato, Fausto Sargeni, Jafar Shojaii, Franco Spinella, Alberto Stabile, Alessandra Toncelli, Gabriella Trucco, and Valerio Vitali

Subjects
quantum information, quantum computation, integrated photonics, quantum processors, quantum technologies, Technology, Engineering (General). Civil engineering (General), TA1-2040, Biology (General), QH301-705.5, Physics, QC1-999, Chemistry, QD1-999
Abstract

Since the 1980s, researchers have taken giant steps in understanding how to use quantum mechanics for solving real problems—for example, making a computer that works according to the laws of quantum mechanics. In recent decades, researchers have tried to develop a platform for quantum information and computation that can be integrated into digital and telecom technologies without the need of a cryogenic environment. The current status of research in the field of quantum integrated photonics will be reviewed. A review of the most common integrated photonic platforms will be given, together with the main achievements and results in the last decade.

Published
2023
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15. Characterization of an Associative Memory Chip in 28 nm CMOS Technology.

Author

Alberto Annovi, Giovanni Calderini, Stefano Capra, Bruno Checcucci, Francesco Crescioli, Francesco De Canio, Giacomo Fedi, Luca Frontini, Maroua Garci, Christos Gentsos, Takashi Kubota, Valentino Liberali, Fabrizio Palla, Jafar Shojaii, Calliope-Louisa Sotiropoulou, Alberto Stabile, Gianluca Traversi, and Sebastien Viret

Published
2018
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34. Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance

Author

Valentina Ciriani, Elena Ioana Vatajelu, Dan Alexandrescu, Luca Frontini, Mircea R. Stan, Muhammed Ceylan Morgul, Onur Tunali, Mustafa Altun, Csaba Andras Moritz, Lorena Anghel, Istanbul Technical University (ITÜ), Università degli Studi di Milano = University of Milan (UNIMI), SPINtronique et TEchnologie des Composants (SPINTEC), Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes (UGA), Architectures and Methods for Resilient Systems (TIMA-AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), University of Massachusetts [Amherst] (UMass Amherst), University of Massachusetts System (UMASS), University of Virginia, iROc Technologies (IROC TECHNOLOGIES), Cadence Connection-EDA Consortium-FSA-Cubic Micro, Università degli Studi di Milano [Milano] (UNIMI), Architectures and Methods for Resilient Systems (AMfoRS ), and University of Virginia [Charlottesville]

Subjects
Computer science, Circuit design, Fault tolerance, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Memristor, 021001 nanoscience & nanotechnology, Fault (power engineering), Computer Science Applications, Power optimization, law.invention, PACS 8542, Logic synthesis, CMOS, law, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, Crossbar switch, 0210 nano-technology, ComputingMilieux_MISCELLANEOUS, Hardware_LOGICDESIGN
Abstract

Nano-crossbar arrays have emerged to achieve high performance computing beyond the limits of current CMOS with the drawback of higher fault rates. They offer area and power efficiency in terms of their easy-to-fabricate and dense physical structures. They consist of regularly placed crosspoints as computing elements, which behave as diode, memristor, field effect transistor, or novel four-terminal switching devices. In this study, we establish a complete design framework for crossbar circuits explaining and analyzing every step of the process. We comparatively elaborate on these technologies in the sense of their capabilities for computation regarding area including a new logic synthesis technique for memristors, fault tolerance including a novel paradigm for four-terminal devices, delay, and power consumption. As a result, this study introduces a synthesis methodology that considers basic technology preference for switching crosspoints and fault rates of the given crossbar as well as their effects on performance metrics including power, delay, and area.

Published
2021
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36. Design and test of silicon photonic Mach-Zehnder interferometers for data transmission applications

Author

Vincenzo Bonaiuto, Andreas Mai, Paolo Prosposito, A. Salamon, Giovanni Paulozzi, Fabio De Matteis, Alberto Stabile, Luca Frontini, Luca Colavecchi, Valentino Liberali, Fausto Sargeni, Roberto Gunnella, Gaetano Salina, Patrick Steglich, Matteo Salvato, Davide Badoni, and Giovanni Di Giuseppe

Subjects
Power transmission, Settore FIS/03, Silicon photonics, Materials science, Silicon, business.industry, Physics::Optics, chemistry.chemical_element, Silicon on insulator, Mach–Zehnder interferometer, Chip, optical data transmission, chemistry, Hardware_INTEGRATEDCIRCUITS, Mach-Zehnder interferometer, Optoelectronics, Photonics, business, Data transmission
Abstract

In this paper we describe the layout of a Silicon Photonic chip, composed of two different Mach-Zehnder interferometers realized with SOI technology; we report the results obtained from the electromagnetic simulations, that have been performed splitting the MZIs in multiple components to extract the power transmission parameters and we also report the result of the measurements taken in lab. The aim of this study is to demonstrate the ability the Silicon photonics devices have to become the new generation of digital interconnects.

Published
2020
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37. Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices

Author

Anna Bernasconi, Valentina Ciriani, Lorena Anghel, Luca Frontini, Gabriella Trucco, Ioana Vatajelu, SPINtronique et TEchnologie des Composants (SPINTEC), Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes (UGA), Dipartimento di Informatica [Pisa], University of Pisa - Università di Pisa, Dipartimento di Informatica, Università degli Studi di Milano, Italy (UNIMI), Istituto Nazionale di Fisica Nucleare, Sezione di Milano (INFN), Istituto Nazionale di Fisica Nucleare (INFN), Architectures and Methods for Resilient Systems (AMfoRS ), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Università degli Studi di Milano = University of Milan (UNIMI), and Architectures and Methods for Resilient Systems (TIMA-AMfoRS )

Subjects
Switching lattices, Emerging technologies, Computer science, Defect avoidance, Fault injection, Fault tolerance, Stuck-at-fault model, 020208 electrical & electronic engineering, 02 engineering and technology, Crossbar array, 020202 computer hardware & architecture, Stuck-at fault, PACS 8542, Computer engineering, Lattice (order), 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Boolean function, AND gate, Logic optimization
Abstract

International audience; Switching lattices are two-dimensional arrays composed of two or four-terminals switches organized as a crossbar array. The idea of using regular two-dimensional arrays of switches for Boolean function implementation was proposed by Akers in 1972. Recently, with the advent of a variety of emerging nanoscale technologies, lattices have found a renewed interest. Emerging technologies allow more complex function integration, thanks to their smaller sizes and advanta geous properties such as zero leakage current, capability to retain data when in power-off state, and almost unlimit edendurance, to name just a few appealing features. Also, implementation of new computing paradigms combining memory and logic becomes possible. However, emerging technologies show a non-negligible defect ratio and higher sensitivity to process and environment variations. The reliability challenges in adopting these technologies need to be investigated. In this paper, we analyze the resilience of switching lattices to stuck-at-fault model (SAF). We first identify the critical switches through an elaborated sensitivity methodology and extensive analysis of the lattice. Next, we propose several techniques to improve lattice resilience in the face of these types of faults, that can be implemented after lattice logic optimization steps.

Published
2020
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38. Testability of Switching Lattices in the Cellular Fault Model

Author

Valentina Cieiani, Anna Bernasconi, and Luca Frontini

Subjects
Switching lattices, Computer science, 020208 electrical & electronic engineering, Semiconductor device modeling, testability, 02 engineering and technology, Topology, 020202 computer hardware & architecture, cellular fault model, Lattice (order), 0202 electrical engineering, electronic engineering, information engineering, Fault model, logic synthesis, Testability
Abstract

A switching lattice is a two-dimensional array of four-terminal switches implemented in its cells. Each switch is linked to the four neighbors and is connected with them when the switch is ON, or is disconnected when the switch is OFF. Recently, with the advent of a variety of emerging nanoscale technologies based on regular arrays of switches, lattices of multi-terminal switches, originally introduced by Akers in 1972, have found a renewed interest. In this paper, the testability under the Cellular Fault Model (CFM) of switching lattices is defined and analyzed. Moreover, some techniques for improving the testability of lattices are discussed and experimentally evaluated.

Published
2020

39. Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model

Author

Ioana Vatajelu, Luca Frontini, Lorena Anghel, Gabriella Trucco, Anna Bernasconi, and Valentina Ciriani

Subjects
010302 applied physics, Switching lattices, Computer science, fault tolerance, Stuck-At-Fault Model, Fault tolerance, 02 engineering and technology, Topology, 01 natural sciences, 020202 computer hardware & architecture, Stuck-at fault, Fault mitigation, Lattice (order), 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Preprocessor, Crossbar switch, Boolean function, Logic optimization
Abstract

Switching lattices are two-dimensional arrays composed by four-terminal switches (crossbar arrays). The idea of using regular two-dimensional arrays of switches to implement Boolean functions was proposed by Akers in 1972. Recently, with the advent of a variety of emerging nanoscale technologies, lattices have found a renewed interest. Switching lattices can have a non-negligible defective ratio. In this paper, we analyze the fault tolerance of switching lattices under the stuck-at-fault model (SAFM). We first identify the critical switches with a sensitivity analysis of the lattice. We then propose some techniques to improve the resilience to faults, which are implemented as a post preprocessing step after logic optimization.

Published
2020

40. The first ASIC prototype of a 28 nm time-space front-end electronics for real-time tracking

Author

Jafar Shojaii, Adriano Lai, Corrado Napoli, Alberto Stabile, Valentino Liberali, Luca Frontini, Lorenzo Piccolo, Massimo Barbaro, Angelo Rivetti, Stefano Sonedda, Luigi Casu, and S. Cadeddu

Subjects
Discriminator, CMOS, Application-specific integrated circuit, Computer science, business.industry, Amplifier, Electrical engineering, business, Tracking (particle physics), Communication channel, Block (data storage), Electronic circuit
Abstract

A front-end ASIC for 4D tracking is presented. The prototype includes the block necessary to build a pixel front-end chain for timing measurement, as independent circuits. The architecture includes a charge-sensitive amplifier, a discriminator with programmable threshold, and a time- to-digital converter. The blocks were designed with target specifications in mind including: an area occupation of 55 μm × 55 μm, a power consumption tens of micro ampere per channel and timing a resolution of at least 100 ps. The prototype has been designed and integrated in 28 nm CMOS technology. The presented design is part of the TimeSpOT project which aims to reach a high-resolution particle tracking both in space and in time, in order to provide front-end circuitry suitable for next generation colliders.

Published
2020

41. A 28-nm CMOS pixel read-out ASIC for real-time tracking with time resolution below 20 ps

Author

Lorenzo Piccolo, Angelo Rivetti, Alberto Stabile, Luca Frontini, S. Cadeddu, Adriano Lai, and Valentino Liberali

Subjects
Discriminator, Pixel, Semiconductor device modeling, business.industry, Computer science, Layout, ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION, Power budget, Fabrication, Semiconductor device modeling, Fabrication, Power system measurements, Layout, Prototypes, Feature extraction, Real-time systems, CMOS, Application-specific integrated circuit, Prototypes, Feature extraction, Power system measurements, business, Real-time systems, Computer hardware, Charge amplifier, Power density
Abstract

We present the development of a test ASIC, named Timespot1, designed in CMOS 28-nm technology, featuring a 32x32 pixel matrix and a pitch of 55 μm, The ASIC is conceived as the first prototype in a series, capable to read-out pixels with timing capabilities in the range of 30 ps and below. Each pixel is endowed with a charge amplifier, a discriminator and a Time-to-Digital-Converter, capable of time resolutions below 20 ps and read-out rates (per pixel) around 3 MHz. The timing performance are obtained respecting a power budget of about 50 µW per pixel, corresponding to a power density of approximately 2 W/cm2• This feature makes the Timespot1 approach an interesting solution for vertex detectors of the next generation of colliders, where high space and time resolutions will be mandatory requirements to cope with the huge amount of tracks per event to be detected and processed.

Published
2020

42. A Pixel Read-Out Front-End in 28 nm CMOS with Time and Space Resolution

Author

Massimo Barbaro, Jafar Shojaii, Alberto Stabile, Luca Frontini, S. Cadeddu, Francesco De Canio, Adriano Lai, Angelo Rivetti, Stefano Sonedda, Lorenzo Piccolo, Corrado Napoli, Luigi Casu, Gianluca Traversi, and Valentino Liberali

Subjects
Pixel, Computer science, business.industry, Bandwidth (signal processing), Pixel detector, time resolution, tracking, Chip, Settore ING-INF/01 - Elettronica, Front and back ends, CMOS, Picosecond, Electronics, business, Radiation hardening, Computer hardware
Abstract

Future high luminosity colliders will require front-end electronics with unprecedented performance, both in space and time resolution (tens of micrometers and tens of picoseconds) and in radiation hardness (tens of megagray). Moreover, the high number of events will generate an enormous quantity of data (some terabits per second), and the limited bandwidth requires to perform data selection as close as possible to the front-end stage, to reduce the amount of data transmitted and stored for off-line analysis.The TimeSpOT (TIME and SPace real-time Operating Tracker) project, funded by INFN, is developing a complete demonstrator of a tracking device including all the features needed for future high luminosity experiments.In this presentation, we describe the first prototype of the readout electronics in 28 nm CMOS technology. The modules of the front-end circuitry have been designed and integrated in a test chip, which will allow us to characterize each block separately, and to connect them in a processing chain to evaluate the overall performance.

Published
2019
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43. Design of Non-Metastable SRAM Cells in 28 nm CMOS Technology

Author

Alberto Stabile, Luca Frontini, Valentino Liberali, Francesco Crescioli, Laboratoire de Physique Nucléaire et de Hautes Énergies (LPNHE (UMR_7585)), and Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Paris Diderot - Paris 7 (UPD7)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Materials science, Layout, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, law.invention, Computer Science::Hardware Architecture, MOSFET, Computer Science::Emerging Technologies, law, Metastability, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Hardware_INTEGRATEDCIRCUITS, Static random-access memory, Physics::Atomic Physics, [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det], 010302 applied physics, business.industry, SRAM cells, Transistor, Sram cell, Monte Carlo methods, CMOS technology, 020202 computer hardware & architecture, CMOS, Optoelectronics, business
Abstract

International audience; This paper presents the design of an SRAM cell in 28 nm, specifically designed to avoid metastability at start-up. Metastable operation is avoided by unbalancing the size of transistors. Extensive simulations have confirmed that the probability of metastable operation is greatly reduced.

Published
2019
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44. Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC

Author

M. Garcia-Sciveres, R. Gaglione, P. Breugnon, Fabian Hügging, R. Beccherle, Fabio Morsani, Steven Bell, Stefano Bonaldo, D. Dzahini, Duccio Abbaneo, Luca Pacher, O. Le Dortz, Ta-Wei Wang, Mohsine Menouni, Guido Magazzu, M. Vogt, Francesco Crescioli, T. Benka, G. Neue, M. Da Rocha Rolo, E. Conti, F. Loddo, L. M. Jara Casas, Sally Seidel, Alexandre Rozanov, V. Gromov, G. Marzocca, Norbert Wermes, Fabrizio Palla, Tom Zimmerman, Valentino Liberali, M. Standke, Angelo Rivetti, Pisana Placidi, Mauro Menichelli, V. Kafka, F. De Canio, A. Paterno, Simone Gerardin, Z. Janoska, A. Krieger, V. Wallangen, Gianluca Traversi, Ennio Monteil, Y. Dieter, Alessandro Paccagnella, Alberto Stabile, Dario Gnani, B. Van Eijk, Serena Mattiazzo, Farah Fahim, Marco Bomben, D. Vogrig, Marta Bagatin, B. Nachman, Marlon Barbero, C. Renteira, S. Godiot, E. M. S. Jimenez, G. Marchiori, T. Liu, P. Pangaud, Luca Frontini, D. Gajanana, F. E. Rarbi, Scott Thomas, M. Karagounis, Hans Krüger, P. Rymaszewski, K. Papadopoulou, Tomasz Hemperek, Richard B. Lipton, Nicola Bacchetta, M.L. Prydderch, A. Andreazza, S. Poulios, Cristoforo Marzocca, R. Kluit, Konstantin Androsov, David-leon Pohl, Valerio Re, K. Moustakas, Sandeep Miryala, A. Vitkovskiy, Timon Heim, G. Calderini, F. Licciulli, Jesper Roy Christiansen, R. Carney, G. M. Bilei, M. Minuti, D. Fougeron, Lodovico Ratti, G. Deptuch, F. R. Palomo, G. De Robertis, G. Dellacasa, Luigi Gaioni, M. Daas, Martin Hoeferkamp, E. Lopez-Morillo, Massimo Manghisoni, G. Mazza, A. Stiller, S. Orfanelli, S. Marconi, Ivan Vila, M. Marcisovsky, C. Vacchi, E. Riceputi, Vaclav Vrba, Natale Demaria, L. Tomasek, D. C. Christian, J. Hoff, Fernando Muñoz, Dario Bisello, Miroslav Havranek, Centre de Physique des Particules de Marseille (CPPM), Aix Marseille Université (AMU)-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS), Laboratoire de Physique Subatomique et de Cosmologie (LPSC), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Laboratoire d'Annecy de Physique des Particules (LAPP), and Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
Computer science, readout electronics, sensors, radiation hardness, Settore ING-INF/01 - Elettronica, 01 natural sciences, Signal, CMOS image sensors, nuclear electronics, particle tracking, 030218 nuclear medicine & medical imaging, 03 medical and health sciences, Microelectronics, 0302 clinical medicine, Design objective, mixed analogue-digital integrated circuits, 0103 physical sciences, [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det], [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Large Hadron Collider, Pixel, 010308 nuclear & particles physics, business.industry, Settore FIS/01 - Fisica Sperimentale, Detector, Mixed-signal integrated circuit, Chip, position sensitive particle detectors, CMOS, silicon radiation detectors, business, Computer hardware
Abstract

International audience; The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50×50 or 25× 100 µm2) and large pixel chip size (~2x2 cm2), high hit rate (3 GHz/cm2), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (~12.5 µs), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400×192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discussed

Published
2018
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45. A very compact population count circuit for associative memories

Author

Valentino Liberali, Alberto Stabile, and Luca Frontini

Subjects
Population count, 010308 nuclear & particles physics, Transistor, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Content-addressable memory, 01 natural sciences, New population, 020202 computer hardware & architecture, law.invention, CMOS, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Control logic, Associative property, Hardware_LOGICDESIGN
Abstract

This paper presents a new population count circuit, suitable for very scaled CMOS technologies. The proposed circuit is optimized for the total area, instead of the number of transistors, in order to take full advantage of deeply scaled technology features. Moreover, the circuit is purely combinational, in order to simplify the control logic. The envisaged solution has been designed in a commercial 28 nm CMOS technology, and the design of the layout has been validated. The total silicon area is 14.04 × 0.905 μm2 for a counter from 0 to 8.

Published
2018
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46. Characterization of an Associative Memory Chip in 28 nm CMOS Technology

Author

Giacomo Fedi, Maroua Garci, Christos Gentsos, Francesco Crescioli, Jafar Shojaii, Gianluca Traversi, Alberto Annovi, Francesco De Canio, Alberto Stabile, Valentino Liberali, Luca Frontini, S. Capra, Sébastien Viret, Fabrizio Palla, Takashi Kubota, B. Checcucci, G. Calderini, Calliope Louisa Sotiropoulou, Laboratoire de Physique Nucléaire et de Hautes Énergies (LPNHE (UMR_7585)), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Paris Diderot - Paris 7 (UPD7)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS), Institut de Physique Nucléaire de Lyon (IPNL), Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS)-Université de Paris (UP), Centre National de la Recherche Scientifique (CNRS)-Université Claude Bernard Lyon 1 (UCBL), and Université de Lyon-Université de Lyon-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)

Subjects
[PHYS]Physics [physics], 010308 nuclear & particles physics, business.industry, Computer science, Content-addressable memory, Chip, 01 natural sciences, Settore ING-INF/01 - Elettronica, 030218 nuclear medicine & medical imaging, 03 medical and health sciences, 0302 clinical medicine, CMOS, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, Field-programmable gate array, business, Computer hardware
Abstract

International audience; This paper presents the characterization of the new Associative Memory chip (version 7) designed and fabricated in 28 nm CMOS. The design aims at: enhancing links from/to FPGAs; increasing bandwidth thanks to full custom LVDS transceivers; and reducing power consumption and silicon area by means of new memory cells designed with full-custom approach. The design was submitted in December 2016; the prototypes were fabricated and packaged in a 17 × 17 Ball Grid Array (BGA) standalone package. Prototype characterization confirms the chip functionality. The final chip will be assembled in a System In Package (SiP) together with a bare FPGA die.

Published
2018
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47. R&D on Electronic Devices and Circuits for the HL-LHC

Author

Valentino Liberali, M. Citterio, Attilio Andreazza, Jafar Shojaii, Alberto Stabile, Luca Frontini, and C. Meroni

Subjects
Large Hadron Collider, Pixel, Physics::Instrumentation and Detectors, business.industry, Computer science, High Luminosity Large Hadron Collider, Integrated circuit, law.invention, CMOS, law, Electronic engineering, Microelectronics, Electronics, business, Electronic circuit
Abstract

The paper presents the research activities in microelectronics, aiming at improving detection capabilities of future High Energy Physics (HEP) experiments. The output of this research will be the development of novel integrated circuits, to enhance the performance of electronic systems for the High Luminosity Large Hadron Collider (HL-LHC). In particular, the main research activities are focused on monolithic pixel arrays, on new digital architectures for pixel readout in 65 nm CMOS, and on associative memories for several interdisciplinary applications, such as fast tracking for trigger, DNA sequencing, magnetic resonance and image analysis.

Published
2018
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48. Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Upgrades

Author

Fabrizio Palla, Carla Vacchi, Attilio Andreazza, Jorgen Christiansen, E. Conti, Vratislav Kafka, Ruud Kluit, Vladimir Gromov, Esther Jiménez, Lodovico Ratti, Mark Prydderch, Simone Gerardin, Serena Mattiazzo, Zdenko Janoska, Bob Van Eijk, Mohsine Menouni, Tom Zimmerman, Alessandro Paccagnella, Luis Miguel Jara Casas, Piotr Rymazewski, Nicola Bacchetta, F. R. Palomo, Ivan Vila, Timon Heim, Patrick Breugnon, Stephanie Godiot, Stamatis Poulios, Tianyang Wang, Katerini Papadopoulou, Norbert Wermes, E. Riceputi, Veronica Wallangen, Marco Vogt, Stephen Thomas, Massimo Minuti, Marta Bagatin, Renaud Gaglione, Farah Fahim, Giovanni Mazza, F. Loddo, Angelo Rivetti, Valentino Liberali, Tomas Benka, S. Orfanelli, Michal Marcisovsky, Alberto Stabile, Duccio Abbaneo, M. Karagounis, Natale Demaria, Amanda Krieger, F. Munoz, Manuel Dionisio Da Rocha Rolo, Gianluca Traversi, Ennio Monteil, Maurice Garcia-Sciveres, Luca Frontini, Luca Pacher, Dario Bisello, B. Nachman, Gordon Neue, Rebecca Carney, Patrick Pangaud, Fatah Ellah Rarbi, Giuseppe De Robertis, Cristoforo Marzocca, G. Calderini, Fabian Huegging, Stefano Bonaldo, Alexandre Rozanov, Gian Mario Bilei, Francesco Corsi, Francesco Crescioli, Miroslav Havranek, S. Marconi, F. Licciulli, Konstantin Androsov, Olivier Le Dortz, Fabio Morsani, A. Paterno, Sally Seidel, Dario Gnani, James Hoff, Pisana Placidi, D. Vogrig, Sandeep Miryala, Stephen Jean-Marc Bell, Hans Krueger, Lukas Tomasek, Mauro Menichelli, Valerio Re, David Charles Christian, Tomasz Hemperek, Marco Bomben, Marlon Barbero, Luigi Gaioni, F. Ciciriello, Martin Robert Hoeferkamp, Arseniy Vitkovskiy, Daniel Dzahini, Deepak Gajanna, E. Lopez-Morillo, Massimo Manghisoni, Cesar Renteira, Roberto Beccherle, G. Dellacasa, Giovanni Marchiori, Gregorz Deptuch, Vaclav Vrba, Francesco De Canio, Denis Fougeron, Guido Magazzu, Centre de Physique des Particules de Marseille (CPPM), Aix Marseille Université (AMU)-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS), Laboratoire de Physique Nucléaire et de Hautes Énergies (LPNHE (UMR_7585)), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS)-Université de Paris (UP), Laboratoire de Physique Subatomique et de Cosmologie (LPSC), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), Université Grenoble Alpes (UGA), Laboratoire d'Annecy de Physique des Particules (LAPP), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), RD53, Centre National de la Recherche Scientifique (CNRS)-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Aix Marseille Université (AMU), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Paris Diderot - Paris 7 (UPD7)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Institut Polytechnique de Grenoble - Grenoble Institute of Technology-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Laboratoire d'Annecy de Physique des Particules (LAPP/Laboratoire d'Annecy-le-Vieux de Physique des Particules), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS), and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)

Subjects
Computer science, High radiation, Integrated circuit design, 01 natural sciences, 030218 nuclear medicine & medical imaging, 03 medical and health sciences, 0302 clinical medicine, semiconductor detector: pixel, Atlas (anatomy), RD53 collaboration, 0103 physical sciences, medicine, Pixel matrix, [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det], Detectors and Experimental Techniques, High rate, Multidisciplinary, Pixel, 010308 nuclear & particles physics, business.industry, CMS, 65 nm CMOS pixel chip, ATLAS and CMS phase 2 upgrades, ATLAS, Chip, medicine.anatomical_structure, CMOS, integrated circuit: design, electronics: readout, business, Computer hardware, 65 nm CMOS pixel chip, RD53 collaboration, ATLAS and CMS phase 2 upgrades
Abstract

International audience; RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments.

Published
2017
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49. A low-power and high-density Associative Memory in 28 nm CMOS technology

Author

Seyed Ruhollah Shojaii, Takashi Kubota, Francesco Crescioli, Valentino Liberali, Gianluca Traversi, Pierluigi Luciano, Fabrizio Palla, G. Calderini, Calliope Louisa Sotiropoulou, Alberto Annovi, Alberto Stabile, Luca Frontini, Francesco De Canio, Laboratoire de Physique Nucléaire et de Hautes Énergies (LPNHE (UMR_7585)), and Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Paris Diderot - Paris 7 (UPD7)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Engineering, 02 engineering and technology, Integrated circuit design, fabrication, silicon in package, reduced power consumption, Circuits and systems, Settore ING-INF/01 - Elettronica, Memory cell, Ball grid array, 0202 electrical engineering, electronic engineering, information engineering, Hardware_INTEGRATEDCIRCUITS, low-power associative memory, ball grid array standalone package, ball grid arrays, [INFO]Computer Science [cs], Analytical models, Computer architecture, [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det], Field-programmable gate array, Cams, FPGA, field programmable gate arrays, Clocks, density, business.industry, memory cell area density, electronics, Associative memory, 020208 electrical & electronic engineering, size 28 nm, power consumption, memory architecture, AM chip design, Content-addressable memory, Chip, CMOS technology, CMOS, Large Hadron Collider, Embedded system, high-density associative memory, integrated circuit: design, CMOS memory circuits, low-power electronics, Signal integrity, business, LVDS drivers, Computer hardware
Abstract

International audience; In this paper we present a new Associative Memory (AM) chip designed in the 28 nm TSMC HPL technology. Two of the main characteristics of the new chip are reduced power consumption and an increased memory cell area density by the use of two newly designed memory cell technologies. The aim of the new chip is to test the new technologies with realistic front-end functions. The integration of the AM and FPGA is also enhanced. In addition, LVDS drivers and receivers are implemented to strengthen the signal integrity of the I/Os. The new AM chip design is submitted for the fabrication. The die will be packaged in a 17 × 17 Ball Grid Array (BGA) standalone package with a Silicon In Package (SiP) structure mounting AM dies and a bare die FPGA.

Published
2017
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50. Population count circuits for Associative Memories: A comparison study

Author

Valentino Liberali, Alberto Stabile, and Luca Frontini

Subjects
Flexibility (engineering), Matching (graph theory), Computer science, Transistor, Hardware_PERFORMANCEANDRELIABILITY, law.invention, Set (abstract data type), Transistor count, law, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, State (computer science), Associative property, Hardware_LOGICDESIGN, Electronic circuit
Abstract

This paper proposes a novel population count circuit for Associative Memories (AM)s. Currently, AM chips requires a large number of silicon area for the population count circuitry. For this reason, is necessary an optimization in terms of area for the future AM devices to have a better memory density. A population count circuit counts how many blocks of the AM are in a matching state. If the count sum is greater than a preconfigured threshold, the output wire is set to ‘1’, otherwise is set to ‘0’. In the existing circuits there are, in addition, several control signals that are used to increase the circuit flexibility, but these controls require a large number of transistors and interconnections. The purpose of the proposed circuit is to reduce the number of transistors and interconnections complexity, with the final aim to reduce the occupied silicon area.

Published
2017
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